OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Features
•
Output voltage 5 V ±2%
•
Current capability 200 mA
•
Ultra low current consumption
•
Very low dropout voltage
•
Watchdog circuit for monitoring a microprocessor
with programmable load-dependent activating threshold
•
Reset circuit sensing the output voltage
with programmable switching threshold and delay time
•
Reset output active low down to VQ = 1 V
•
Separated reset and watchdog output
•
Excellent line transient robustness
•
Maximum input voltage VI = -42 V to +45 V
•
Reverse polarity protection
•
Short circuit protected
•
Overtemperature shutdown
•
Automotive temperature range Tj = -40°C to +150°C
•
Available in a small thermally enhanced PG-SSOP-14 package
•
Green Product (RoHS Compliant)
Potential applications
General automotive applications.
Product validation
Qualified for automotive applications. Product validation according to AEC-Q100.
Description
The OPTIREG™ Linear TLE4678 is a monolithic integrated low dropout fixed output voltage regulator for loads
up to 200 mA. An input voltage of up to 45 V is regulated to an output voltage of 5 V. The integrated reset and
watchdog function, as well as several protection circuits, combined with a wide operating temperature range
offered by the TLE4678GM make it suitable for supplying microprocessor systems in automotive
environments.
Datasheet
www.infineon.com/OPTIREG-Linear
1
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
The watchdog circuitry will be disabled in case the output current drops below a programmable threshold,
enabling a microcontroller to switch to stand-by mode. Modifying the reset threshold is possible by an
optional resistor divider.
The TLE4678GM is available in a PG-DSO-14 package which makes it pin-compatible to the TLE4278, as well as
in a small thermally enhanced PG-SSOP-14 exposed pad package.
Type
Package
Marking
TLE4678GM
PG-DSO-14
TLE4678GM
TLE4678EL
PG-SSOP-14
TLE4678
Datasheet
2
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Table of contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
2.2
2.3
2.4
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin assignment PG-DSO-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin definitions and functions PG-DSO-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin assignment PG-SSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin definitions and functions PG-SSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3.1
3.2
3.3
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
4.1
4.2
4.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical characteristics voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical performance characteristics voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
5.1
5.2
Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical characteristics current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Typical performance characteristics current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6
6.1
6.2
6.3
Reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical characteristics reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical performance characteristics reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
21
23
7
7.1
7.2
7.3
Watchdog function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical characteristics watchdog function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical performance characteristics standard watchdog function . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
24
27
29
8
8.1
8.2
8.2.1
8.2.2
8.3
8.4
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selection of external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
30
31
31
31
32
33
9
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Datasheet
3
5
5
5
6
6
11
11
12
14
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Block Diagram
1
Block Diagram
For details on the circuit blocks see the respective section in this datasheet.
TLE 4678
I
Q
Regulated Output Voltage
CQ
RO
Protection
Circuits
Bandgap
Reference
WO
Reset
and
Watchdog
Generator
WI
RADJ
WADJ
GND
Load
e. g.
Micro
Controller
XC22xx
GND
Blo ckDia gram _AppCircuit1 .vsd
Supply
D
CD
Figure 1
Datasheet
Block diagram and simplified application circuit
4
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Pin configuration
2
Pin configuration
2.1
Pin assignment PG-DSO-14
WO
1
14
RO
WADJ
2
13
I
GND
3
12
GND
GND
4
11
GND
GND
5
10
GND
D
6
9
Q
RADJ
7
8
WI
P inout_SO14 .vsd
Figure 2
Pin assignment PG-DSO-14 package
2.2
Pin definitions and functions PG-DSO-14
Pin
Symbol
Function
1
WO
Watchdog output
Open collector output with an internal pull-up resistor to the output Q.
An additional external pull-up resistor to the output Q is optional.
Leave open if the watchdog function is not needed.
2
WADJ
Watchdog activating threshold adjust
An external resistor to GND determines the watchdog activating threshold.
Connect directly to GND for disabling the watchdog.
Connect directly to GND if the watchdog function is not needed.
Connect to output Q via 270 kΩ resistor for permanently activating the watchdog.
3, 4, 5,
GND
10, 11, 12
IC ground
Interconnect the GND pins on PCB.
Connect to heat sink area.
6
D
Reset delay and watchdog timing
Connect a ceramic capacitor D (pin 6) to GND for reset delay and watchdog timing
adjustment.
Leave only open if both the reset and the watchdog function are not needed.
7
RADJ
Reset switching threshold adjust
For reset threshold adjustment connect to a voltage divider from output Q to GND.
For triggering the reset at the internally determined threshold, connect this pin
directly to GND.
Connect directly to GND if the reset function is not needed.
Datasheet
5
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Pin configuration
Pin
Symbol
Function
8
WI
Watchdog input
Positive edge triggered input, usable for microcontroller monitoring.
Connect to GND if the watchdog function is not needed.
9
Q
5 V regulator output
Block to GND with a capacitor close to the IC pins, respecting capacitance and ESR
requirements given in the Chapter 3.2.
13
I
Regulator input and IC supply
For compensating line influences, a capacitor to GND close to the IC pins is
recommended.
14
RO
Reset output
Open collector output with an internal pull-up resistor to the output Q.
An additional external pull-up resistor to the output Q is optional.
Leave open if the reset function is not needed.
2.3
Pin assignment PG-SSOP-14
WO
n.c.
WADJ
GND
D
n.c.
RADJ
1
2
3
4
5
6
7
14
13
12
11
10
9
8
RO
n.c.
I
n.c.
Q
n.c.
WI
Pinout_SSOP14.vsd
Figure 3
Pin assignment PG-SSOP-14 package
2.4
Pin definitions and functions PG-SSOP-14
Pin
Symbol
Function
1
WO
Watchdog output
Open collector output with an internal pull-up resistor to the output Q.
An additional external pull-up resistor to the output Q is optional.
Leave open if the watchdog function is not needed.
3
WADJ
Watchdog activating threshold adjust
An external resistor to GND determines the watchdog activating threshold.
Connect directly to GND for disabling the watchdog.
Connect directly to GND if the watchdog function is not needed.
Connect to output Q via 270 kΩ resistor for permanently activating the watchdog.
Datasheet
6
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Pin configuration
Pin
Symbol
Function
4
GND
IC ground
Interconnect with the exposed pad and heatsink area on PCB.
5
D
Reset delay and watchdog timing
Connect a ceramic capacitor D (pin 5) to GND for reset delay and watchdog timing
adjustment.
Leave only open if both, the reset and the watchdog function are not needed.
7
RADJ
Reset switching threshold adjust
For reset threshold adjustment connect to a voltage divider from output Q to GND.
For triggering the reset at the internally determined threshold, connect this pin
directly to GND.
Connect directly to GND if the reset function is not needed.
8
WI
Watchdog input
Positive edge triggered input, usable for microcontroller monitoring.
Connect to GND if the watchdog function is not needed.
10
Q
5 V regulator output
Block to GND with a capacitor close to the IC pins, respecting capacitance and ESR
requirements given in the Chapter 3.2.
12
I
Regulator input and IC supply
For compensating line influences, a capacitor to GND close to the IC pins is
recommended.
14
RO
Reset output
Open collector output with an internal pull-up resistor to the output Q.
An additional external pull-up resistor to the output Q is optional.
Leave open if the reset function is not needed.
2, 6, 9,
11, 13
n. c.
Internally not connected
Connection to GND on PCB recommended.
Exposed pad
Datasheet
Connect to heat sink area on PCB. Interconnect with GND.
7
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
General product characteristics
3
General product characteristics
3.1
Absolute maximum ratings
Table 1
Absolute maximum ratings1)
Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Voltage rating
Regulator input and IC supply I VI
-42
–
45
V
–
P_4.1.1
Regulator output Q
VQ
-1
–
7
V
–
P_4.1.2
Reset output RO
VRO
-0.3
–
7
V
–
P_4.1.3
Reset delay and watchdog
timing D
VD
-0.3
–
7
V
–
P_4.1.4
Reset Switching threshold
adjust RADJ
VRADJ
-0.3
–
7
V
–
P_4.1.5
Watchdog input WI
VWI
-0.3
–
7
V
–
P_4.1.6
Watchdog output WO
VWO
-0.3
–
7
V
–
P_4.1.7
-0.3
–
7
V
–
P_4.1.8
Watchdog activating threshold VWADJ
adjust WADJ
Temperature
Junction temperature
Tj
-40
–
150
°C
–
P_4.1.9
Storage temperature
Tstg
-55
–
150
°C
–
P_4.1.10
VESD,HBM -3
–
3
kV
Human Body Model 2)
Pin 13 (Input) only.
P_4.1.11
-2
–
2
kV
P_4.1.12
Human Body Model 2)
All pins except pin 13 (Input)
VESD,CDM -1
–
1
kV
Charged Device Model 3)
ESD susceptibility
ESD resistivity
P_4.1.13
1) Not subject to production test, specified by design.
2) ESD susceptibility, Human Body Model “HBM” according to EIA/JESD 22-A114B.
3) ESD susceptibility, Charged Device Model “CDM” according to EIA/JESD22-C101 or ESDA STM5.3.1.
Note:
Datasheet
Stresses above the ones listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Integrated protection functions are designed to prevent IC destruction under fault conditions
described in the data sheet. Fault conditions are considered as “outside” normal operating range.
Protection functions are not designed for continuous repetitive operation.
8
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
General product characteristics
3.2
Functional range
Table 2
Functional range
Parameter
Symbol
Values
Min.
Unit Note or Test Condition Number
Typ. Max.
Input voltage range for normal
operation
VI(nor)
VQ + Vdr –
45
V
1)
P_4.2.1
Extended input voltage range
VI(ext)
3.3
–
45
V
2)
P_4.2.2
-10
–
20
V/µs ∆VI ≤ 10 V; VI > 9 V;
P_4.2.3
3)
No trigger of WO, RO.
Input voltage transient immunity ∆VI/∆t
Junction temperature
Tj
-40
–
150
°C
–
P_4.2.4
Output capacitor requirements
CQ
10
–
–
µF
4)
P_4.2.5
Ω
5)
P_4.2.6
ESRCQ
–
–
3
1) For specification of the output voltage VQ and the dropout voltage Vdr, see Chapter 4.
2) The output voltage VQ will follow the input voltage, but is outside the specified range.
For details see Chapter 4.
3) Transient measured directly at the input pin. Not subject to production test, specified by design.
4) The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%.
5) Relevant ESR value at f = 10 kHz.
Note:
Datasheet
Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics
table.
9
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
General product characteristics
3.3
Thermal resistance
Note:
This thermal data was generated in accordance with JEDEC JESD51 standards.
For more information, go to www.jedec.org.
Table 3
Thermal resistance
Parameter
Symbol
Values
Unit
Note or Test Condition
Number
Min.
Typ.
Max.
–
27
–
K/W
Pins 3 - 5 and 10 - 12
fixed to TA 1)
P_4.3.1
–
104
–
K/W
Footprint only 1) 2)
P_4.3.2
TLE4678GM (PG-DSO-14)
Junction – Soldering point RthJSP
Junction – Ambient
RthJA
2
–
73
–
K/W
300 mm PCB
heatsink area 1) 2)
P_4.3.3
–
65
–
K/W
600 mm2 PCB
heatsink area 1) 2)
P_4.3.4
–
63
–
K/W
2s2p PCB 1) 3)
P_4.3.5
–
10
–
K/W
1)
TLE4678EL (PG-SSOP-14)
Junction to case
RthJC
Junction to ambient
RthJA
–
140
–
K/W
P_4.3.6
Footprint only
2
1) 2)
P_4.3.7
–
63
–
K/W
300 mm PCB
heatsink area 1) 2)
P_4.3.8
–
53
–
K/W
600 mm2 PCB
heatsink area 1) 2)
P_4.3.9
–
47
–
K/W
2s2p PCB 1) 3)
P_4.3.10
1) Not subject to production test; specified by design.
2) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The product
(chip+package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 × 70 µm Cu).
3) Specified RthJA value is according to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The product
(chip+package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 2 inner copper layers (2 × 70 µm Cu,
2 × 35 µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
Datasheet
10
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Voltage regulator
4
Voltage regulator
4.1
Description voltage regulator
The output voltage VQ is controlled by comparing a portion of it to an internal reference and driving a PNP pass
transistor accordingly. Saturation control as a function of the load current prevents any oversaturation of the
pass element. The control loop stability depends on the output capacitor CQ, the load current, the chip
temperature and the poles/zeros introduced by the integrated circuit. To ensure stable operation, the output
capacitor’s capacitance and its equivalent series resistor ESR requirements given in the table Table 3.2 have
to be maintained. For details see also the typical performance graph “Output Capacitor Series Resistor ESRCQ
vs. Output Current IQ”. Also, the output capacitor shall be sized to buffer load transients.
An input capacitor CI is not needed for the control loop stability, but recommended to buffer line influences.
Connect the capacitors close to the IC terminals.
Protection circuitry prevents the IC as well as the application from destruction in case of catastrophic events.
These safeguards contain output current limitation, reverse polarity protection as well as thermal shutdown
in case of overtemperature.
In order to avoid excessive power dissipation that could never be handled by the pass element and the
package, the maximum output current is decreased at input voltages above VI = 22 V.
The thermal shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g. output
continuously short-circuited) by switching off the power stage. After the chip has cooled down, the regulator
restarts. This leads to an oscillatory behavior of the output voltage until the fault is removed. However, a
junction temperature above 150°C is outside the maximum rating and therefore reduces the IC lifetime.
The TLE4678GM allows a negative supply voltage. However, several small currents are flowing into the IC
increasing its junction temperature. This has to be considered for the thermal design, respecting that the
thermal protection circuit is not operating during reverse polarity condition.
II
Supply
I
+
VI
Q
CQ
CI
Bandgap
Reference
VQ
LOAD
GND
BlockDiagram _VoltageRegulator .vsd
Datasheet
Regulated
Output Voltage
+
Saturation Control
Current Limitation
Temperature
Shutdown
Figure 4
IQ
Block diagram voltage regulator circuit
11
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Voltage regulator
V
VI
VQ,nom
Vdr
VQ
VI(ext),min
dVQ
Iload
≈
CQ
dt
dVQ
IQ,max - Iload
≈
CQ
dt
Diagram_Output-InputVoltage.svg
t
Figure 5
Output voltage vs. input voltage
4.2
Electrical characteristics voltage regulator
Table 4
Electrical characteristics voltage regulator
VI = 13.5 V, Tj = -40°C to +150°C, all voltages with respect to ground, direction of currents as shown in Figure 4
(unless otherwise specified)
Parameter
Output voltage
Symbol
VQ
Values
Min.
Typ.
Max.
4.9
5.0
5.1
Unit
Note or
Test Condition
Number
V
0 mA ≤ IQ ≤ 200 mA;
8 V ≤ VI ≤ 18 V
P_5.2.1
0 mA ≤ IQ ≤ 150 mA;
6 V ≤ VI ≤ 18 V
P_5.2.2
0 mA ≤ IQ ≤ 100 mA;
18 V ≤ VI ≤ 32 V
Tj ≤ 105°C 1) 2)
P_5.2.3
0 mA ≤ IQ ≤ 10 mA;
32 V ≤ VI ≤ 45 V
Tj ≤ 105°C 1) 2)
P_5.2.4
0.3 mA ≤ IQ ≤ 100 mA;
18 V ≤ VI ≤ 32 V 1)
P_5.2.5
0.3 mA ≤ IQ ≤ 10 mA;
32 V ≤ VI ≤ 45 V 1)
P_5.2.6
Load regulation
steady-state
|∆VQ,load| –
5
30
mV
IQ = 1 mA to 150 mA;
VI = 6 V
P_5.2.7
Line regulation
steady-state
|∆VQ,line|
–
5
20
mV
VI = 6 V to 32 V;
IQ = 5 mA
P_5.2.8
60
65
–
dB
fripple = 100 Hz;
Vripple = 1 Vpp 2)
P_5.2.9
–
90
200
mV
IQ = 50 mA 3)
P_5.2.10
–
165
350
mV
IQ = 150 mA 3)
P_5.2.11
Power supply ripple rejection PSRR
Dropout voltage
Vdr = VI - VQ
Vdr
Output current limitation
IQ,max
201
350
500
mA
0 V ≤ VQ ≤ 4.8 V
P_5.2.12
Reverse current
IQ
-1.5
-0.7
–
mA
VI = 0 V; VQ = 5 V
P_5.2.13
Datasheet
12
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Voltage regulator
Table 4
Electrical characteristics voltage regulator (cont’d)
VI = 13.5 V, Tj = -40°C to +150°C, all voltages with respect to ground, direction of currents as shown in Figure 4
(unless otherwise specified)
Parameter
Reverse current
at negative input voltage
Symbol
II
Values
Unit
Note or
Test Condition
Number
Min.
Typ.
Max.
-2
-1
–
mA
VI = -16 V; VQ = 0 V
P_5.2.14
-5
-3
–
mA
VI = -42 V; VQ = 0 V
P_5.2.15
P_5.2.16
Overtemperature shutdown
threshold
Tj,sd
151
–
200
°C
Tj increasing
Overtemperature shutdown
threshold hysteresis
Tj,hy
–
20
–
K
Tj decreasing 2)
2)
P_5.2.17
1) See typical performance graph for details.
2) Parameter not subject to production test; specified by design.
3) Measured when the output voltage VQ has dropped 100 mV from its nominal value.
Datasheet
13
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Voltage regulator
4.3
Typical performance characteristics voltage regulator
Output voltage VQ vs.
junction temperature Tj
Output capacitor series resistor ESRCQ vs.
output current IQ
VQ -Tj. v s d
100
VQ [V]
ESR 1 0 u-IQ .v s d
ESRCQ
C Q ≥ 10 µF;
6 V ≤ VI ≤ 28 V;
-40 °C ≤ Tj ≤ 150 °C
[Ω]
10
5.02
5.00
1
Stable
Region
4.98
0 .1
4.96
-40 -20
0
20 40
60
0.01
80 100 120 140
T j [°C]
0
40
80
120
160
IQ [mA]
Output current limitation IQ,max vs.
input voltage VI
SO A.v s d
IQ,ma x
[mA]
400
Tj = 25 °C
T j = 125 °C
300
200
100
0
10
20
30
40
VI [V]
Datasheet
14
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Voltage regulator
Dropout voltage Vdr vs.
output current IQ
Dropout voltage Vdr vs.
junction temperature Tj
300
Vd r- IQ.v s d
Vdr [mV]
Vd r- Tj. v s d
Vdr [mV]
IQ = 150 mA
200
200
T j = 125 °C
100
150
100
50
T j = 25 °C
20
IQ = 50 mA
IQ = 200 µA
0.2
1
10
100
0
-40 -20
20
40
60
80 100 120 140
IQ [mA]
Reverse output current IQ vs.
output voltage VQ
Tj [°C]
Reverse current II vs.
input voltage VI
0
0
IQ-VQ @ VI=0 v. s d
IQ [mA]
II [mA]
VI = 0 V
II-VI@VQ =0 .v s d
VQ = 0 V
-1
-0.4
T j = -40 °C
-1.5
-0.6
T j = 150 °C
Tj = -40 °C
-2
-0.8
Tj = 25 °C
-2.5
T j = 150 °C
0
1.6
3.2
4 .8
6
-32
V Q [V]
Datasheet
- 24
-16
-8
0
VI [V]
15
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Current consumption
5
Current consumption
5.1
Electrical characteristics current consumption
Table 5
Electrical characteristics current consumption
VI = 13.5 V, Tj = -40°C to +150°C, all voltages with respect to ground, direction of currents as shown in Figure 6
(unless otherwise specified)
Parameter
Symbol
Current consumption Iq1
watchdog deactivated
Iq = II - IQ
Current consumption
Iq = II - IQ
II
Supply
Iq2
Values
Unit
Note or Test Condition
Number
Min.
Typ.
Max.
–
70
80
µA
IQ ≤ 200 µA; Tj ≤ 25°C
Watchdog deactivated
P_6.1.1
–
77
85
µA
IQ ≤ 200 µA; Tj ≤ 85°C
Watchdog deactivated
P_6.1.2
–
117
130
µA
IQ ≤ 2 mA; Tj ≤ 25°C
Watchdog activated
P_6.1.3
–
127
135
µA
IQ ≤ 2 mA; Tj ≤ 85°C
Watchdog activated
P_6.1.4
–
1
2
mA
IQ = 50 mA
P_6.1.5
–
5.5
8
mA
IQ = 150 mA
P_6.1.6
I
Q
IQ
Voltage Regulator
+
+
VI
CQ
CI
CurrentConsumption _ ParameterDefinition .vsd
Regulated
Output Voltage
VQ
LOAD
GND
Iq
Figure 6
Datasheet
Parameter definition
16
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Current consumption
5.2
Typical performance characteristics current consumption
Current consumption Iq vs.
junction temperature Tj
Current consumption Iq vs.
junction temperature Tj
Iq -Tj .v s d
Iq [mA]
140
VI = 13 .5 V
Iq1 0 0 u _ Tj. v s d
IQ = 100 µA
VI = 13.5 V
Iq [µA]
Watchdog activated
Watchdog deactivated
10
IQ = 150 mA
100
IQ = 50 mA
1
80
60
IQ = 2 mA
0.1
40
0.01
-40 -20
20
0
40
60
80 100 120 140
0
-40
40
80
Tj [°C]
Current consumption Iq vs.
output current IQ
120
150
T j [°C]
Current consumption Iq vs.
input voltage VI
Iq -IQ .v s d
24
Iq [mA]
Iq -VI.v s d
Tj = 25 °C
Iq [mA]
10
16
RL = 50 Ω
1
12
VI = 13.5 V
T j = 125 °C
VI = 13 .5 V
Tj = 25 °C
RL = 500 Ω
8
0.1
4
0.01
0.2
1
10
0
100
IQ [mA]
Datasheet
2
4
6
8
VI [V]
17
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Reset function
6
Reset function
6.1
Description reset function
The reset function provides several features:
Output undervoltage reset
An output undervoltage condition is indicated by setting the reset output “RO” to “low”. This signal might be
used to reset a microcontroller during low supply voltage.
Power-on reset delay time
The power-on reset delay time td,PWR-ON allows a microcontroller and oscillator to start up. This delay time is
the time period from exceeding the upper reset switching threshold VRT,hi until the reset is released by
switching the reset output “RO” from “low” to “high”. The power-on reset delay time td,PWR-ON is defined by an
external delay capacitor CD connected to pin “D” which is charged up by the delay capacitor charge
current ID,ch starting from VD = 0 V.
In case a power-on reset delay time td,PWR-ON different from the value for CD = 100 nF is required, the delay
capacitor’s value can be derived from the specified value given in P_7.2.15:
CD = 100 nF × td,PWR-ON / td,PWR-ON,100nF
(6.1)
with
•
td,PWR-ON: Desired power-on reset delay time.
•
td,PWR-ON,100nF: Power-on reset delay time specified in P_7.2.15.
•
CD: Delay capacitor required.
The formula is valid for CD ≥ 10 nF. For precise timing calculations consider also the delay capacitor’s
tolerance.
Undervoltage reset delay time
Unlike the power-on reset delay time, the undervoltage reset delay time td considers a short output
undervoltage event where the delay capacitor CD is assumed to be discharged to VD = VDST,lo only before the
charging sequence starts. Therefore, the undervoltage reset delay time td is defined by the delay capacitor
charge current ID,ch starting from VD = VDST,lo and the external delay capacitor CD.
A delay capacitor CD for a different undervoltage reset delay time as specified in P_7.2.14 can be calculated
similar as above:
CD = 100 nF × td / td,100nF
(6.2)
with
•
td: Desired undervoltage reset delay time.
•
td,100nF: Power-on reset delay time specified in P_7.2.14.
•
CD: Delay capacitor required
The formula is valid for CD ≥ 10 nF. For precise timing calculations consider also the delay capacitor’s
tolerance.
Datasheet
18
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Reset function
Reset reaction time
In case the output voltage of the regulator drops below the output undervoltage lower reset threshold VRT,lo,
the delay capacitor CD is discharged rapidly. Once the delay capacitor’s voltage has reached the lower delay
switching threshold VDST,lo, the reset output “RO” will be set to “low”.
Additionally to the delay capacitor discharge time trr,d, an internal reaction time trr,int applies. Hence, the total
reset reaction rime trr,total becomes:
trr,total = trr,int + trr,d
(6.3)
with
•
trr,total: Total reset reaction time.
•
trr,int: Internal reset reaction time; see P_7.2.16.
•
trr,d: Delay capacitor discharge time. For a capacitor CD different from the value specified in P_7.2.17, see
typical performance graphs.
Reset output “RO”
The reset output “RO” is an open collector output with an integrated pull-up resistor. In case a lower-ohmic
“RO” signal is desired, an external pull-up resistor to the output “Q” can be connected. Since the maximum
“RO” sink current is limited, the optional external resistor RRO,ext must not be lower than specified in P_7.2.8.
Reset output “RO” Low for VQ ≥ 1 V
In case of an undervoltage reset condition reset output “RO” is held “low” for VQ ≥ 1 V, even if the input
voltage VI is 0 V. This is achieved by supplying the reset circuit from the output capacitor.
Reset adjust function
The undervoltage reset switching threshold can be adjusted according to the application’s needs by
connecting an external voltage divider (RADJ1, RADJ2) at pin “RADJ”. For selecting the default threshold connect
pin “RADJ” to GND. The reset adjustment range is given in P_7.2.6.
When dimensioning the voltage divider, take into consideration that there will be an additional current
constantly flowing through the resistors.
With a voltage divider connected, the reset switching threshold VRT,adj is calculated as follows:
VRT,adj = VRADJ,th × (RADJ,1 + RADJ,2) / RADJ,2
(6.4)
with
•
VRT,adj: Desired reset switching threshold.
•
RADJ,1, RADJ,2: Resistors of the external voltage divider, see Figure 7.
•
VRADJ,th: Reset adjust switching threshold given in P_7.2.5.
Datasheet
19
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Reset function
I
Q
R RO
Int.
Supply
Control
VDD
CQ
RO
ID ,ch
Reset
IRO
VDST
V RADJ ,th
optional
Supply
OR
MicroController
RADJ ,1
RADJ
IRADJ
GND
opti onal
IDR ,dsch
D
BlockDiagram _ResetAdjust .vsd
GND
RADJ ,2
CD
Figure 7
Block diagram reset circuit
VI
t
VQ
t < trr,blank
V RH
V RT,hi
V RT,lo
1V
t
td
VD
VDS T,hi
VDS T,lo
t
VRO
V RO,low
td
trr,total
Datasheet
t rr,total
td
t rr,total
1V
t
Thermal
Shutdown
Figure 8
td
Input
Voltage Dip
Undervoltage
Spike at
output
Overload
T i mi n g Di a g ra m_ Re se t. vs
Timing diagram reset
20
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Reset function
6.2
Electrical characteristics reset function
Table 6
Electrical characteristics reset function
VI = 13.5 V, Tj = -40°C to +150°C, all voltages with respect to ground, direction of currents as shown in Figure 7
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Unit
Note or Test Condition Number
Max.
Output undervoltage reset comparator default values (pin RADJ = GND)
Output undervoltage reset
lower switching threshold
VRT,lo
4.6
4.7
4.8
V
VI = 0 V
VQ decreasing
RADJ = GND
P_7.2.1
Output undervoltage reset
upper switching threshold
VRT,hi
4.7
4.8
4.9
V
VI within operating
range
VQ increasing
RADJ = GND
P_7.2.2
Output undervoltage reset
switching hysteresis
VRT,hy
60
120
–
mV
VI within operating
range
RADJ = GND.
P_7.2.3
Output undervoltage reset
headroom
VRH
250
300
–
mV
Calculated Value:
VQ - VRT,lo
VI within operating
range
IQ = 50 mA
RADJ = GND
P_7.2.4
Reset adjust
lower switching threshold
VRADJ,th
1.176
1.20
1.224
V
VI = 0 V
3.2 V ≤ VQ < 5 V
P_7.2.5
Lower reset threshold
adjustment range 1)
VRT,adj
3.20
–
VRT,lo
V
–
P_7.2.6
Reset output low voltage
VRO,low
–
0.2
0.4
V
VI = 0 V;
RRO,ext = 3.3 kΩ;
1 V ≤ VQ ≤ VRT,low
P_7.2.7
Reset output
external pull-up resistor to Q
RRO,ext
3
–
–
kΩ
VI = 0 V;
VRO = 0.4 V
1 V ≤ VQ ≤ VRT,low
P_7.2.8
Reset output
internal pull-up resistor
RRO
20
30
40
kΩ
Internally connected
to Q
P_7.2.9
Upper delay
switching threshold
VDST,hi
–
1.21
–
V
–
P_7.2.10
Lower delay
switching threshold
VDST,lo
–
0.30
–
V
–
P_7.2.11
Delay capacitor
charge current
ID,ch
–
2.8
–
µA
VD = 1 V
P_7.2.12
Reset threshold adjustment
Reset output RO
Reset delay timing
Datasheet
21
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Reset function
Table 6
Electrical characteristics reset function (cont’d)
VI = 13.5 V, Tj = -40°C to +150°C, all voltages with respect to ground, direction of currents as shown in Figure 7
(unless otherwise specified)
Parameter
Symbol
Values
Unit
Note or Test Condition Number
Min.
Typ.
Max.
–
80
–
mA
VD = 1 V
Undervoltage reset delay time td,100nF
23
31
41
ms
Calculated value;
P_7.2.14
2)
CD = 100 nF ;
CD discharged to VDST,lo
td,PWR-
30
43
56
ms
Calculated value;
CD = 100 nF 2);
CD discharged to 0 V;
P_7.2.15
–
9
15
µs
CD = 0 nF
P_7.2.16
Delay capacitor
reset discharge current
Power-on reset delay time
IDR,dsch
ON,100nF
Internal reset reaction time
trr,int
Delay capacitor
discharge time
trr,d,100nF
Total reset reaction time
trr,total,100 –
–
P_7.2.13
1.5
3
µs
CD = 100 nF
10.5
18
µs
Calculated Value:
trr,d,100nF + trr,int;
CD = 100 nF 2)
nF
2)
P_7.2.17
P_7.2.18
1) Related parameters (VRT,hi, VRT,hy) are scaled linear when the reset switching threshold is modified.
2) For programming a different delay and reset reaction time, see Chapter 6.1.
Datasheet
22
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Reset function
6.3
Typical performance characteristics reset function
Undervoltage reset switching thresholds VRT,lo,
VRT,hi vs. junction temperature Tj
Reset delay time td, td,PWR-ON vs.
delay capacitor CD
td -CD .v s d
VRT-Tj .v s d
td ,
VQ [V],
VRT [V]
5.0
[ms]
VQ
100
4,7
td (typ.)
VRT,hi
10
VRT,lo
-40 -20
0
20
40
60
1
10
80 100 120 140
100
1000
CD [nF]
Tj [°C]
Datasheet
td,PWR-ON (typ.)
Output Undervoltage
Reset Headroom VRH
4,9
4,8
td ,PWR- ON
Pin RADJ = GND
23
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Watchdog function
7
Watchdog function
7.1
Description
The TLE4678 features a load dependent watchdog function with a programmable activating threshold as well
as programmable watchdog timing.
The watchdog function monitors a microcontroller, including time base failures. In case of a missing rising
edge within a certain pulse repetition time, the watchdog output is set to ‘low’. The programming of the
expected watchdog pulse repetition time can be easily done by an external reset delay capacitor.
The watchdog output “WO” is separated from the reset output “RO”. Hence, the watchdog output might be
used as an interrupt signal for the microcontroller independent from the reset signal. It is possible to
interconnect pin “WO” and pin “RO” in order to establish a wire-or function with a dominant low signal.
Programmable watchdog activation threshold and hysteresis
In case a microcontroller is set to sleep mode or to low power mode, its current consumption is very low and
the controller might not be able to send any watchdog pulses to the regulators watchdog input “WI”. In order
to avoid unwanted wake-up signals due to missing edges at pin “WI”, the TLE4678 watchdog function can be
activated dependent on the regulator’s output current. The TLE4678 comprises a default watchdog activating
threshold IQ,WDact,th with a small hysteresis IQ,WDact,hy. The thresholds can be increased by connecting an
external resistor RWADJ,ext to pin “WADJ”. For using the default watchdog activating threshold, leave pin
“WADJ” open.
The following equation calculates the external resistor RWADJ,ext that is needed at pin “WADJ” for activating the
watchdog at a desired output current IQ,WDact,th:
(7.1)
RWADJ,ext =
FWDact,th × RWADJ,int
(RWADJ,int × IQ,WDact,th) - FWDact,th
for IQ,WDact,th larger than the default value given in P_8.2.1.
At decreasing output current, the deactivation threshold then would be:
(7.2)
IQ,WDdeact,th = FWDdeact,th ×
RWADJ,int + RWADJ,ext
RWADJ,int × RWADJ,ext
The watchdog activating threshold hysteresis IQ,WDact,hy calculates:
(7.3)
IQ,WDact,hy = FWDact,hy ×
RWADJ,int + RWADJ,ext
RWADJ,int × RWADJ,ext
with:
•
IQ,WDact,th : Desired “watchdog activating threshold”.
•
RWADJ,int : Internal watchdog adjust resistor.
Datasheet
24
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Watchdog function
•
RWADJ,ext : External watchdog adjust resistor.
•
FWDact,th : Activating threshold factor.
•
FWDdeact,th : Deactivating threshold factor.
•
FWDact,hy : Activating threshold factor hysteresis.
Supply
I
IQ
Q
IWADJ
Control
VDD
CQ
RWO
VWADJ,th
RWADJ ,ext
optional
WADJ
MicroController
RWADJ ,int
(optional)
Int.
Supply
WI
Edge
Detect
OR
S
R
WO
I D,ch
Reset
IWO
VDW
&
1
IDW ,dsch
WI
I/O
VDW,hi
GND
D
GND
BlockDiagram _WatchdogAdjust .vsd
CD
Figure 9
Block diagram watchdog circuit
Watchdog output “WO”
The watchdog output “WO” is an open collector output with an integrated pull-up resistor. In case a lowerohmic “WO” signal is desired, an external pull-up resistor to the output “Q” can be connected. Since the
maximum “WO” sink current is limited, the optional external resistor RWO,ext needs to be sized to comply with
the watchdog output sink current (see P_8.2.15 and P_8.2.16).
Watchdog input “WI”
The watchdog is triggered by a positive edge at the watchdog input “WI”. The signal is filtered by a band-pass
filter and therefore its amplitude and slope have to comply with the specification P_8.2.10 to P_8.2.14. For
details on the test pulse applied, see Figure 10.
V WI
V WI
tWI,p
VWI,hi
VWI,lo
VWI,hi
VWI,lo
d VWI / d t
t
Figure 10
Datasheet
1 / fWI
t
Test pulses watchdog input WI
25
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Watchdog function
Watchdog timing
Positive edges at the watchdog input pin “WI” are expected within the watchdog trigger time frame tWI,tr,
otherwise a low signal at pin “WO” is generated. If a watchdog low signal at pin “WO” is generated, it remains
low for tWD,lo. All watchdog timings are defined by charging and discharging the capacitor CD at pin “D”. Thus,
the watchdog timing can be programmed by selecting CD. For timing details see also Figure 11.
In case a watchdog trigger time period tWI,tr different from the value for CD = 100 nF is required, the delay
capacitor’s value can be derived from the specified value given in P_8.2.22:
CD = 100nF × tWI,tr / tWI,tr,100nF
(7.4)
The watchdog output low time tWD,lo and the watchdog period tWD,p then becomes:
tWD,lo = tWD,lo,100nF × CD / 100 nF
(7.5)
tWD,p = tWI,tr + tWD,lo
(7.6)
The formula is valid for CD ≥ 10nF. For precise timing calculations consider also the delay capacitor’s
tolerance.
VWI
V WI,hi
V WI,lo
dV WI / d t
outside spec
No positive
VWI edge
VD
tWI,tr
1/ fWI
t WI,p
t
TWI,p
VDW,hi
VDW,lo
t
t WD,lo
t WD,lo
VWO
V WO,low
Figure 11
Datasheet
T i mi n g Di a g ra m_ W a t ch d o g .vsd
t
Timing diagram watchdog
26
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Watchdog function
7.2
Electrical characteristics watchdog function
Table 7
Electrical characteristics watchdog function
VI = 13.5 V, Tj = -40°C to +150°C, all voltages with respect to ground, direction of currents as shown in Figure 9
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Unit
Note or
Test Condition
Number
Max.
Default watchdog activating threshold (pin WADJ left open)
Watchdog activating
threshold
IQ,WDact,th
0.65
1.1
1.5
mA
IQ increasing
P_8.2.1
Watchdog deactivating
threshold
IQ,WDdeact,t 0.55
0.9
–
mA
IQ decreasing
P_8.2.2
Watchdog activating
threshold hysteresis
IQ,WDact,hy
200
–
µA
–
P_8.2.3
h
50
Adjustable watchdog activating threshold (external resistor connected to pin WADJ)
Activating threshold
VWADJ,th
–
693
–
mV
–
P_8.2.4
Current ratio
IQ / IWADJ
–
208
–
–
VWADJ = 0V
P_8.2.5
Internal watchdog adjust
resistor
RWADJ,int
96
131
175
kΩ
–
P_8.2.6
Activating threshold factor
FWDact,th
127
144
162
mA
× kΩ
Calculated value 1)
P_8.2.7
Deactivating threshold factor
FWDdeact,th 104
118
–
mA
× kΩ
Calculated value 1)
P_8.2.8
Activating threshold
switching hysteresis factor
FWDact,hy
7
26
–
mA
× kΩ
Calculated value 1)
P_8.2.9
Watchdog input
low signal valid
VWI,lo
–
–
0.8
V
– 2)
P_8.2.10
Watchdog input
high signal valid
VWI,hi
2.6
–
–
V
– 2)
P_8.2.11
Watchdog input
high signal pulse length
tWI,p
0.5
–
–
µs
VWI ≥ VWI,high 2)
P_8.2.12
Watchdog input signal
slew rate
∆VWI/∆t
1
–
–
V/µs
VWI,low ≤ VWI ≤ VWI,high 2)
P_8.2.13
Watchdog input signal
frequency capture range
fWI
–
–
1
MHz
Square wave,
50% duty cycle 2)
P_8.2.14
Watchdog input WI
Datasheet
27
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Watchdog function
Table 7
Electrical characteristics watchdog function (cont’d)
VI = 13.5 V, Tj = -40°C to +150°C, all voltages with respect to ground, direction of currents as shown in Figure 9
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Number
Watchdog output WO
Watchdog output
low voltage
VWO,low
–
0.2
0.4
V
IWO = 1 mA;
Watchdog active;
VWI = 0 V
P_8.2.15
Watchdog output
maximum sink current
IWO,max
1.5
13
30
mA
VWO = 0.8 V;
Watchdog active;
VWI = 0 V
P_8.2.16
Watchdog output
internal pull-up resistor
RWO
20
30
40
kΩ
–
P_8.2.17
Delay capacitor
charge current
ID
–
2.78
–
µA
VD = 1 V
P_8.2.18
Delay capacitor
watchdog discharge current
IDW,disch
–
1.39
–
µA
VD = 1 V
P_8.2.19
Upper watchdog timing
threshold
VDW,hi
–
1.2
–
V
–
P_8.2.20
Lower watchdog timing
threshold
VDW,lo
–
0.7
–
V
–
P_8.2.21
Watchdog trigger time
tWI,tr,100nF
25
36
47
ms
Calculated value;
CD = 100 nF 3)
P_8.2.22
Watchdog output low time
tWD,lo,100nF 13
18
23
ms
Calculated value;
CD = 100 nF 3)
VQ > VRT,lo
P_8.2.23
Watchdog period
tWD,p,100nF 38
54
70
ms
Calculated value;
tWI,tr,100nF + tWD,lo,100nF
CD = 100 nF 3)
P_8.2.24
Watchdog timing
1) See Chapter 7.1 for calculation hint.
2) For details on the test pulse applied, see Figure 10.
3) For programming a different watchdog timing, see Chapter 7.1.
Datasheet
28
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Watchdog function
7.3
Typical performance characteristics standard watchdog function
Watchdog activating threshold VWADJact,th vs.
external resistor RWADJ,ext
24
Watchdog deactivating threshold VWADJdeact,th vs.
external resistor RWADJ,ext
24
VWADJ a c t-RWADJ e x t.v s d
VWADJ d e a c t-RWADJ e x t.v s d
IQ,WDact,th
IQ,WDact,th
[mA]
[mA]
16
16
typ.
14
14
min.
12
12
10
10
max.
8
8
6
6
4
4
2
2
4
10
100
1000
4000
typ.
4
RWAD J ,e xt [kΩ]
10
100
1000
4000
RWAD J ,e xt [kΩ]
Watchdog trigger time tWI,tr vs.
delay capacitor CD
tWItr-CD v. s d
tWI,tr
[ms]
100
max.
typ.
10
min .
1
10
100
1000
C D [nF]
Datasheet
29
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Application information
8
Application information
Note:
The following information is given as a hint for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition or quality of the device.
8.1
Application diagram
Supply
TLE 4678
I
Q
Regulated Output Voltage
Load
e. g.
Micro
Controller
XC22xx
CQ 10µF
ESR < 3Ohm
RO
DI
CI2
CI1
< 45V
10µF
100nF
Protection
Circuits
Bandgap
Reference
Reset
and
Watchdog
Generator
WO
WI
RADJ
GND
WADJ
GND
D
CD
Figure 12
100nF
Application diagram with selecting default reset and watchdog activation thresholds
Supply
TLE 4678
I
Q
Regulated Output Voltage
CQ
RO
DI
CI2
CI1
< 45V
10µF
100nF
Protection
Circuits
Bandgap
Reference
Reset
and
Watchdog
Generator
10µF
ESR < 3Ohm
47k
WO
Load
e. g.
Micro
Controller
XC22xx
WI
RADJ
GND
WADJ
GND
D
CD
Figure 13
Datasheet
33k
22k
100nF
Application diagram with reset and watchdog activation threshold adjustment
30
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Application information
8.2
Selection of external components
8.2.1
Input pin
The typical input circuitry for a linear voltage regulator is shown in the application diagram above.
A ceramic capacitor at the input, in the range of 100 nF to 470 nF, is recommended to filter out the high
frequency disturbances imposed by the line e.g. ISO pulses 3a/b. This capacitor must be placed very close to
the input pin of the linear voltage regulator on the PCB.
An aluminum electrolytic capacitor in the range of 10 µF to 470 µF is recommended as an input buffer to
smooth out high energy pulses, such as ISO pulse 2a. This capacitor should be placed close to the input pin of
the linear voltage regulator on the PCB.
An overvoltage suppressor diode can be used to further suppress any high voltage beyond the maximum
rating of the linear voltage regulator and protect the device against any damage due to over-voltage.
The external components at the input are not mandatory for the operation of the voltage regulator, but they
are recommended in case of possible external disturbances.
8.2.2
Output pin
An output capacitor is mandatory for the stability of linear voltage regulators.
The requirement to the output capacitor is given in Chapter 3.2. The graph Output capacitor series resistor
ESRCQ vs. output current IQ shows the stable operation range of the device.
TLE4678 is designed to be stable with extremely low ESR capacitors. According to the automotive
environment, ceramic capacitors with X5R or X7R dielectrics are recommended.
The output capacitor should be placed as close as possible to the regulator’s output and GND pins and on the
same side of the PCB as the regulator itself.
In case of rapid transients of input voltage or load current, the capacitance should be dimensioned in
accordance and verified in the real application that the output stability requirements are fulfilled.
Datasheet
31
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Application information
8.3
Thermal considerations
Knowing the input voltage, the output voltage and the load profile of the application, the total power
dissipation can be calculated:
(8.1)
PD = ( VI – VQ ) × IQ + VI × Iq
with
•
PD: continuous power dissipation
•
VI: input voltage
•
VQ: output voltage
•
IQ: output current
•
Iq: quiescent current
The maximum acceptable thermal resistance RthJA can then be calculated:
(8.2)
R thJA, max
T j, max – T a
= --------------------------PD
with
•
Tj,max: maximum allowed junction temperature
•
Ta: ambient temperature
Based on the above calculation the proper PCB type and the necessary heat sink area can be determined with
reference to the specification in Chapter 3.3.
Example
Application conditions:
VI = 13.5 V
VQ = 5 V
IQ = 150 mA
Ta = 75°C
Calculation of RthJA,max:
PD = (VI – VQ) × IQ + VI × Iq
= (13.5 V – 5 V) × 150 mA + 13.5 V × 8 mA
= 1.275 W + 0.108 W
= 1.383 W
RthJA,max = (Tj,max – Ta) / PD
= (150°C – 75°C) / 1.383 W
= 54.2 K/W
Datasheet
32
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Application information
As a result, the PCB design must ensure a thermal resistance RthJA lower than 54.2 K/W. By considering
TLE4678EL (PG-SSOP-14 EP package) and according to Chapter 3.3, at least 600 mm2 heatsink area is needed
on the FR4 1s0p PCB, or the FR4 2s2p board can be used.
8.4
Reverse polarity protection
TLE4678 is self protected against reverse polarity faults and allows negative supply voltage. External reverse
polarity diode is not needed. However, the absolute maximum ratings of the device as specified in
Chapter 3.1 must be kept.
The reverse voltage causes several small currents to flow into the IC hence increasing its junction
temperature. As the thermal shut down circuitry does not work in the reverse polarity condition, designers
have to consider this in their thermal design.
Datasheet
33
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Package information
9
Package information
1.75 MAX.
C
1)
4 -0.2
B
1.27
0.64 ±0.25
0.1
2)
0.41+0.10
-0.06
6±0.2
0.2 M A B 14x
14
0.2 M C
8
1
7
1)
8.75 -0.2
8˚MAX.
0.19 +0.06
0.175 ±0.07
(1.47)
0.35 x 45˚
A
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Lead width can be 0.61 max. in dambar area
GPS01230
Figure 14
PG-DSO-141)
1) Dimensions in mm
Datasheet
34
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
0.35 x 45°
6 x 0.65 = 3.9
0.19 +0.06
H
0.08 C
SEATING
PLANE
0.64 ±0.25
D
0.15 M C A-B D 14x
Bottom View
3 ±0.2
A
14
1
8
1
7
Exposed
Diepad
B
Index
Marking 4.9 ±0.11)
0.1 H A-B 2x
14
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Lead width can be 0.61 max. in dambar area
Figure 15
0.2 C 14x
6 ±0.2
2)
7
8
2.65 ±0.2
0.25 ±0.05
0.1 H D 2x
8° MAX.
C
0.65
3.9 ±0.11)
1.7 MAX.
0.05 ±0.05
STAND OFF
(1.45)
Package information
PG-SSOP-14
PG-SSOP-141)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-compliant
(i.e. Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Further information on packages
https://www.infineon.com/packages
1) Dimensions in mm
Datasheet
35
Rev. 1.21
2019-09-30
OPTIREG™ Linear TLE4678
Low drop out linear voltage regulator
Revision history
10
Revision history
Revision Date
Changes
1.21
2019-09-30 Updated layout and structure
Editorial changes.
1.2
2014-10-17 Typical values for Iq1 and Iq2 updated in Electrical characteristics current
consumption.
Chapter added: Application information.
Package Outline PG-SSOP-14 updated: Package information
1.1
2009-08-27 Final datasheet version for both package variants.
Modified the Programmable watchdog activation threshold and hysteresis
description for better understanding.
Reset function: Renamed VRT,new to VRT,adj for better understanding.
1.01
2008-08-19 Added target definition for PG-SSOP-14 package. Modifications: Overview page,
thermal resistance table, pin definition, package outlines.
1.0
2008-07-31 Final datasheet initial version.
Datasheet
36
Rev. 1.21
2019-09-30
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2019-09-30
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2019 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email: erratum@infineon.com
Document reference
Z8F52950151
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