74F191_07

74F191 Up/Down Binary Counter with Preset and Ripple Clock April 2007 74F191 Up/Down Binary Counter with Preset and Ripple Clock Features ■ High-Speed—125MHz typical count frequency ■ Synchronous counting ■ Asynchronous parallel load ■ Cascadable tm General Description The 74F191 is a reversible modulo-16 binary counter featuring synchronous counting and asynchronous presetting. The preset feature allows the 74F191 to be used in programmable dividers. The Count Enable input, the Terminal Count output and Ripple Clock output make possible a variety of methods of implementing multistage counters. In the counting modes, state changes are initiated by the rising edge of the clock. Ordering Information Order Number 74F191SC 74F191SJ 74F191PC Package Number M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Logic Symbols Connection Diagram IEEE/IEC ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0.2 www.fairchildsemi.com 74F191 Up/Down Binary Counter with Preset and Ripple Clock Unit Loading/Fan Out Pin Names CE CP P0–P3 PL U/D Q0–Q3 RC TC Description Count Enable Input (Active LOW) Clock Pulse Input (Active Rising Edge) Parallel Data Inputs Asynchronous Parallel Load Input (Active LOW) Up/Down Count Control Input Flip-Flop Outputs Ripple Clock Output (Active LOW) Terminal Count Output (Active HIGH) U.L. HIGH / LOW 1.0 / 3.0 1.0 / 1.0 1.0 / 1.0 1.0 / 1.0 1.0 / 1.0 50 / 33.3 50 / 33.3 50 / 33.3 Input IIH / IIL Output IOH / IOL 20µA / -1.8mA 20µA / -0.6 mA 20µA / -0.6 mA 20µA / -0.6mA 20µA / -0.6mA -1mA / 20mA -1mA / 20mA -1mA / 20mA Functional Description The 74F191 is a synchronous up/down 4-bit binary counter. It contains four edge-triggered flip-flops, with internal gating and steering logic to provide individual preset, count-up and count-down operations. Each circuit has an asynchronous parallel load capability permitting the counter to be preset to any desired number. When the Parallel Load (PL) input is LOW, information present on the Parallel Data inputs (P0–P3) is loaded into the counter and appears on the Q outputs. This operation overrides the counting functions, as indicated in the Mode Select Table. A HIGH signal on the CE input inhibits counting. When CE is LOW, internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The direction of counting is determined by the U/D input signal, as indicated in the Mode Select Table. CE and U/D can be changed with the clock in either state, provided only that the recommended setup and hold times are observed. Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches 15 in the count-up mode. The TC output will then remain HIGH until a state change occurs, whether by counting or presetting or until U/D is changed. The TC output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is also used internally to enable the Ripple Clock (RC) output. The RC output is normally HIGH. When CE is LOW and TC is HIGH, the RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multistage counters, as indicated in Figure 1 and Figure 2. In Figure 1, each RC output is used as the clock input for the next higher stage. This configuration is particularly advantageous when the clock source has a limited drive capability, since it drives only the first stage. To prevent counting in all stages it is only necessary to inhibit the first stage, since a HIGH signal on CE inhibits the RC output pulse, as indicated in the RC Truth Table. A disadvantage of this configuration, in some applications, is the timing skew between state changes in the first and last stages. This represents the cumulative delay of the clock as it ripples through the preceding stages. A method of causing state changes to occur simultaneously in all stages is shown in Figure 2. All clock inputs are driven in parallel and the RC outputs propagate the carry/borrow signals in ripple fashion. In this configuration the LOW state duration of the clock must be long enough to allow the negative-going edge of the carry/borrow signal to ripple through to the last stage before the clock goes HIGH. There is no such restriction on the HIGH state duration of the clock, since the RC output of any device goes HIGH shortly after its CP input goes HIGH. The configuration shown in Figure 3 avoids ripple delays and their associated restrictions. The CE input for a given stage is formed by combining the TC signals from all the preceding stages. Note that in order to inhibit counting an enable signal must be included in each carry gate. The simple inhibit scheme of Figure 1 and Figure 2 doesn’t apply, because the TC output of a given stage is not affected by its own CE. ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0.2 www.fairchildsemi.com 2 74F191 Up/Down Binary Counter with Preset and Ripple Clock Mode Select Table Inputs PL H H L H RC Truth Table Inputs Output CP X X CE L L X H U/D L H X X CP Mode Count Up Count Down CE L H X TC(1) H X L RC H H X X Preset (Asyn.) No Change (Hold) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition = LOW Pulse Note: 1. TC is generated internally. Figure 1. n-Stage Counter Using Ripple Clock Figure 2. Synchronous n-Stage Counter Using Ripple Carry/Borrow Figure 3. Synchronous n-Stage Counter with Gated Carry/Borrow ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0.2 www.fairchildsemi.com 3 74F191 Up/Down Binary Counter with Preset and Ripple Clock Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 4. ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0.2 www.fairchildsemi.com 4 74F191 Up/Down Binary Counter with Preset and Ripple Clock Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol TSTG TA TJ VCC VIN IIN VO Storage Temperature Parameter Ambient Temperature Under Bias Junction Temperature Under Bias VCC Pin Potential to Ground Pin Input Voltage(2) Input Current(2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max.) Rating –65°C to +150°C –55°C to +125°C –55°C to +150°C –0.5V to +7.0V –0.5V to +7.0V –30mA to +5.0mA –0.5V to VCC –0.5V to +5.5V twice the rated IOL (mA) Note: 2. Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol TA VCC Free Air Ambient Temperature Supply Voltage Parameter Rating 0°C to +70°C +4.5V to +5.5V ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0.2 www.fairchildsemi.com 5 74F191 Up/Down Binary Counter with Preset and Ripple Clock DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD IIL IOS ICC Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage 10% VCC 5% VCC 10% VCC VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal Min. 2.0 Typ. Max. Units V 0.8 –1.2 V V V 0.5 5.0 7.0 50 V µA µA µA V 3.75 –0.6 –1.8 µA mA mA mA Min. Min. Min. Max. Max. Max. 0.0 0.0 Max. Max. Max. IIN = –18mA IOH = –1mA IOL = 20mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9µA, All Other Pins Grounded VIOD = 150mV, All Other Pins Grounded VIN = 0.5V (except CE) VIN = 0.5V (CE) VOUT = 0.0V –60 38 4.75 2.5 2.7 Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Voltage –150 55 ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0.2 www.fairchildsemi.com 6 74F191 Up/Down Binary Counter with Preset and Ripple Clock AC Electrical Characteristics TA = +25°C, VCC = +5.0V, CL = 50pF Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL TA = –55°C to +125°C, VCC = +5.0V, CL = 50pF Min. 3.0 5.0 6.0 5.0 3.0 3.0 3.0 3.0 7.0 5.5 4.0 4.0 3.0 6.0 5.0 5.5 TA = 0°C to 70°C, VCC = +5.0V, CL = 50pF Min. 3.0 5.0 6.0 5.0 3.0 3.0 3.0 3.0 7.0 5.5 4.0 4.0 3.0 6.0 5.0 5.5 5.0 6.0 6.5 6.0 8.0 6.0 10.0 9.0 Parameter Maximum Count Frequency Propagation Delay, CP to Qn Propagation Delay, CP to TC Propagation Delay, CP to RC Propagation Delay, CE to RC Propagation Delay, U/D to RC Propagation Delay, U/D to TC Propagation Delay, Pn to Qn Propagation Delay, PL to Qn Propagation Delay, Pn to TC Propagation Delay, Pn to RC Propagation Delay, PL to TC Propagation Delay, PL to RC Min. 3.0 5.0 6.0 5.0 3.0 3.0 3.0 3.0 7.0 5.5 4.0 4.0 3.0 6.0 5.0 5.5 5.0 6.5 6.5 6.0 8.0 6.0 10.0 9.0 Typ. 100 5.5 8.5 10.0 8.5 5.5 5.0 5.0 5.5 11.0 9.0 7.0 6.5 4.5 10.0 8.5 9.0 Max. 7.5 11.0 13.0 11.0 7.5 7.0 7.0 7.0 18.0 12.0 10.0 10.0 7.0 13.0 11.0 12.0 14.0 13.0 19.0 14.0 16.5 13.5 20.0 15.5 Max. 9.5 13.5 16.5 13.5 9.5 9.0 9.0 9.0 22.0 14.0 13.5 12.5 9.0 16.0 13.0 14.5 Max. 8.5 12.0 14.0 12.0 8.5 8.0 8.0 8.0 20.0 13.0 11.0 11.0 8.0 14.0 12.0 13.0 15.0 14.0 20.0 15.0 17.5 14.5 21.0 16.0 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0.2 www.fairchildsemi.com 7 74F191 Up/Down Binary Counter with Preset and Ripple Clock AC Operating Requirements TA = +25°C, VCC = +5.0V Symbol tS(H) tS(L) tH(H) tH(L) tS(L) tH(L) tS(H) tS(L) tH(H) tH(L) tW(L) tW(L) tREC TA = –55°C to +125°C, TA = 0°C to 70°C, VCC = +5.0V VCC = +5.0V Min. 6.0 6.0 2.0 2.0 10.5 0 12.0 12.0 0 0 8.5 7.0 7.5 Parameter Setup Time, HIGH or LOW, Pn to PL Hold Time, HIGH or LOW, Pn to PL Setup Time LOW, CE to CP Hold Time LOW, CE to CP Setup Time, HIGH or LOW, U/D to CP Hold Time, HIGH or LOW, U/D to CP PL Pulse Width LOW CP Pulse Width LOW Recovery Time, PL to CP Min. 4.5 4.5 2.0 2.0 10.0 0 12.0 12.0 0 0 6.0 5.0 6.0 Max. Max. Min. 5.0 5.0 2.0 2.0 10.0 0 12.0 12.0 0 0 6.0 5.0 6.0 Max. Units ns ns ns ns ns ns ns ns ns ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0.2 www.fairchildsemi.com 8 74F191 Up/Down Binary Counter with Preset and Ripple Clock Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 5. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0.2 www.fairchildsemi.com 9 74F191 Up/Down Binary Counter with Preset and Ripple Clock Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 6. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0.2 www.fairchildsemi.com 10 74F191 Up/Down Binary Counter with Preset and Ripple Clock Physical Dimensions (Continued) Dimensions are in inches (millimeters) unless otherwise noted. Figure 7. 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0.2 www.fairchildsemi.com 11 74F191 Up/Down Binary Counter with Preset and Ripple Clock TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Across the board. Around the world. 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FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I24 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. No Identification Needed Full Production Obsolete Not In Production ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0.2 www.fairchildsemi.com 12