74LVX74

74LVX74 LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR (5V TOLERANT INPUTS) s s s s s s s s s s s HIGH SPEED: fMAX = 145MHz (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL: VIL=0.8V, VIH=2V AT VCC=3V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 IMPROVED LATCH-UP IMMUNITY POWER DOWN PROTECTION ON INPUTS SOP TSSOP Table 1: Order Codes PACKAGE SOP TSSOP T&R 74LVX74MTR 74LVX74TTR DESCRIPTION The 74LVX74 is a low voltage CMOS DUAL D-TYPE FLIP-FLOP WITH PRESET AND CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications. Figure 1: Pin Connection And IEC Logic Symbols A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of the clock pulse. CLR and PR are independent of the clock and accomplished by a low setting on the appropriate input. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V system. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. August 2004 Rev. 3 1/13 74LVX74 Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N° 1, 13 2, 12 3, 11 SYMBOL 1CLR, 2CLR 1D, 2D 1CK, 2CK NAME AND FUNCTION Asynchronous Reset Direct Input Data Inputs Clock Input (LOW to HIGH, Edge Triggered) Asynchronous Set - Direct Input True Flip-Flop Outputs Complement Flip-Flop Outputs Ground (0V) Positive Supply Voltage 4, 10 5, 9 6, 8 7 14 1PR, 2PR 1Q, 2Q 1Q, 2Q GND VCC Table 3: Truth Table INPUTS CLR L H L H H H X : Don’t Care OUTPUTS FUNCTION D X X X L H X CK X X X Q L H H L H Qn Q H L H H L Qn NO CHANGE CLEAR PRESET PR H L L H H H Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays 2/13 74LVX74 Table 4: Absolute Maximum Ratings Symbol VCC VI VO IIK IOK IO Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 ± 20 ± 25 ± 50 -65 to +150 300 Unit V V V mA mA mA mA °C °C ICC or IGND DC VCC or Ground Current Storage Temperature Tstg TL Lead Temperature (10 sec) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 5: Recommended Operating Conditions Symbol VCC VI VO Top dt/dv Supply Voltage (note 1) Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time (note 2) (VCC = 3.3V) Parameter Value 2 to 3.6 0 to 5.5 0 to VCC -55 to 125 0 to 100 Unit V V V °C ns/V 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2.0V Table 6: DC Specifications Test Condition Symbol Parameter VCC (V) 2.0 3.0 3.6 2.0 3.0 3.6 2.0 3.0 3.0 VOL Low Level Output Voltage 2.0 3.0 3.0 II ICC Input Leakage Current Quiescent Supply Current 3.6 3.6 IO=-50 µA IO=-50 µA IO=-4 mA IO=50 µA IO=50 µA IO=4 mA VI = 5V or GND VI = VCC or GND TA = 25°C Min. 1.5 2.0 2.4 0.5 0.8 0.8 1.9 2.9 2.58 0.0 0.0 0.1 0.1 0.36 ± 0.1 2 2.0 3.0 1.9 2.9 2.48 0.1 0.1 0.44 ±1 20 Typ. Max. Value -40 to 85°C Min. 1.5 2.0 2.4 0.5 0.8 0.8 1.9 2.9 2.4 0.1 0.1 0.55 ±1 20 µA µA V V Max. -55 to 125°C Min. 1.5 2.0 2.4 0.5 0.8 0.8 Max. V Unit VIH High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIL V VOH 3/13 74LVX74 Table 7: Dynamic Switching Characteristics Test Condition Symbol Parameter VCC (V) 3.3 3.3 3.3 CL = 50 pF TA = 25°C Min. Typ. 0.3 -0.5 2 0.8 -0.3 V Max. 0.5 Value -40 to 85°C Min. Max. -55 to 125°C Min. Max. Unit VOLP VOLV VIHD VILD Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f=1MHz. Table 8: AC Electrical Characteristics (Input tr = tf = 3ns) Test Condition Symbol Parameter VCC (V) 2.7 2.7 3.3(*) tPLH tPHL Propagation Delay Time PR or CLR to Q or Q 3.3(*) 2.7 2.7 3.3(*) tw tw(L) ts th tREM fMAX Minimum Pulse Width HIGH or LOW, CK Minimum Pulse Width LOW PR or CLR Minimum Setup Time D to CK HIGH or LOW Minimum Hold Time D to CK HIGH or LOW Minimum Removal Time PR or CLR to CK Maximum Clock Frequency 3.3(*) 2.7 3.3(*) 2.7 3.3 2.7 3.3 2.7 (*) Value TA = 25°C Min. Typ. 7.3 9.8 5.7 8.2 8.4 10.9 6.6 9.1 Max. 15.0 18.5 9.7 13.2 15.6 19.1 10.1 13.6 8.5 6.0 8.5 6.0 8.0 5.5 0.5 0.5 6.5 5.0 55 45 95 60 135 60 145 85 0.5 0.5 1.0 1.0 50 40 80 50 1.5 1.5 -40 to 85°C Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max. 18.5 22.0 11.5 15.0 18.5 22.0 12.0 15.5 10.0 7.0 10.0 7.0 9.5 6.5 0.5 0.5 7.5 5.0 50 40 80 50 1.5 1.5 ns MHz -55 to 125°C Unit Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max. 18.5 22.0 11.5 15.0 18.5 22.0 12.0 15.5 10.0 7.0 10.0 7.0 9.5 6.5 0.5 0.5 7.5 5.0 ns ns ns ns ns ns ns CL (pF) 15 50 15 50 15 50 15 50 50 50 50 50 50 50 50 50 50 50 15 50 15 50 50 50 tPLH tPHL Propagation Delay Time CK to Q or Q (*) 3.3(*) 2.7 3.3 2.7 2.7 (*) 3.3(*) tOSLH tOSHL Output To Output Skew Time (note1, 2) 3.3(*) 2.7 3.3(*) 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V 4/13 74LVX74 Table 9: Capacitive Characteristics Test Condition Symbol Parameter VCC (V) 3.3 3.3 fIN = 10 MHz TA = 25°C Min. Typ. 4 25 Max. 10 Value -40 to 85°C Min. Max. 10 -55 to 125°C Min. Max. 10 pF pF Unit CIN CPD Input Capacitance Power Dissipation Capacitance (note 1) 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per circuit) Figure 4: Test Circuit CL =15/50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) 5/13 74LVX74 Figure 5: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle) Figure 6: Waveform - Recovery Time (f=1MHz; 50% duty cycle) 6/13 74LVX74 Figure 7: Waveform - Propagation Delays, Minimum Pulse Width (f=1MHz; 50% duty cycle) Figure 8: Waveform - Minimum Pulse Width 7/13 74LVX74 SO-14 MECHANICAL DATA DIM. A A1 A2 B C D E e H h L k ddd 5.8 0.25 0.4 0° mm. MIN. 1.35 0.1 1.10 0.33 0.19 8.55 3.8 1.27 6.2 0.50 1.27 8° 0.100 0.228 0.010 0.016 0° TYP MAX. 1.75 0.25 1.65 0.51 0.25 8.75 4.0 MIN. 0.053 0.004 0.043 0.013 0.007 0.337 0.150 0.050 0.244 0.020 0.050 8° 0.004 inch TYP. MAX. 0.069 0.010 0.065 0.020 0.010 0.344 0.157 0016019D 8/13 74LVX74 TSSOP14 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0˚ 0.45 0.60 0.05 0.8 0.19 0.09 4.9 6.2 4.3 5 6.4 4.4 0.65 BSC 8˚ 0.75 0˚ 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 5.1 6.6 4.48 0.002 0.031 0.007 0.004 0.193 0.244 0.169 0.197 0.252 0.173 0.0256 BSC 8˚ 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0089 0.201 0.260 0.176 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080337D 9/13 74LVX74 Tape & Reel SO-14 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 6.4 9 2.1 3.9 7.9 12.8 20.2 60 22.4 6.6 9.2 2.3 4.1 8.1 0.252 0.354 0.082 0.153 0.311 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.260 0.362 0.090 0.161 0.319 MIN. TYP. MAX. 12.992 0.519 inch 10/13 74LVX74 Tape & Reel TSSOP14 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 6.7 5.3 1.6 3.9 7.9 12.8 20.2 60 22.4 6.9 5.5 1.8 4.1 8.1 0.264 0.209 0.063 0.153 0.311 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.272 0.217 0.071 0.161 0.319 MIN. TYP. MAX. 12.992 0.519 inch 11/13 74LVX74 Table 10: Revision History Date 27-Aug-2004 Revision 3 Description of Changes Ordering Codes Revision - pag. 1. 12/13 74LVX74 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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