HT68F002(SOP-8)

Cost-Effective Flash MCU with EEPROM HT68F002/HT68F0025/HT68F003 Revision: V1.41 Date: April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Table of Contents Features............................................................................................................. 5 CPU Features.......................................................................................................................... 5 Peripheral Features.................................................................................................................. 5 General Description.......................................................................................... 6 Selection Table.................................................................................................. 6 Block Diagram................................................................................................... 7 Pin Assignment................................................................................................. 7 Pin Description................................................................................................. 8 Absolute Maximum Ratings........................................................................... 10 D.C. Characteristics.........................................................................................11 A.C. Characteristics........................................................................................ 12 LVR&LVD Electrical Characteristics............................................................. 13 Power on Reset Electrical Characteristics................................................... 13 System Architecture....................................................................................... 14 Clocking and Pipelining.......................................................................................................... 14 Program Counter.................................................................................................................... 15 Stack...................................................................................................................................... 15 Arithmetic and Logic Unit – ALU............................................................................................ 16 Flash Program Memory.................................................................................. 16 Structure................................................................................................................................. 16 Special Vectors...................................................................................................................... 17 Look-up Table......................................................................................................................... 17 Table Program Example......................................................................................................... 18 In Circuit Programming.......................................................................................................... 19 On-Chip Debug Support – OCDS.......................................................................................... 20 RAM Data Memory.......................................................................................... 21 Structure................................................................................................................................. 21 General Purpose Data Memory............................................................................................. 21 Special Purpose Data Memory.............................................................................................. 21 Special Function Register Description......................................................... 24 Indirect Addressing Registers – IAR0, IAR1.......................................................................... 24 Memory Pointers – MP0, MP1............................................................................................... 24 Bank Pointer – BP.................................................................................................................. 25 Accumulator – ACC................................................................................................................ 25 Program Counter Low Register – PCL................................................................................... 25 Look-up Table Registers – TBLP, TBLH................................................................................. 25 Status Register – STATUS..................................................................................................... 26 Rev. 1.41 2 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM EEPROM Data Memory................................................................................... 28 EEPROM Data Memory Structure......................................................................................... 28 EEPROM Registers............................................................................................................... 28 Reading Data from the EEPROM ......................................................................................... 30 Writing Data to the EEPROM................................................................................................. 30 Write Protection...................................................................................................................... 30 EEPROM Interrupt................................................................................................................. 30 Programming Considerations................................................................................................. 31 Oscillators....................................................................................................... 32 Oscillator Overview................................................................................................................ 32 System Clock Configurations................................................................................................. 32 Internal RC Oscillator – HIRC................................................................................................ 32 Internal 32kHz Oscillator – LIRC............................................................................................ 33 Supplementary Oscillator....................................................................................................... 33 Operating Modes and System Clocks.......................................................... 33 System Clocks....................................................................................................................... 33 System Operation Modes....................................................................................................... 34 Control Register..................................................................................................................... 36 Operating Mode Switching .................................................................................................... 38 Standby Current Considerations............................................................................................ 42 Wake-up................................................................................................................................. 42 Watchdog Timer.............................................................................................. 43 Watchdog Timer Clock Source............................................................................................... 43 Watchdog Timer Control Register.......................................................................................... 43 Watchdog Timer Operation.................................................................................................... 44 Reset and Initialisation................................................................................... 45 Reset Functions..................................................................................................................... 45 Reset Initial Conditions.......................................................................................................... 48 Input/Output Ports.......................................................................................... 50 Pull-high Resistors................................................................................................................. 51 Port A Wake-up...................................................................................................................... 52 I/O Port Control Registers...................................................................................................... 52 Pin-Shared Functions............................................................................................................. 53 I/O Pin Structures................................................................................................................... 56 Programming Considerations................................................................................................. 56 Timer Modules – TM....................................................................................... 57 Introduction............................................................................................................................ 57 TM Operation......................................................................................................................... 57 TM Clock Source.................................................................................................................... 57 TM Interrupts.......................................................................................................................... 58 TM External Pins.................................................................................................................... 58 TM Input/Output Pin Control.................................................................................................. 58 Programming Considerations................................................................................................. 59 Rev. 1.41 3 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Standard Type TM – STM............................................................................... 60 Standard TM Operation.......................................................................................................... 60 Standard Type TM Register Description................................................................................ 61 Standard Type TM Operating Modes..................................................................................... 65 Periodic Type TM – PTM................................................................................. 75 Periodic TM Operation........................................................................................................... 75 Periodic Type TM Register Description.................................................................................. 76 Periodic Type TM Operating Modes....................................................................................... 80 Interrupts......................................................................................................... 89 Interrupt Registers.................................................................................................................. 89 Interrupt Operation................................................................................................................. 93 External Interrupt.................................................................................................................... 94 Multi-function Interrupt........................................................................................................... 94 Time Base Interrupts.............................................................................................................. 95 EEPROM Interrupt................................................................................................................. 96 TM Interrupts.......................................................................................................................... 96 Interrupt Wake-up Function.................................................................................................... 96 Programming Considerations................................................................................................. 97 Low Voltage Detector – LVD.......................................................................... 98 LVD Register.......................................................................................................................... 98 LVD Operation........................................................................................................................ 99 Application Circuits...................................................................................... 100 Instruction Set............................................................................................... 101 Introduction.......................................................................................................................... 101 Instruction Timing................................................................................................................. 101 Moving and Transferring Data.............................................................................................. 101 Arithmetic Operations........................................................................................................... 101 Logical and Rotate Operation.............................................................................................. 102 Branches and Control Transfer............................................................................................ 102 Bit Operations...................................................................................................................... 102 Table Read Operations........................................................................................................ 102 Other Operations.................................................................................................................. 102 Instruction Set Summary............................................................................. 103 Table Conventions................................................................................................................ 103 Instruction Definition.................................................................................... 105 Package Information.....................................................................................114 8-pin SOP (150mil) Outline Dimensions...............................................................................115 10-pin SOP (150mil) Outline Dimensions.............................................................................116 10-pin MSOP Outline Dimensions........................................................................................117 16-pin NSOP (150mil) Outline Dimensions...........................................................................118 Rev. 1.41 4 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Features CPU Features • Operating Voltage ♦♦ fSYS = 8MHz: 2.2V~5.5V • Up to 0.5μs instruction cycle with 8MHz system clock at VDD=5V • Power down and wake-up functions to reduce power consumption • Two Oscillators ♦♦ Internal High Speed 8MHz RC oscillator – HIRC ♦♦ Internal Low Speed 32kHz RC oscillator – LIRC • Fully intergrated internal oscillators require no external components • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • All instructions executed in one or two instruction cycles • Table read instructions • 63 powerful instructions • Up to 4 level subroutine nesting • Bit manipulation instruction Peripheral Features • Flash Program Memory: 1K×14 ~ 2K×14 • RAM Data Memory: 64×8 • True EEPROM Memory: 32×8 • Watchdog Timer function • Up to 14 bidirectional I/O lines • One pin-shared external interrupt • Multiple Timer Modules for time measure, compare match output, capture input, PWM output functions • Dual Time-Base functions for generation of fixed time interrupt signals • Low voltage reset function • Low voltage detect function • Multiple package types • Flash program memory can be re-programmed up to 100,000 times • Flash program memory data retention > 10 years • True EEPROM data memory can be re-programmed up to 1,000,000 times • True EEPROM data memory data retention > 10 years Rev. 1.41 5 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM General Description The devices are Flash Memory type 8-bit high performance RISC architecture microcontrollers. Offering users the convenience of Flash Memory multi-programming features, these devices also include a wide range of functions and features. Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile data such as serial numbers, calibration data etc. Analog features include multiple and extremely flexible Timer Modules provide timing, pulse generation, capture input, compare match output and PWM generation functions. Protective features such as an internal Watchdog Timer and Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A full choice of HIRC and LIRC oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. The inclusion of flexible I/O programming features, Time-Base functions along with many other features ensure that the devices will find excellent use in applications such as electronic metering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others. Selection Table Most features are common to all devices, the main feature distinguishing them are Program Memory and Data memory capacity. The following table summarises the main features of each device. Part No. Program Data Data Memory Memory EEPROM I/O Ext. Interrupt Timer Module Time Base Stack Package HT68F002 1K×14 64×8 32×8 8 1 10-bit STM×1 2 2 8SOP 10MSOP HT68F0025 2K×14 64×8 32×8 8 1 10-bit STM×1 2 4 8SOP 10SOP HT68F003 1K×14 64×8 32×8 14 1 10-bit STM×1 10-bit PTM×1 2 2 16NSOP Rev. 1.41 6 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Block Diagram EEPROM Data Memory Watchdog Timer Low Voltage Reset Flash/EEPROM Programming Circuitry Flash Program Memory Reset Circuit 8-bit RISC MCU Core Time Bases Interrupt Controller Internal RC Oscillators RAM Data Memory I/O Timer Modules Low Voltage Detect Pin Assignment VDD PA6/STP0I/[STCK0] 1 8 2 7 VSS PA0/[STP0]/[STP0I]/ICPDA PA5/INT/STP0B 3 6 PA1/[STP0B] PA7/[INT]/STCK0/RES/ICPCK 4 5 PA2/[INT]/STP0 VDD PA6/STP0I/[STCK0] 1 10 2 9 PA0/[STP0]/[STP0I]/ICPDA PA5/INT/STP0B 3 8 PA1/[STP0B] PA7/[INT]/STCK0/RES/ICPCK 4 7 PA4 5 6 PA2/[INT]/STP0 PA3/[INT] HT68F002 10 MSOP-A HT68F002 8 SOP-A VDD PA6/STP0I/[STCK0] 1 8 VSS PA5/INT/STP0B 2 7 3 6 PA0/[STP0]/[STP0I]/ICPDA PA1/[STP0B] 4 5 PA2/[INT]/STP0 PA7/[INT]/STCK0/RES/ICPCK VSS VDD 1 10 PA6/STP0I/[STCK0] 2 9 PA5/INT/STP0B 3 8 PA0/[STP0]/[STP0I]/ICPDA PA1/[STP0B] PA7/[INT]/STCK0/RES/ICPCK 4 7 PA2/[INT]/STP0 PA4 5 6 PA3/[INT] VSS HT68F0025 10 SOP-A HT68F0025 8 SOP-A PB2/PTP1B PB1/[PTCK1]/STP0B PB0/[PTP1I] 1 16 PB3/[PTP1] 2 15 PB4/[PTP1B] 3 14 PB5/PTP1 PA3/INT/STCK0 4 13 PA4/[INT]/PTCK1/STP0 PA2/[INT]/[STCK0]/OCDSCK/ICPCK 5 12 PA5/[INT]/PTP1I PA1 PA0/[STP0I]/OCDSDA/ICPDA 6 11 7 10 PA6/[PTCK1]/STP0I/[STP0] PA7/[PTCK1]/[STP0B]/RES VSS 8 9 VDD VDD 1 16 VSS PA6/STP0I/[STCK0] 2 15 PA5/INT/STP0B 3 14 PA0/[STP0]/[STP0I]/ICPDA PA1/[STP0B] PA7/[INT]/STCK0/RES/ICPCK PA4 4 13 PA2/[INT]/STP0 5 12 NC 6 11 PA3/[INT] NC NC OCDSCK 7 10 8 9 NC OCDSDA HT68V002/HT68V0025 16 NSOP-A HT68F003/HT68V003 16 NSOP-A Note: Bracketed pin names indicate non-default pinout remapping locations. Rev. 1.41 7 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Pin Description With the exception of the power pins and some relevant transformer control pins, all pins on these devices can be referenced by their Port name, e.g. PA0, PA1 etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the Analog to Digital Converter, Timer Module pins etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. HT68F002/HT68F0025 Pin Name PA0/[STP0]/ [STP0I]/ICPDA PA1/[STP0B] PA2/[INT]/STP0 Function OPT I/T O/T Description PA0 PAWU PAPU PASR ST CMOS General purpose I/O. Register enabled pull-up and wake-up STP0 PASR — CMOS TM0 (STM) output STP0I PASR IFS0 ST ICPDA — ST CMOS ICP Data Line PA1 PAWU PAPU PASR ST CMOS STP0B PASR — CMOS TM0 (STM) inverting output PA2 PAWU PAPU PASR ST CMOS INT PASR IFS0 ST — STP0 PASR — CMOS TM0 (STM) output PA3 PAWU PAPU PASR ST CMOS INT PASR IFS0 ST — PA4 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up PA5 PAWU PAPU PASR ST CMOS General purpose I/O. Register enabled pull-up and wake-up INT PASR IFS0 ST — STP0B PASR — CMOS TM0 (STM) inverting output PA6 PAWU PAPU ST CMOS PA3/[INT] PA4 PA5/INT/STP0B PA6/STP0I/ [STCK0] — TM0 (STM) input General purpose I/O. Register enabled pull-up and wake-up General purpose I/O. Register enabled pull-up and wake-up External interrupt input General purpose I/O. Register enabled pull-up and wake-up External interrupt input External interrupt input General purpose I/O. Register enabled pull-up and wake-up STP0I IFS0 ST — TM0 (STM) input STCK0 IFS0 ST — TM0 (STM) clock input PA7 PAWU PAPU ST INT IFS0 ST — External interrupt input STCK0 IFS0 ST — TM0 (STM) clock input RES RSTC ST — External reset input ICPCK — ST VDD VDD — PWR — Digital positive power supply VSS VSS — PWR — Digital negative power supply OCDSCK OCDSCK — ST — On Chip Debug System Clock Line (OCDS EV only) OCDSDA OCDSDA — ST PA7/[INT]/STCK0/ RES/ICPCK Rev. 1.41 General purpose I/O. Register enabled pull-up and CMOS wake-up CMOS ICP Clock Line CMOS On Chip Debug System Data Line (OCDS EV only) 8 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM HT68F003 Pin Name PA0/[STP0I]/ OCDSDA/ICPDA PA1 PA2/[INT]/ [STCK0] /OCDSCK/ICPCK PA3/INT/STCK0 PA4/[INT]/PTCK1/ STP0 PA5/[INT]/PTP1I PA6/[PTCK1]/ STP0I/[STP0] PA7/[PTCK1]/ [STP0B]/RES Rev. 1.41 Function OPT I/T O/T Description PA0 PAWU PAPU PASR ST CMOS General purpose I/O. Register enabled pull-up and wake-up STP0I PASR IFS0 ST — OCDSDA — ST CMOS On Chip Debug System Data Line (OCDS EV only) ICPDA — ST CMOS ICP Data Line PA1 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up PA2 PAWU PAPU PASR ST CMOS General purpose I/O. Register enabled pull-up and wake-up INT PASR IFS0 ST — STCK0 IFS0 ST — TM0 (STM) clock input OCDSCK — ST — On Chip Debug System Clock Line (OCDS EV only) ICPCK — ST CMOS ICP Clock Line PA3 PAWU PAPU PASR ST CMOS General purpose I/O. Register enabled pull-up and wake-up INT PASR IFS0 ST — External interrupt input STCK0 IFS0 ST — TM0 (STM) clock input PA4 PAWU PAPU PASR ST CMOS INT PASR IFS0 ST — External interrupt input PTCK1 PASR IFS0 ST — TM1 (PTM) clock input STP0 PASR — CMOS TM0 (STM) output PA5 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up INT IFS0 ST — External interrupt input PTP1I IFS0 ST — TM1 (PTM) input PA6 PAWU PAPU PASR ST CMOS PTCK1 PASR IFS0 ST — TM1 (PTM) clock input STP0I PASR IFS0 ST — TM0 (STM) input STP0 PASR — CMOS TM0 (STM) output PA7 PAWU PAPU PASR ST CMOS General purpose I/O. Register enabled pull-up and wake-up PTCK1 PASR IFS0 ST — STP0B PASR ST CMOS RES RSTC ST — 9 TM0 (STM) input External interrupt input General purpose I/O. Register enabled pull-up and wake-up General purpose I/O. Register enabled pull-up and wake-up TM1 (PTM) clock input TM0 (STM) inverting output External reset input April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Pin Name Function OPT I/T O/T PB0 PBPU PBSR ST CMOS PTP1I PBSR IFS0 ST — PB1 PBPU PBSR ST CMOS PTCK1 PBSR IFS0 ST — STP0B PBSR ST CMOS TM0 (STM) inverting output PB2 PBPU PBSR ST CMOS General purpose I/O. Register enabled pull-up PTP1B PBSR ST CMOS TM1 (PTM) inverting output PB3 PBPU PBSR ST CMOS General purpose I/O. Register enabled pull-up PTP1 PBSR — CMOS TM1 (PTM) output PB4 PBPU PBSR ST CMOS General purpose I/O. Register enabled pull-up PTP1B PBSR — CMOS TM1 (PTM) inverting output PB5 PBPU PBSR ST CMOS General purpose I/O. Register enabled pull-up PTP1 PBSR — CMOS TM1 (PTM) output VDD VDD — PWR — Digital positive power supply VSS VSS — PWR — Digital negative power supply PB0/[PTP1I] PB1/[PTCK1]/ STP0B PB2/PTP1B PB3/[PTP1] PB4/[PTP1B] PB5/PTP1 Description General purpose I/O. Register enabled pull-up TM1 (PTM) input General purpose I/O. Register enabled pull-up TM1 (PTM) clock input Note: I/T: Input type; O/T: Output type OPT: Optional by register option PWR: Power; ST: Schmitt Trigger input CMOS: CMOS output Absolute Maximum Ratings Supply Voltage.................................................................................................VSS−0.3V to VSS+6.0V Input Voltage...................................................................................................VSS−0.3V to VDD+0.3V Storage Temperature.....................................................................................................-50˚C to 125˚C Operating Temperature...................................................................................................-40˚C to 85˚C IOL Total...................................................................................................................................... 80mA IOH Total.....................................................................................................................................-80mA Total Power Dissipation.......................................................................................................... 500mW Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to these devices. Functional operation of these devices at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect devices reliability. Rev. 1.41 10 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM D.C. Characteristics Ta = 25°C Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit VDD Operating Voltage (HIRC) — fSYS=8MHz 2.2 — 5.5 V IDD1 Operating Current, Normal Mode, fSYS=fH (HIRC) 3V No load, fH=8MHz, WDT enable, LVR enable — 1.0 2.0 mA — 2.0 3.0 mA No load, fSYS=LIRC, WDT enable, LVR enable — 20 30 μA — 30 60 μA No load, fSYS=fH/2, WDT enable, LVR enable — 1.0 1.5 mA — 1.5 2.0 mA No load, fSYS=fH/4, WDT enable, LVR enable — 0.9 1.3 mA — 1.3 1.8 mA No load, fSYS=fH/8, WDT enable, LVR enable — 0.8 1.1 mA — 1.1 1.6 mA — 0.7 1.0 mA — mA IDD2 Operating Current, Slow Mode, fSYS=fL=LIRC 5V 3V 5V 3V 5V 3V 5V 3V IDD3 Operating Current, Normal Mode, fH=8MHz (HIRC) 5V 3V 5V 3V 5V 3V 5V 3V No load, fSYS=fH/16, WDT enable, LVR enable 1.0 1.4 No load, fSYS=fH/32, WDT enable, LVR enable — 0.6 0.9 mA — 0.9 1.2 mA No load, fSYS=fH/64, WDT enable, LVR enable — 0.5 0.8 mA — 0.8 1.1 mA No load, WDT enable, LVR disable — 1.3 3.0 μA — 5.0 10 μA No load, WDT enable, fSYS=8MHz on — 0.8 1.6 mA — 1.0 2.0 mA No load, WDT disable, LVR disable — 0.1 1.0 μA — 0.3 2.0 μA — 1.3 5.0 μA IIDLE0 IDLE0 Mode Standby Current (LIRC on) 5V IIDLE1 IDLE1 Mode Standby Current (HIRC) 5V ISLEEP0 SLEEP0 Mode Standby Current (LIRC off) 5V ISLEEP1 SLEEP1 Mode Standby Current (LIRC on) — 2.2 10 μA VIL1 Input Low Voltage for I/O Ports or Input Pins except RES pin 5V — 0 — 1.5 V — — 0 — 0.2VDD V VIH1 Input High Voltage for I/O Ports or Input Pins except RES pin 5V — 3.5 — 5.0 V — — 0.8VDD — VDD V VIL2 Input Low Voltage (RES) — — 0 — 0.4VDD V VIH2 Input High Voltage (RES) — — 0.9VDD — VDD V IOL I/O Port Sink Current IOH I/O Port, Source Current 3V 3V 3V 5V No load, WDT enable, LVR disable 3V VOL=0.1VDD 18 36 — mA 5V VOL=0.1VDD 40 80 — mA 3V VOH=0.9VDD -3 -6 — mA 5V VOH=0.9VDD -7 -14 — mA 3V — 20 60 100 kΩ 5V — 10 30 50 kΩ RPH Pull-high Resistance for I/O Ports IOCDS Operating Current, Normal Mode, fSYS=fH (HIRC) (for OCDS EV testing, connect to an e-Link) 3V No load, fH=8MHz, WDT enable — 1.4 2.0 mA ILEAK Input Leakage Current 5V VIN=VDD or VIN=VSS — — ±1 μA Rev. 1.41 11 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM A.C. Characteristics Ta = 25°C Symbol fCPU fHIRC Parameter Operating Clock System Clock (HIRC) Test Conditions VDD Condition 2.2~5.5V — 3V/5V Ta = 25°C 3V/5V Min. Typ. Max. Unit DC — 8 MHz -2% 8 +2% MHz Ta = 0°C to 70°C -5% 8 +5% MHz 2.2V~5.5V Ta = 0°C to 70°C -8% 8 +8% MHz 2.2V~5.5V Ta = -40°C to 85°C -12% 8 +12% MHz fLIRC System Clock (LIRC) 8 32 50 kHz tTIMER xTCKn, xTPnI Input Pulse Width 2.2V~5.5V Ta = -40°C to 85°C — — 0.3 — — μs tRES External Reset Low Pulse Width — — 10 — — μs tINT Interrupt Pulse Width — — 0.3 — — μs tEERD EEPROM Read Time — — — 2 4 tSYS tEEWR EEPROM Write Time — — — 4 10 ms tSST System Start-up Timer Period (Wake-up from HALT, fSYS off at HALT State) — fSYS = HIRC 16 — — fSYS = LIRC 2 — — System Reset Delay Time (Power On Reset, LVR Reset, WDT S/W Reset(WDTC)) — — 25 50 100 ms System Reset Delay Time (RES Reset, WDT Normal Reset) — — 8.3 16.7 33.3 ms tRSTD tSYS Note: 1. tSYS= 1/fSYS 2. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1μF decoupling capacitor should be connected between VDD and VSS and located as close to the device as possible. Rev. 1.41 12 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM LVR&LVD Electrical Characteristics Symbol Parameter Test Conditions VDD VDD Operating Voltage — VLVR Low Voltage Reset Voltage — VLVD Low Voltage Detector Voltage — Min. Conditions — LVR Enable, 2.1V option Low Voltage Width to Reset tLVDS LVDO stable time Max. Unit 1.9 — 5.5 V -5% 2.1 +5% V ENLVD = 1, VLVD = 2.0V 2.0 V ENLVD = 1, VLVD = 2.2V 2.2 V ENLVD = 1, VLVD = 2.4V 2.4 V ENLVD = 1, VLVD = 2.7V 2.7 -5% ENLVD = 1, VLVD = 3.0V 3.0 +5% V V ENLVD = 1, VLVD = 3.3V 3.3 V ENLVD = 1, VLVD = 3.6V 3.6 V ENLVD = 1, VLVD = 4.0V tLVR Typ. — 4.0 — 160 320 V 640 μs — For LVR enable, LVD off→on — — 15 μs — For LVR disable, LVD off→on — — 150 μs Power on Reset Electrical Characteristics Ta = 25°C Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV RRPOR VDD Rising Rate to Ensure Power-on Reset — — 0.035 — — V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — ms             Rev. 1.41 13       April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The device takes advantage of the usual features found within RISC microcontrollers providing increased speed of operation and Periodic performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O control system with maximum reliability and flexibility. This makes these devices suitable for lowcost, high-volume production for controller applications Clocking and Pipelining The main system clock, derived from either a HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute.              
                                                   
                                                                                       System Clock and Pipelining For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. Rev. 1.41 14 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM    
                                                                                                          Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as "JMP" or "CALL" that demand a jump to a nonconsecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Device Program Counter Program Counter High byte PCL Register HT68F002/HT68F003 PC9~PC8 PCL7~PCL0 HT68F0025 PC10~PC8 PCL7~PCL0 The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. Rev. 1.41 15 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Program Counter Top of Stack Stack Level 1 : : Stack Pointer Bottom of Stack Program Memory Stack Level N Device Stack Levels HT68F002/HT68F003 N=2 HT68F0025 N=4 Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA • Rotation: RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC • Increment and Decrement: INCA, INC, DECA, DEC • Branch decision: JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Flash Program Memory The Program Memory is the location where the user code or program is stored. For these devices the Program Memory are Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, these Flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 1K×14 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. Device Rev. 1.41 Capacity HT68F002/HT68F003 1K×14 HT68F0025 2K×14 16 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Program Memory Structure Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by these devices reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP. This register defines the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the "TABRDC[m]" or "TABRDL[m]" instructions, respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as "0". The accompanying diagram illustrates the addressing data flow of the look-up table.             
                                        Rev. 1.41                                            17 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is "300H" which refers to the start address of the last page within the 1K words Program Memory of the device. The table pointer is setup here to have an initial value of "06H". This will ensure that the first data read from the data table will be at the Program Memory address "306H" or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the "TABRDC[m]" instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the "TABRDC[m]" instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Table Read Program Example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a ; to the last page or present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address "306H" transferred to tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address "305H" transferred to tempreg2 and TBLH in this ; example the data "1AH" is transferred to tempreg1 and data "0FH" to ; register tempreg2 : : org 300h ; sets initial address of program memory dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : Rev. 1.41 18 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM In Circuit Programming The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. Holtek Write Pins MCU Programming Pins HT68F002/HT68F0025 ICPDA PA0 ICPCK PA7 Function HT68F003 Programming Serial Data PA2 Programming Serial Clock VDD VDD Power Supply VSS VSS Ground The Program Memory and EEPROM data memory can both be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply and ground. The technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. W r ite r C o n n e c to r S ig n a ls M C U P r o g r a m m in g P in s W r ite r C o n n e c to r S ig n a ls M C U W r ite r _ V D D V D D W r ite r _ V D D V D D IC P D A P A 0 IC P D A P A 0 IC P C K P A 7 IC P C K P A 2 W r ite r _ V S S V S S W r ite r _ V S S V S S * * * * T o o th e r C ir c u it T o o th e r C ir c u it P r o g r a m m in g P in s HT68F002/HT68F0025 HT68F003 Note: * may be resistor or capacitor. The resistance of * must be greater than 1k or the capacitance of * must be less than 1nF. Rev. 1.41 19 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM On-Chip Debug Support – OCDS There is an EV chip which is used to emulate the HT68F00x device series. This EV chip device also provides an "On-Chip Debug" function to debug the device during the development process. The EV chip and the actual MCU devices are almost functionally compatible except for the "OnChip Debug" function. Users can use the EV chip device to emulate the real chip device behavior by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip for debugging, other functions which are shared with the OCDSDA and OCDSCK pins in the actual MCU device will have no effect in the EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For a more detailed OCDS description, refer to the corresponding document named "Holtek e-Link for 8-bit MCU OCDS User’s Guide". Rev. 1.41 Holtek e-Link Pins EV Chip Pins OCDSDA OCDSDA On-chip Debug Support Data/Address input/output OCDSCK OCDSCK On-chip Debug Support Clock input VDD VDD Power Supply GND VSS Ground 20 Pin Description April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM RAM Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Structure Divided into two sections, the first of these is an area of RAM, known as the Special Function Data Memory. Here are located registers which are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is known as the General Purpose Data Memory, which is reserved for general purpose use. All locations within this area are read and write accessible under program control. The overall Data Memory is subdivided into two banks. The Special Purpose Data Memory registers are accessible in all banks, with the exception of the EEC register at address 40H, which is only accessible in Bank 1. Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value. The start address of the Data Memory for all devices is the address 00H. General Purpose Data Memory There is 64×8 bytes of general purpose data memory which are arranged in 40H~7FH of Bank 0 and Bank1. All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user programing for both reading and writing operations. By using the bit operation instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value "00H". Rev. 1.41 Device Capacity Bank 0 Bank 1 HT68F002 HT68F0025 HT68F003 64×8 40H~7FH 40H EEC register only 21 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Bank0 & Bank1 IAR0 MP0 IAR1 MP1 BP ACC PCL TBLP TBLH Unused STATUS SMOD LVDC INTEG INTC0 INTC1 Unused MFI0 Unused Unused PA PAC PAPU PAWU IFS0 WDTC Unused TBC SMOD1 Unused EEA EED 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH ~ 3FH Bank0 & Bank1 Unused Unused Unused Unused Unused RSTC PASR Unused STM0C0 STM0C1 STM0DL STM0DH STM0AL STM0AH Unused : Unused, read as “00” HT68F002/HT68F0025 Special Purpose Data Memory Structure Rev. 1.41 22 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Bank0 & Bank1 IAR0 MP0 IAR1 MP1 BP ACC PCL TBLP TBLH Unused STATUS SMOD LVDC INTEG INTC0 INTC1 Unused MFI0 MFI1 Unused PA PAC PAPU PAWU IFS0 WDTC Unused TBC SMOD1 Unused EEA EED 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH ~ 3FH Bank0 & Bank1 Unused Unused Unused Unused Unused RSTC PASR PBSR STM0C0 STM0C1 STM0DL STM0DH STM0AL STM0AH Unused PB PBC PBPU PTM1C0 PTM1C1 PTM1DL PTM1DH PTM1AL PTM1AH PTM1RPL PTM1RPH Unused : Unused, read as “00” HT68F003 Special Purpose Data Memory Structure 40H EEC General Purpose Data Memory Unused 7FH HT68F002/HT68F0025/HT68F003 General Purpose Data Memory Rev. 1.41 23 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section, however several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of "00H" and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all banks according to BP register. Direct Addressing can only be used with Bank 0, all other Banks must be addressed indirectly using MP1 and IAR1. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Indirect Addressing Program Example data .section ´data´ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ´code´ org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp0,a ; setup memory pointer with first RAM address loop: clr IAR0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. Rev. 1.41 24 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Bank Pointer – BP For this series of devices, the Data Memory is divided into two banks, Bank0 and Bank1. Selecting the required Data Memory area is achieved using the Bank Pointer. Bit 0 of the Bank Pointer is used to select Data Memory Banks 0~1. The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within any bank. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from Bank1 must be implemented using Indirect Addressing. BP Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — — DMBP0 R/W — — — — — — — R/W POR — — — — — — — 0 Bit 7 ~ 1 Unimplemented, read as "0" Bit 0 DMBP0: Select Data Memory Banks 0: Bank 0 1: Bank 1 Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user-defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBLH These two special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP is the table pointer and indicate the location where the table data is located. Its value must be setup before any table read commands are executed. Its value can be changed, for example using the "INC" or "DEC" instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Rev. 1.41 25 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing the "HALT" or "CLR WDT" instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the "CLR WDT" instruction. PDF is set by executing the "HALT" instruction. • TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Rev. 1.41 26 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM STATUS Register Bit 7 6 5 4 3 2 1 0 Name — — TO PDF OV Z AC C R/W — — R R R/W R/W R/W R/W POR — — 0 0 × × × × "×" unknown Bit 7~6 Unimplemented, read as "0" Bit 5 TO: Watchdog Time-Out flag 0: After power up or executing the "CLR WDT" or "HALT" instruction 1: A watchdog time-out occurred. Bit 4 PDF: Power down flag 0: After power up or executing the "CLR WDT" instruction 1: By executing the "HALT" instruction Bit 3 OV: Overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2 Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1 AC: Auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0 C: Carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction. Rev. 1.41 27 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM EEPROM Data Memory These devices contain an area of internal EEPROM Data Memory. EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form of memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. EEPROM Data Memory Structure The EEPROM Data Memory capacity is 32×8 bits for this series of devices. Unlike the Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped and is therefore not directly accessible in the same way as the other types of memory. Read and Write operations to the EEPROM are carried out in single byte operations using one address register and one data register and a single control register in Bank 1. EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory. These are the address registers, EEA, the data register, EED and a single control register, EEC. As both the EEA and EED registers are located in Bank 0, they can be directly accessed in the same way as any other Special Function Register. The EEC register however, being located in Bank1, cannot be directly addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer and Indirect Addressing Register, IAR1. Because the EEC control register is located at address 40H in Bank 1, the MP1 Memory Pointer must first be set to the value 40H and the Bank Pointer register, BP, set to the value, 01H, before any operations on the EEC register are executed. EEPROM Control Registers List Bit Register Name 7 6 5 4 3 2 1 0 EEA — — — D4 D3 D2 D1 D0 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC — — — — WREN WR RDEN RD EEA Register Rev. 1.41 Bit 7 6 5 4 3 2 1 0 Name — — — D4 D3 D2 D1 D0 R/W — — — R/W R/W R/W R/W R/W POR — — — 0 0 0 0 0 Bit 7 ~ 5 Unimplemented, read as "0" Bit 4 ~ 0 Data EEPROM address Data EEPROM address bit 4 ~ bit 0 28 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM EED Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 2 1 0 Bit 7 ~ 0 Data EEPROM data Data EEPROM data bit 7 ~ bit 0 EEC Register Bit 7 6 5 4 3 Name — — — — WREN WR RDEN RD R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7 ~ 4 Unimplemented, read as "0" Bit 3 WREN: Data EEPROM Write Enable 0: Disable 1: Enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. Bit 2 WR: EEPROM Write Control 0: Write cycle has finished 1: Activate a write cycle This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high. Bit 1 RDEN: Data EEPROM Read Enable 0: Disable 1: Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations. Bit 0 RD: EEPROM Read Control 0: Read cycle has finished 1: Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high. Note: The WREN, WR, RDEN and RD can not be set to "1" at the same time in one instruction. The WR and RD can not be set to "1" at the same time. Rev. 1.41 29 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Writing Data to the EEPROM The EEPROM address of the data to be written must first be placed in the EEA register and the data placed in the EED register. To write data to the EEPROM, the write enable bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the EEC register must be immediately set high to initiate a write cycle. These two instructions must be executed consecutively. The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the devices are powered-on the Write Enable bit in the control register will be cleared preventing any write operations. Also at power-on the Bank Pointer, BP, will be reset to zero, which means that Data Memory Bank 0 will be selected. As the EEPROM control register is located in Bank 1, this adds a further measure of protection against spurious write operations. During normal program operation, ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect write operations. EEPROM Interrupt The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. When an EEPROM write cycle ends, the DEF request flag will be set. If the global, EEPROM Interrupt are enabled and the stack is not full, a subroutine call to the EEPROM Interrupt vector, will take place. When the EEPROM Interrupt is serviced, the EEPROM Interrupt flag DEF will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Rev. 1.41 30 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be Periodic by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Bank Pointer could be normally cleared to zero as this would inhibit access to Bank 1where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that the devices should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally complete. Otherwise, the EEPROM read or write operation will fail. Programming Examples • Reading data from the EEPROM - polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, 040H MOV MP1, A MOV A, 01H MOV BP, A SET IAR1.1 SET IAR1.0 BACK: SZ IAR1.0 JMP BACK CLR IAR1 CLR BP MOV A, EED MOV READ_DATA, A ; user defined address ; setup memory pointer MP1 ; MP1 points to EEC register ; setup Bank Pointer ; set RDEN bit, enable read operations ; start Read Cycle - set RD bit ; check for read cycle end ; disable EEPROM write ; move read data to register • Writing Data to the EEPROM - polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, EEPROM_DATA MOV EED, A MOV A, 040H MOV MP1, A MOV A, 01H MOV BP, A CLR EMI SET IAR1.3 SET IAR1.2 SET EMI BACK: SZ IAR1.2 JMP BACK CLR IAR1 CLR BP Rev. 1.41 ; user defined address ; user defined data ; setup memory pointer MP1 ; MP1 points to EEC register ; setup Bank Pointer ; set WREN bit, enable write operations ; start Write Cycle - set WR bit– executed immediately after ; set WREN bit ; check for write cycle end ; disable EEPROM write 31 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Oscillators Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. Two fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. The higher frequency oscillator provides higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillator. With the capability of dynamically switching between fast and slow system clock, these devices have the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. Type Name Freq. Internal High Speed RC HIRC 8MHz Internal Low Speed RC LIRC 32kHz Oscillator Types System Clock Configurations There are two methods of generating the system clock, a high speed oscillator and a low speed oscillator. The high speed oscillator is the internal 8MHz RC oscillator. The low speed oscillator is the internal 32kHz RC oscillator. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the HLCLK bit and CKS2 ~ CKS0 bits in the SMOD register and as the system clock can be dynamically selected. fH/2 fH/4 High Speed Oscillator HIRC fH/8 fH Prescaler fSYS fH/16 fH/32 fH/64 HLCLK CKS2~CKS0 bits Low Speed Oscillator LIRC fL System Clock Configurations Internal RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a fixed frequency of 8MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at temperature of 25°C degrees, the fixed oscillation frequency of the HIRC will have a tolerance within 2%. Rev. 1.41 32 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Internal 32kHz Oscillator – LIRC The internal 32kHz System Oscillator is the low frequency oscillator. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. Supplementary Oscillator The low speed oscillator, in addition to providing a system clock source is also used to provide a clock source to two other device functions. These are the Watchdog Timer and the Time Base Interrupts. Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks These devices have two different clock sources for both the CPU and peripheral function operation. By providing the user with clock options using register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency, fH, or a low frequency, fL, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from HIRC oscillator. The low speed system clock source can be sourced from the internal clock fL. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. There is one additional internal clock for the peripheral circuits, the Time Base clock, fTBC. fTBC is sourced from the LIRC oscillators. The fTBC clock is used as a source for the Time Base interrupt functions and for the TMs. Rev. 1.41 33 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM fH/2 fH/4 High Speed Oscillator fH/8 fH HIRC Prescaler fSYS fH/16 fH/32 fH/64 HLCLK CKS2~CKS0 bits Low Speed Oscillator fLIRC LIRC fL WDT fTBC fTB IDLEN Time Base 0 fSYS/4 Time Base 1 TBCK System Clock Configurations Note: When the system clock source fSYS is switched to fL from fH, the high speed oscillation will stop to conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use. System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0, SLEEP1, IDLE0 and IDLE1 modes are used when the microcontroller CPU is switched off to conserve power. Rev. 1.41 Description Operating Mode CPU fSYS fLIRC NORMAL mode On fH~fH/64 On On SLOW mode On fL On On IDLE0 mode Off Off On On fTBC IDLE1 mode Off On On On SLEEP0 mode Off Off Off Off SLEEP1 mode Off Off On Off 34 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided the high speed oscillator. This mode operates allowing the microcontroller to operate normally with a clock source will come from the high speed oscillator HIRC. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 and HLCLK bits in the SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used will be from the low speed oscillator LIRC. Running the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW Mode, the fH is off. SLEEP0 Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP0 mode the CPU will be stopped, and the fLIRC clock will be stopped too, and the Watchdog Timer function is disabled. SLEEP1 Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP1 mode the CPU will be stopped. However the fLIRC clocks will continue to operate if the Watchdog Timer function is enabled. IDLE0 Mode The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the SMOD1 register is low. In the IDLE0 Mode the system oscillator will be inhibited from driving the CPU but some peripheral functions will remain operational such as the Watchdog Timer and TMs. In the IDLE0 Mode, the system oscillator will be stopped. IDLE1 Mode The IDLE1 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the SMOD1 register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational such as the Watchdog Timer and TMs. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. In the IDLE1 Mode, the Watchdog Timer clock, fLIRC, will be on. Rev. 1.41 35 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Control Register A single register, SMOD, is used for overall control of the internal clocks within the device. SMOD Register Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 — LTO HTO IDLEN HLCLK R/W R/W R/W R/W — R R R/W R/W POR 0 0 0 — 0 0 1 1 Bit 7 ~ 5 CKS2 ~ CKS0: The system clock selection when HLCLK is "0" 000: fL (fLIRC) 001: fL (fLIRC) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which can be the LIRC, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4 Unimplemented, read as "0" Bit 3 LTO: Low speed system oscillator ready flag 0: Not ready 1: Ready This is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. The flag will be low when in the SLEEP0 mode, but after a wake-up has occurred the flag will change to a high level after 1~2 cycles if the LIRC oscillator is used. Bit 2 HTO: High speed system oscillator ready flag 0: Not ready 1: Ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to "0" by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as "1" by the application program after device power-on. Bit 1 IDLEN: IDLE Mode Control 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. Bit 0 HLCLK: System Clock Selection 0: fH/2 ~ fH/64 or fL 1: fH This bit is used to select if the fH clock or the fH/2 ~ fH/64 or fL clock is used as the system clock. When the bit is high the fH clock will be selected and if low the fH/2 ~ fH/64 or fL clock will be selected. When system clock switches from the fH clock to the fL clock and the fH clock will be automatically switched off to conserve power. Rev. 1.41 36 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM SMOD1 Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — D3 LVRF — WRF R/W R/W — — — R/W R/W — R/W POR 0 — — — 0 x — 0 "x" unknown Bit 7 FSYSON: fSYS Control in IDLE Mode 0: Disable 1: Enable Bit 6~4 Unimplemented, read as "0" Bit 3 D3: Reserved bit Bit 2 LVRF: LVR function reset flag 0: Not active 1: Active This bit can be clear to "0", but can not be set to "1". Bit 1 Unimplemented, read as "0" Bit 0 WRF: WDT Control register software reset flag 0: Not occur 1: Occurred This bit is set to 1 by the WDT Control register software reset and cleared by the application program. Note that this bit can only be cleared to 0 by the application program. Rev. 1.41 37 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Operating Mode Switching The devices can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/ SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the SMOD1 register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, fH, to the clock source, fH/2~fH/64 or fL. If the clock is from the fL, the high speed clock source will stop running to conserve power. When this happens it must be noted that the fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the TMs.                                       ­                                                                                ­                                                           
                                                 
    Rev. 1.41 38                           April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by setting the HLCLK bit to "0" and setting the CKS2~CKS0 bits to "000" or "001" in the SMOD register.This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LIRC oscillator and therefore requires this oscillator to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register.                                           

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                Entering the SLEEP0 Mode There is only one way for the devices to enter the SLEEP0 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the WDT and LVD both off. When this instruction is executed under the conditions described above, the following will occur: • The system clock, WDT clock and Time Base clock will be stopped and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and stopped. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Rev. 1.41 40 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Entering the SLEEP1 Mode There is only one way for the devices to enter the SLEEP1 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the WDT or LVD on. When this instruction is executed under the conditions described above, the following will occur: • The system clock and Time Base clock will be stopped and the application program will stop at the "HALT" instruction, but the WDT or LVD will remain with the clock source coming from the fLIRC clock. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT is enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the FSYSON bit in SMOD1 register equal to "0". When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the "HALT" instruction, but the Time Base clock will be on. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT is enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE1 Mode There is only one way for the devices to enter the IDLE1 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the FSYSON bit in SMOD1 register equal to "1". When this instruction is executed under the conditions described above, the following will occur: • The system clock and Time Base clock will be on and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT is enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Rev. 1.41 41 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the devices to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external reset • An external falling edge on Port A • A system interrupt • A WDT overflow If the system is woken up by an external reset, the device will experience a full system reset, however, If these devices are woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the "HALT" instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "HALT" instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Rev. 1.41 42 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal fLIRC clock which is supplied by the LIRC oscillator. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 215 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. The WDT can be enabled/disabled using the WDTC register. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable/disable operation. The WRF software reset flag will be indicated in the SMOD1 register. These registers control the overall operation of the Watchdog Timer. WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~ 3 WE4 ~ WE0: WDT function software control 10101: WDT disable 01010: WDT enable Other values: Reset MCU When these bits are changed to any other values by the environmental noise to reset the microcontroller, the reset operation will be activated after 2~3 LIRC clock cycles and the WRF bit will be set to 1to indicate the reset source. Bit 2~ 0 WS2 ~ WS0: WDT Time-out period selection 000: 28/ fLIRC 001: 29/fLIRC 010: 210/fLIRC 011: 211/fLIRC (default) 100: 212/fLIRC 101: 213/fLIRC 110: 214/fLIRC 111: 215/fLIRC These three bits determine the division ratio of the Watchdog Timer sourece clock, which in turn determines the timeout period. SMOD1 Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — — R/W R/W — — — D3 LVRF — WRF — R/W R/W — POR 0 — — R/W — 0 x — 0 "x" unknown Bit 7 FSYSON: fSYS Control in IDLE Mode 0: Disable 1: Enable Rev. 1.41 43 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Bit 6~4 Unimplemented, read as "0" Bit 3 D3: Reserved bit Bit 2 LVRF: LVR function reset flag 0: Not active 1: Active This bit can be clear to "0", but can not be set to "1". Bit 1 Unimplemented, read as "0" Bit 0 WRF: WDT Control register software reset flag 0: Not occur 1: Occurred This bit is set to 1 by the WDT Control register software reset and cleared by the application program. Note that this bit can only be cleared to 0 by the application program. Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, the clear WDT instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. With regard to the Watchdog Timer enable/disable function, there are five bits, WE4~WE0, in the WDTC register to additional enable/disable and reset control of the Watchdog Timer. WE4 ~ WE0 Bits WDT Function 10101B Disable 01010B Enable Any other value Reset MCU Watchdog Timer Enable/Disable Control Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Four methods can be adopted to clear the contents of the Watchdog Timer. The first is a WDT reset, which means a value other than 01010B and 10101B is written into the WE4~WE0 bit locations, the second is an external hardware reset, which means a low level on the external reset pin, the third is using the Watchdog Timer software clear instructions and the fourth is via a HALT instruction. There is only one method of using software instruction to clear the Watchdog Timer. That is to use the single "CLR WDT" instruction to clear the WDT. The maximum time-out period is when the 215 division ratio is selected. As an example, with a 32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 215 division ratio, and a minimum timeout of 7.8ms for the 28 division ration. Rev. 1.41 44 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM WDTC Register WE4~WE0 bits Reset MCU CLR RES pin reset “CLR WDT”Instruction “HALT”Instruction LIRC fLIRC 11-stage Divider 7-stage Divider WDT Time-out (28/fLIRC ~ 215/fLIRC) 8-to-1 MUX WS2~WS0 (fLIRC/21 ~ fLIRC/211) Watchdog Timer Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the devices can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are several ways in which a microcontroller reset can occur, through events occurring both internally and externally: Rev. 1.41 45 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs.                                 Note: tRSTD is power-on delay, typical time=50ms Power-On Reset Timing Chart RES Pin Reset Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer. For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimize any stray noise interference. For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended.                                                  Note: "*" It is recommended that this component is added for added ESD protection "**" It is recommended that this component is added in environments where power line noiseis significant External RES Circuit Pulling the RES Pin low using external hardware will also execute a device reset. In this case, as in the case of other resets, the Program Counter will reset to zero and program execution initiated from this point. Rev. 1.41 46 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM                               Note: tRSTD is power-on delay, typical time=16.7ms RES Reset Timing Chart • RSTC External Reset Register Bit 7 6 5 4 3 2 1 0 Name RSTC7 RSTC6 RSTC5 RSTC4 RSTC3 RSTC2 RSTC1 RSTC0 R/W R/W R/W R/W R/W R R R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7 ~ 0 RSTC7 ~ RSTC0: PA7/RES selection 01010101: configured as PA7 pin or other function 10101010: configured as RES pin Other Values: Inhibit to use All reset will reset this register as POR value except WDT time out Hardware warm reset. Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device and provide an MCU reset should the value fall below a certain predefined level. The LVR function is always enabled during the normal and slow modes with a specific LVR voltage VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally and the LVRF bit in the SMOD1 register will also be set to1. For a valid LVR signal, a low voltage, i.e., a voltage in the range between 0.9V~ VLVR must exist for greater than the value tLVR specified in the A.C. characteristics. If the low voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR is 2.1V, the LVR will reset the device after 2~3 LIRC clock cycles. Note that the LVR function will be automatically disabled when the device enters the SLEEP/IDLE mode.                       Note:tRSTD is power-on delay, typical time=50ms Low Voltage Reset Timing Chart • SMOD1 Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — D3 LVRF — WRF R/W R/W — — — R/W R/W — R/W POR 0 — — — 0 x — 0 "x" unknown Bit 7 FSYSON: fSYS Control in IDLE Mode Describe elsewhere Bit 6~4 Unimplemented, read as "0" Bit 3 D3: Reserved bit Rev. 1.41 47 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Bit 2 LVRF: LVR function reset flag 0: Not active 1: Active This bit can be clear to "0", but can not be set to "1". Bit 1 Unimplemented, read as "0" Bit 0 WRF: WDT Control register software reset flag Describe elsewhere Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as an LVR reset except that the Watchdog time-out flag TO will be set to "1".                              Note: tRSTD is power-on delay, typical time=16.7ms WDT Time-out Reset during Normal Operation Timing Chart Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics for tSST details.                       WDT Time-out Reset during SLEEP or IDLE Timing Chart Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 0 Power-on reset RESET Conditions u u LVR reset during NORMAL or SLOW Mode operation 1 u WDT time-out reset during NORMAL or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation Note: "u" stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Rev. 1.41 Condition After RESET Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Clear after reset, WDT begins counting Timer Modules Timer Modules will be turned off Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack 48 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation for the larger package type. HT68F0025 HT68F003 Program Counter HT68F002 Register Reset (Power On) ● ● ● 000H WDT Time-out (Normal Operation) RES Reset (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* 000H 000H 000H 000H MP0 ● ● ● 1xxx xxxx 1xxx xxxx 1xxx xxxx 1xxx xxxx 1uuu uuuu MP1 ● ● ● 1xxx xxxx 1xxx xxxx 1xxx xxxx 1xxx xxxx 1uuu uuuu BP ● ● ● ---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- ---u ACC ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu PCL ● ● ● 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 TBLP ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH ● ● ● --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu STATUS ● ● ● --00 xxxx --1u uuuu --uu uuuu --01 uuuu - - 11 u u u u SMOD ● ● ● 0 0 0 - 0 0 11 0 0 0 - 0 0 11 0 0 0 - 0 0 11 0 0 0 - 0 0 11 uuu- uuuu LVDC ● ● ● --00 -000 --00 -000 --00 -000 --00 -000 --uu -uuu INTEG ● ● ● ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ● INTC0 INTC1 MFI0 ● ● ● ● ● 0-00 0-00 0-00 0-00 0-00 0-00 0-00 0-00 u-uu u-uu ● ● ● --00 --00 --00 --00 --00 --00 --00 --00 --uu --uu ● --00 --00 --00 --00 --00 --00 --00 --00 --uu --uu ● ● ● 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu MFI1 PA -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu --00 --00 --00 --00 --00 --00 --00 --00 --uu --uu PAC ● ● ● 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PAPU ● ● ● 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu PAWU ● ● ● 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ● ● --00 --00 --00 --00 --00 --00 --00 --00 --uu --uu ● 0000 0-00 0000 0-00 0000 0-00 0000 0-00 uuuu u-uu IFS0 WDTC ● ● ● 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 uuuu uuuu TBC ● ● ● 0 0 11 - 111 0 0 11 - 111 0 0 11 - 111 0 0 11 - 111 uuuu –uuu SMOD1 ● ● ● 0--- 0x-0 0--- 0x-0 0--- 0x-0 0--- 0x-0 u--- uu-u EEA ● ● ● ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---u uuuu EED ● ● ● 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu RSTC ● ● ● 0101 0101 0101 0101 0101 0101 0101 0101 uuuu uuuu ● ● -0-0 -0-0 -0-0 -0-0 -0-0 -0-0 -0-0 -0-0 -u-u -u-u ● 000- ---- 000- ---- 000- ---- 000- ---- uuu- ---- PASR PBSR STM0C0 ● ● ● --00 000- --00 000- --00 000- --00 000- --uu uuu- ● 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu STM0C1 ● ● ● 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu STM0DL ● ● ● 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu STM0DH ● ● ● ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu STM0AL ● ● ● 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu STM0AH ● ● ● ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu Rev. 1.41 49 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM HT68F003 HT68F0025 HT68F002 Register Reset (Power On) WDT Time-out (Normal Operation) RES Reset (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* PB ● - - 11 1111 - - 11 1111 - - 11 1111 - - 11 1111 --uu uuuu PBC ● - - 11 1111 - - 11 1111 - - 11 1111 - - 11 1111 --uu uuuu PBPU ● --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu PTM1C0 ● 0000 0--- 0000 0--- 0000 0--- 0000 0--- uuuu u--- PTM1C1 ● 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM1DL ● 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM1DH ● ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu PTM1AL ● 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM1AH ● ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu PTM1RPL ● 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM1RPH ● ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ● ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu EEC ● ● Note: "*" stands for warm reset "-" not implemented "u" stands for "unchanged" "x" stands for "unknown" Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The devices provide bidirectional input/output lines labeled with port names PA and PB. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction "MOV A, [m]", where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. I/O Control Register List • HT68F002/HT68F0025 Rev. 1.41 Bit Register Name 7 6 5 4 3 2 1 0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PASR — PAS6 — PAS4 — PAS2 — PAS0 IFS0 — — — — INTPS1 INTPS0 STCK0PS STP0IPS 50 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM • HT68F003 Bit Register Name 7 6 5 4 3 2 1 0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PB — — D5 D4 D3 D2 D1 D0 PBC — — D5 D4 D3 D2 D1 D0 PBPU — — D5 D4 D3 D2 D1 D0 PASR PAS7 PAS6 PAS5 — — — — — PBSR — — PBS5 PBS4 PBS3 PBS2 PBS1 — — INTPS1 INTPS0 IFS0 PTCK1PS1 PTCK1PS0 STCK0PS STP0IPS PTP1IPS Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using register PAPU~PBPU, and are implemented using weak PMOS transistors. PAPU Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0 I/O Port A bit7~ bit 0 Pull-High Control 0: Disable 1: Enable PBPU Register – HT68F003 only Rev. 1.41 Bit 7 6 5 4 3 2 1 0 Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5~0 I/O Port B bit5~ bit 0 Pull-High Control 0: Disable 1: Enable 51 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. PAWU Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0 I/O Port A bit 7 ~ bit 0 Wake Up Control 0: Disable 1: Enable I/O Port Control Registers Each I/O port has its own control register known as PAC~PBC, to control the input/output configuration. With these control registers, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a "1". This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a "0", the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. PAC Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7 ~ 0 I/O Port A bit 7 ~ bit 0 Input/Output Control 0: Output 1: Input PBC Register – HT68F003 only Rev. 1.41 Bit 7 6 5 4 3 2 1 0 Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 1 1 1 1 1 1 Bit 7 ~ 6 Unimplemented, read as "0" Bit 5 ~ 0 I/O Port B bit 5 ~ bit 0 Input/Output Control 0: Output 1: Input 52 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Pin-Shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. The way in which the pin function of each pin is selected is different for each function and a priority order is established where more than one pin function is selected simultaneously. Additionally there are a PASR and a PBSR register to establish certain pin functions. Generally speaking, the analog function has higher priority than the digital function. However, if more than two analog functions are enabled and the analog signal input comes from the same external pin, the analog input will be internally connected to all of these active analog functional modules. Pin-shared Registers The limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. However by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. • PASR Register – HT68F002/HT68F0025 Bit 7 6 5 4 3 2 1 0 Name — PAS6 — PAS4 — PAS2 — PAS0 R/W — R/W — R/W — R/W — R/W POR — 0 — 0 — 0 — 0 Bit 7 Unimplemented, read as "0" Bit 6 PAS6: Pin-Shared Control Bit 0: PA5/INT 1: STP0B Bit 5 Unimplemented, read as "0" Bit 4 PAS4: Pin-Shared Control Bits 0: PA2/INT 1: STP0 Bit 3 Unimplemented, read as "0" Bit 2 PAS2: Pin-Shared Control Bit 0: PA1 1: STP0B Bit 1 Unimplemented, read as "0" Bit 0 PAS0: Pin-Shared Control Bit 0: PA0/STP0I 1: STP0 Rev. 1.41 53 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM • PASR Register – HT68F003 Bit 7 6 5 4 3 2 1 0 Name PAS7 PAS6 PAS5 — — — — — R/W R/W R/W R/W — — — — — POR 0 0 0 — — — — — Bit 7 PAS7: Pin-Shared Control Bit 0: PA7/PTCK1 1: STP0B Note: PAS7 is valid when RSTC=55H Bit 6 PAS6: Pin-Shared Control Bit 0: PA6/PTCK1/STP0I 1: STP0 Bit 5 PAS5: Pin-Shared Control Bit 0: PA4/INT/PTCK1 1: STP0 Bit 4~0 Unimplemented, read as "0" • PBSR Register – HT68F003 only Bit 7 6 5 4 3 2 1 0 Name — — PBS5 PBS4 PBS3 PBS2 PBS1 — R/W — — R/W R/W R/W R/W R/W — POR — — 0 0 0 0 0 — Bit 7~6 Unimplemented, read as "0" Bit 5 PBS5: Pin-Shared Control Bit 0: PB5 1: PTP1 Rev. 1.41 Bit 4 PBS4: Pin-Shared Control Bit 0: PB4 1: PTP1B Bit 3 PBS3: Pin-Shared Control Bit 0: PB3 1: PTP1 Bit 2 PBS2: Pin-Shared Control Bit 0: PB2 1: PTP1B Bit 1 PBS1: Pin-Shared Control Bit 0: PB1/PTCK1 1: STP0B Bit 0 Unimplemented, read as "0" 54 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM • IFS0 Register – HT68F002/HT68F0025 Bit 7 6 5 4 3 2 1 0 Name — — STCK0PS STP0IPS — — INTPS1 INTPS0 R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 STCK0PS: STCK0 Pin Remapping Control 0: STCK0 on PA7 (default) 1: STCK0 on PA6 Bit 4 STP0IPS: STP0I Pin Remapping Control 0: STP0I on PA6 (default) 1: STP0I on PA0 Bit 3~2 Unimplemented, read as "0" Bit 1~0 INTPS1, INTPS0: INT Pin Remapping Control 00: INT on PA5 (default) 01: INT on PA2 10: INT on PA3 11: INT on PA7 • IFS0 Register – HT68F003 Bit 7 6 Name PTCK1PS1 PTCK1PS0 R/W R/W R/W R/W R/W POR 0 0 0 0 Bit 7~6 5 4 3 2 1 0 — INTPS1 INTPS0 R/W — R/W R/W 0 — 0 0 STCK0PS STP0IPS PTP1IPS PTCK1PS1, PTCK1PS0: PTCK1 Pin Remapping Control 00: PTCK1 on PA4 (default) 01: PTCK1 on PA6 10: PTCK1 on PA7 11: PTCK1 on PB1 Bit 5 STCK0PS: STCK0 Pin Remapping Control 0: STCK0 on PA3 (default) 1: STCK0 on PA2 Bit 4 STP0IPS: STP0I Pin Remapping Control 0: STP0I on PA6 (default) 1: STP0I on PA0 Bit 3 PTP1IPS: PTP1I Pin Remapping Control 0: PTP1I on PA5 (default) 1: PTP1I on PB0 Rev. 1.41 Bit 2 Unimplemented, read as "0" Bit 1~0 INTPS1, INTPS0: INT Pin Remapping Control 00: INT on PA3 (default) 01: INT on PA2 10: INT on PA4 11: INT on PA5 55 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown.    
                   
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                                                Generic Input/Output Structure Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control register is then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data register is first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "SET [m].i" and "CLR [m].i" instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Rev. 1.41 56 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions the devices include several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Standard and Periodic TM sections. Introduction The devices contain one or two TMs depending upon which device is selected with each TM having a reference name of TM0~TM1. Each individual TM can be categorised as a certain type, namely Standard Type TM or Periodic Type TM. Although similar in nature, the different TM types vary in their feature complexity. The common features to the Standard and Periodic TMs will be described in this section and the detailed operation will be described in corresponding sections. The main features and differences between the two types of TMs are summarised in the accompanying table. STM PTM Timer/Counter Function √ √ I/P Capture √ √ Compare Match Output √ √ PWM Channels 1 1 Single Pulse Output PWM Alignment PWM Adjustment Period & Duty 1 1 Edge Edge Duty or Period Duty or Period TM Function Summary Device TM0 HT68F002/HT68F0025 10-bit STM TM1 — HT68F003 10-bit STM 10-bit PTM TM Name/Type Reference TM Operation The two different types of TMs offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. When the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the xTnCK2~xTnCK0 bits in the xTM control registers. The clock source can be a ratio of either the system clock fSYS or the internal high clock fH, the fL clock source or the external xTCKn pin. The xTCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting. Rev. 1.41 57 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM TM Interrupts The Standard and Periodic type TMs each has two internal interrupts, the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated, it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has two TM input pins, with the label xTCKn and xTPnI. The TM input pin xTCKn, is essentially a clock source for the TM and is selected using the xTnCK2~xTnCK0 bits in the xTMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. This external TM input pin is shared with other functions but will be connected to the internal TM if selected using the xTnCK2~xTnCK0 bits. The TM input pin can be chosen to have either a rising or falling active edge. The other TM input pin, xTPnI, is the capture input whose active edge can be a rising edge, a falling edge or both rising and falling edges and the active edge transition type is selected using the xTnIO1 and xTnIO0 bits in the xTMnC1 register. The TMs each have two output pins with the label xTPn and xTPnB. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external xTPn output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other function, the TM output function must first be setup using registers. A single bit in one of the registers determines if its associated pin is to be used as an external TM output pin or if it is to have another function. The number of output pins for each TM type is different, the details are provided in the accompanying table. Device STM PTM HT68F002/HT68F0025 STCK0, STP0I STP0, STP0B — HT68F003 STCK0, STP0I STP0, STP0B PTCK1, PTP1I PTP1, PTP1B TM Input/Output Pins TM Input/Output Pin Control Selecting to have a TM input/output or whether to retain its other shared function is implemented using one register, with a single bit in each register corresponding to a TM input/output pin. Configuring the selection bits correctly will setup the corresponding pin as a TM input/output. The details of the pin-shared function selection are described in the pin-shared function section. STM Inverting Output STP0B Output STP0 Capture Input STP0I TCK Input STCK0 STM Function Pin Control Block Diagram Rev. 1.41 58 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Inverting Output PTP1B PTM Output PTP1 Capture Input PTP1I TCK Input PTCK1 PTM Function Pin Control Block Diagram Programming Considerations The TM Counter Registers and the Capture/Compare CCRA register, and CCRP register pair for Periodic Timer Module, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA register and CCRP registers are implemented in the way shown in the following diagram and accessing the register is carried out CCRP low byte register using the following access procedures. Accessing the CCRA or CCRP low byte register without following these access procedures will result in unpredictable values. STM Counter Register (Read only) STM0DL PTM Counter Register (Read only) PTM1DL STM0DH 8-bit Buffer 8-bit Buffer STM0AL PTM1DH PTM1AL STM0AH STM CCRA Register (Read/Write) PTM1AH PTM CCRA Register (Read/Write) Data Bus PTM1RPL PTM1RPH PTM CCRP Register (Read/Write) Data Bus The following steps show the read and write procedures: • Writing Data to CCRA or PTM CCRP ♦♦ Step 1. Write data to Low Byte STM0AL or PTM1RPL ––note that here data is only written to the 8-bit buffer. ♦♦ Step 2. Write data to High Byte STM0AH or PTM1RPH ––here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. • Reading Data from the Counter Registers and CCRA or PTM CCRP Rev. 1.41 ♦♦ Step 1. Read data from the High Byte STM0DH, STM0AH or PTM1RPH ––here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ♦♦ Step 2. Read data from the Low Byte STM0DL, STM0AL or PTM1RPL ––this step reads data from the 8-bit buffer. 59 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Standard Type TM – STM The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can be controlled with two external input pins and can drive two external output pins. Device TM Type TM Name TM Input Pin TM Output Pin HT68F002 HT68F0025 HT68F003 10-bit STM STM STCK0, STP0I STP0, STP0B                  … †  … ‡ˆ †  …‰ ‡
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ƒ           ­ €  ‚           Standard Type TM Block Diagram Standard TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is 3-bit wide whose value is compared with the highest 3 bits in the counter while the CCRA is the 10 bits and therefore compares with all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the ST0ON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Standard Type TM can operate in a number of different operational modes, can be driven by different clock sources and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Rev. 1.41 60 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Standard Type TM Register Description Overall operation of the Standard TM is controlled using series of registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as three CCRP bits. Bit Register Name 7 6 5 4 3 2 1 0 STM0C0 ST0PAU ST0CK2 ST0CK1 ST0CK0 ST0ON ST0RP2 ST0RP1 ST0RP0 STM0C1 ST0M1 ST0M0 ST0IO1 ST0IO0 ST0OC ST0POL ST0DPX ST0CCLR STM0DL D7 D6 D5 D4 D3 D2 D1 D0 STM0DH — — — — — — D9 D8 STM0AL D7 D6 D5 D4 D3 D2 D1 D0 STM0AH — — — — — — D9 D8 10-bit Standard TM Register List STM0C0 Register Bit 7 6 5 4 3 2 1 0 Name ST0PAU ST0CK2 ST0CK1 ST0CK0 ST0ON ST0RP2 ST0RP1 ST0RP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 ST0PAU: STM Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the STM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 ST0CK2~ST0CK0: Select STM Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: fTBC 110: STCK0 rising edge clock 111: STCK0 falling edge clock These three bits are used to select the clock source for the STM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. bit 3 ST0ON: STM Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the STM. Setting the bit high enables the counter to run, clearing the bit disables the STM. Clearing this bit to zero will stop the counter from counting and turn off the STM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the STM is in the Compare Match Output Mode or the PWM output Mode or Single Pulse Output Mode then the STM output pin will be reset to its initial condition, as specified by the ST0OC bit, when the ST0ON bit changes from low to high. bit 7 Rev. 1.41 61 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM bit 2~0 ST0RP2~ ST0RP0: STM CCRP 3-bit register, compared with the STM Counter bit 9~bit 7 Comparator P Match Period 000: 1024 STM0 clocks 001: 128 STM0 clocks 010: 256 STM0 clocks 011: 384 STM0 clocks 100: 512 STM0 clocks 101: 640 STM0 clocks 110: 768 STM0 clocks 111: 896 STM0 clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the ST0CCLR bit is set to zero. Setting the ST0CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. STM0C1 Register Rev. 1.41 Bit 7 6 5 4 3 2 1 0 Name ST0M1 ST0M0 ST0IO1 ST0IO0 ST0OC R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 ST0POL ST0DPX ST0CCLR bit 7~6 ST0M1~ ST0M0: Select STM0 Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM output Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the STM. To ensure reliable operation the STM should be switched off before any changes are made to the ST0M1 and ST0M0 bits. In the Timer/Counter Mode, the STM output pin state is undefined. bit 5~4 ST0IO1~ ST0IO0: Select STM0 function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM output Mode/Single Pulse Output Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of STP0I 01: Input capture at falling edge of STP0I 10: Input capture at falling/rising edge of STP0I 11: Input capture disabled Timer/counter Mode: Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. 62 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM In the Compare Match Output Mode, the ST0IO1~ST0IO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the ST0IO1~ST0IO0 bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the ST0OC bit. Note that the output level requested by the ST0IO1~ST0IO0 bits must be different from the initial value setup using the ST0OC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the ST0ON bit from low to high. In the PWM Mode, the ST0IO1 and ST0IO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the ST0IO1 and ST0IO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the ST0IO1 and ST0IO0 bits are changed when the TM is running. Rev. 1.41 bit 3 ST0OC: STM0 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM output Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the STM output pin. Its operation depends upon whether STM is being used in the Compare Match Output Mode or in the PWM output Mode/ Single Pulse Output Mode. It has no effect if the STM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the STM output pin before a compare match occurs. In the PWM output Mode it determines if the PWM signal is active high or active low. In the Single Pulse Output Mode it determines the logic level of the STM output pin when the ST0ON bit changes from low to high. bit 2 ST0POL: STM0 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the STM0 output pin. When the bit is set high the STM output pin will be inverted and not inverted when the bit is zero. It has no effect if the STM is in the Timer/Counter Mode. bit 1 ST0DPX: STM0 PWM period/duty Control 0: CCRP – period; CCRA – duty 1: CCRP – duty; CCRA – period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. bit 0 ST0CCLR: Select STM0 Counter clear condition 0: STM0 Comparator P match 1: STM0 Comparator A match This bit is used to select the method which clears the counter. Remember that the Standard STM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the ST0CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The ST0CCLR bit is not used in the PWM output mode, Single Pulse or Input Capture Mode. 63 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM STM0DL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0 STM0 Counter Low Byte Register bit 7 ~ bit 0 STM0 10-bit Counter bit 7 ~ bit 0 STM0DH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 2 1 0 bit 7~2 Unimplemented, read as "0" bit 1~0 STM0 Counter High Byte Register bit 1 ~ bit 0 STM0 10-bit Counter bit 9 ~ bit 8 STM0AL Register Bit 7 6 5 4 3 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 bit 7~0 STM0 CCRA Low Byte Register bit 7 ~ bit 0 STM0 10-bit Counter bit 7 ~ bit 0 STM0AH Register Rev. 1.41 Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 bit 7~2 Unimplemented, read as "0" bit 1~0 STM0 CCRA High Byte Register bit 1 ~ bit 0 STM0 10-bit Counter bit 9 ~ bit 8 64 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Standard Type TM Operating Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the ST0M1 and ST0M0 bits in the STM0C1 register. Compare Output Mode To select this mode, bits ST0M1 and ST0M0 in the STM0C1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the ST0CCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both STMA0F and STMP0F interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the ST0CCLR bit in the STM0C1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the STMA0F interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when ST0CCLR is high no STMP0F interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to "0". If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the STMA0F interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the STM output pin, will change state. The STM output pin condition however only changes state when an STMA0F interrupt request flag is generated after a compare match occurs from Comparator A. The STMP0F interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the STM output pin. The way in which the STM output pin changes state are determined by the condition of the ST0IO1 and ST0IO0 bits in the STM0C1 register. The STM output pin can be selected using the ST0IO1 and ST0IO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the STM output pin, which is setup after the ST0ON bit changes from low to high, is setup using the ST0OC bit. Note that if the ST0IO1 and ST0IO0 bits are zero then no pin change will take place. Rev. 1.41 65 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Counter Value 0x3FF ST0CCLR = 0; ST0M[1:0] = 00 Counter overflow CCRP > 0 Counter cleared by CCRP value CCRP = 0 Counter Reset Resume CCRP > 0 CCRP Pause CCRA Stop Time ST0ON ST0PAU ST0POL CCRP Int. Flag STMP0F CCRA Int. Flag STMA0F STM O/P Pin Output Pin set to Initial Level Low if ST0OC= 0 Output Toggle with STMA0F flag Now ST0IO[1:0] = 10 Active High Output Select Output not affected by STMA0F flag. Remains High until reset by ST0ON bit Output inverts when ST0POL is high Output Pin Reset to initial value Output controlled by other pin - shared function Here ST0IO[1:0] = 11 Toggle Output Select Compare Match Output Mode – ST0CCLR = 0 Note: 1. With ST0CCLR = 0 a Comparator P match will clear the counter 2. The TM output pin controlled only by the STMA0F flag 3. The output pin reset to initial state by a ST0ON bit rising edge Rev. 1.41 66 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM ST0CCLR = 1; ST0M[1:0] = 00 Counter Value CCRA > 0 Counter cleared by CCRA value 0x3FF Resume CCRA Pause CCRP CCRA = 0 Counter overflow CCRA = 0 Stop Counter Reset Time ST0ON ST0PAU ST0POL No STMA0F flag generated on CCRA overflow CCRP Int. Flag STMA0F CCRA Int. Flag STMP0F STM O/P Pin Output does not change STMP0F not generated Output not affected by Output Pin set to Initial Level Low if ST0OC= 0 Output Toggle with STMA0F flag STMA0F flag. Remains High Now ST0IO[1:0] = 10 Active High Output Select until reset by ST0ON bit Here ST0IO[1:0] = 11 Toggle Output Select Output inverts when ST0POL is high Output Pin Reset to initial value Output controlled by other pin- shared function Compare Match Output Mode – ST0CCLR = 1 Note: 1. With ST0CCLR = 1 a Comparator A match will clear the counter 2. The TM output pin controlled only by the STMA0F flag 3. The output pin reset to initial state by a ST0ON rising edge 4. The STMP0F flag is not generated when ST0CCLR = 1 Rev. 1.41 67 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Timer/Counter Mode To select this mode, bits ST0M1 and ST0M0 in the STM0C1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the STM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the STM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function by setting pinshre function register. PWM Output Mode To select this mode, bits ST0M1 and ST0M0 in the STM0C1 register should be set to 10 respectively and also the ST0IO1 and ST0IO0 bits should be set to 10 respectively. The PWM function within the STM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the STM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM output mode, the ST0CCLR bit has no effect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the ST0DPX bit in the STM0C1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The ST0OC bit in the STM0C1 register is used to select the required polarity of the PWM waveform while the two ST0IO1 and ST0IO0 bits are used to enable the PWM output or to force the STM output pin to a fixed high or low level. The ST0POL bit is used to reverse the polarity of the PWM output waveform. • 10-bit STM, PWM Mode, Edge-aligned Mode, ST0DPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 Duty CCRA If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 100b and CCRA =128, The STM PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125 kHz, duty = 128/512 = 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. • 10-bit STM, PWM Mode, Edge-aligned Mode, ST0DPX=1 CCRP 001b 010b 011b 100b Period Duty 101b 110b 111b 000b 768 896 1024 CCRA 128 256 384 512 640 The PWM output period is determined by the CCRA register value together with the STM clock while the PWM duty cycle is defined by the CCRP register value. Rev. 1.41 68 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Counter Value ST0DPX=0;ST0M[1:0]=10 Counter Clearedby CCRP Counter reset when ST0ON returns high CCRP Pause Resume CCRA Counter Stop If ST0ON bit low Time ST0ON ST0PAU ST0POL CCRA Int. Flag STMA0F CCRP Int. Flag STMP0F STM O/P Pin (ST0OC=1) STM O/P Pin (ST0OC=0) PWM Duty Cycle set by CCRA Output controlled by Other pin-shared function PWM resumes operation Output Inverts When ST0POL = 1 PWM Period set by CCRP PWM Output Mode – ST0DPX = 0 Note: 1. Here ST0DPX = 0 – Counter cleared by CCRP 2. A counter clear sets PWM Period 3. The internal PWM function continues running even when ST0IO[1:0] = 00 or 01 4. The ST0CCLR bit has no influence on PWM operation Rev. 1.41 69 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Counter Value ST0DPX=1;ST0M[1:0]=10 Counter Cleared by CCRA Counter reset when ST0ON returns high CCRA Pause Resume CCRP Counter Stop If ST0ON bit low Time ST0ON ST0PAU ST0POL CCRP Int. Flag STMP0F CCRA Int. Flag STMA0F STM O/P Pin (ST0OC=1) STM O/P Pin (ST0OC=0) PWM Duty Cycle set by CCRP Output controlled by Other pin-shared function PWM resumes operation Output Inverts When ST0POL = 1 PWM Period set by CCRA PWM Output Mode – ST0DPX = 1 Note: 1. Here ST0DPX = 1 – Counter cleared by CCRA 2. A counter clear sets PWM Period 3. The internal PWM function continues even when ST0IO[1:0] = 00 or 01 4. The ST0CCLR bit has no influence on PWM operation Rev. 1.41 70 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Single Pulse Mode To select this mode, bits ST0M1 and ST0M0 in the STM0C1 register should be set to 10 respectively and also the ST0IO1 and ST0IO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the STM output pin. The trigger for the pulse output leading edge is a low to high transition of the ST0ON bit, which can be implemented using the application program. However in the Single Pulse Mode, the ST0ON bit can also be made to automatically change from low to high using the external STCK0 pin, which will in turn initiate the Single Pulse output. When the ST0ON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The ST0ON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the ST0ON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. Leading Edge Trailing Edge ST0ON bit 0→1 ST0ON bit 1→0 S/W Command SET“ST0ON” or STCK0 Pin Transition S/W Command CLR“ST0ON” or CCRA Compare Match STP0/STP0B Output Pin Pulse Width = CCRA Value Single Pulse Generation Rev. 1.41 71 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Counter Value ST0M [1:0] = 10 ; ST0IO [1:0] = 11 Counter stopped by CCRA Counter Reset when ST0ON returns high CCRA Pause Counter Stops by software Resume CCRP Time ST0ON Software Trigger Auto. set by STCK0 pin Cleared by CCRA match STCK0 pin Software Trigger Software Trigger Software Software Trigger Clear STCK0 pin Trigger ST0PAU ST0POL No CCRP Interrupts generated CCRP Int. Flag STMP0F CCRA Int. Flag STMA0F STM O/P Pin (ST0OC=1) STM O/P Pin (ST0OC=0) Output Inverts when ST0POL = 1 Pulse Width set by CCRA Single Pulse Mode Note: 1. Counter stopped by CCRA match 2. CCRP is not used 3. The pulse is triggered by setting the ST0ON bit high 4. In the Single Pulse Mode, ST0IO [1:0] must be set to "11" and can not be changed. Rev. 1.41 72 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM However a compare match from Comparator A will also automatically clear the ST0ON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a STM interrupt. The counter can only be reset back to zero when the ST0ON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The ST0CCLR and ST0DPX bits are not used in this Mode. Capture Input Mode To select this mode bits ST0M1 and ST0M0 in the STM0C1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the STP0I, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the ST0IO1 and ST0IO0 bits in the STM0C1 register. The counter is started when the ST0ON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the STP0I the present value in the counter will be latched into the CCRA registers and a STM interrupt generated. Irrespective of what events occur on the STP0I the counter will continue to free run until the ST0ON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a STM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The ST0IO1 and ST0IO0 bits can select the active trigger edge on the STP0I to be a rising edge, falling edge or both edge types. If the ST0IO1 and ST0IO0 bits are both set high, then no capture operation will take place irrespective of what happens on the STP0I, however it must be noted that the counter will continue to run. The ST0CCLR and ST0DPX bits are not used in this Mode. Rev. 1.41 73 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Counter Value STnM [1:0] = 01 Counter cleared by CCRP Counter Stop Counter Reset CCRP Resume YY Pause XX Time STnON STnPAU Active edge Active edge Active edge STMn capture pin STPnI CCRA Int. Flag STMnAF CCRP Int. Flag STMnPF CCRA Value STnIO [1:0] Value XX 00 – Rising edge YY 01 – Falling edge XX 10 – Both edges YY 11 – Disable Capture Capture Input Mode (n=0) Note: 1. ST0M[1:0] = 01 and active edge set by the ST0IO[1:0] bits 2. A TM Capture input pin active edge transfers the counter value to CCRA 3. The ST0CCLR and ST0DPX bits are not used 4. No output function – ST0OC and ST0POL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.41 74 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Periodic Type TM – PTM The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can also be controlled with two external input pins and can drive two external output pins. Device Name TM Input Pin TM Output Pin HT68F003 10-bit PTM PTCK1, PTP1I PTP1,PTP1B Periodic TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with the CCRA and CCRP registers. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the PT0ON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Periodic Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control the output pin. All operating setup conditions are selected using relevant internal registers.                   ‚ƒ „ ƒ ‚ƒ …† „ ƒ ‚‡ … ˆ ‚‡ …ˆ † ‚ ‰  ‚ ‰                                                  
                                                                         
  
                 
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         ƒ Periodic Type TM Block Diagram Rev. 1.41 75 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Periodic Type TM Register Description Overall operation of the Periodic TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA and CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Bit Register Name 5 4 3 2 1 0 PTM1C0 PT1PAU PT1CK2 7 6 PT1CK1 PT1CK0 PT1ON — — — PTM1C1 PT1M1 PT1M0 PT1IO1 PT1IO0 PT1OC PT1POL PT1CKS PT1CCLR PTM1DL D7 D6 D5 D4 D3 D2 D1 D0 PTM1DH — — — — — — D9 D8 PTM1AL D7 D6 D5 D4 D3 D2 D1 D0 PTM1AH — — — — — — D9 D8 PTM1RPL D7 D6 D5 D4 D3 D2 D1 D0 PTM1RPH — — — — — — D9 D8 10-bit Periodic TM Register List PTM1C0 Register Bit 7 6 5 4 3 2 1 0 Name PT1PAU PT1CK2 PT1CK1 PT1CK0 PT1ON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7 PT1PAU: PTM Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 Rev. 1.41 PT1CK2~PT1CK0: Select PTM Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: fTBC 110: PTCK1 rising edge clock 111: PTCK1 falling edge clock These three bits are used to select the clock source for the TM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fTBC is another internal clock, the details of which can be found in the oscillator section. 76 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Bit 3 PT1ON: PTM Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the TM Output control bit, when the bit changes from low to high. Bit 2~0 Unimplemented, read as "0" PTM1C1 Register Bit 7 6 5 4 3 2 1 0 Name PT1M1 PT1M0 PT1IO1 PT1IO0 PT1OC PT1POL PT1CKS PT1CCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PT1M1~ PT1M0: Select PTM Operation Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the PT1M1 and PT1M0 bits. In the Timer/Counter Mode, the PTM output pin state is undefined. Bit 5~4 PT1IO1~ PT1IO0: Select PTM output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of PTP1I or PTCK1 01: Input capture at falling edge of PTP1I or PTCK1 10: Input capture at falling/rising edge of PTP1I or PTCK1 11: Input capture disabled Timer/counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. Rev. 1.41 77 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM In the Compare Match Output Mode, the PT1IO1 and PT1IO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When these bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the PT1OC bit. Note that the output level requested by the PT1IO1 and PT1IO0 bits must be different from the initial value setup using the PT1OC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state, it can be reset to its initial level by changing the level of the PT1ON bit from low to high. In the PWM Mode, the PT1IO1 and PT1IO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the PT1IO1 and PT1IO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the PT1IO1 and PT1IO0 bits are changed when the TM is running. Bit 3 PT1OC: PTP1/PTP1B Output control bit Compare Match Output Mode 0: initial low 1: initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 PT1POL: PTP1 Output polarity Control 0: non-invert 1: invert This bit controls the polarity of the PTP1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1 PT1CKS: PTM capture trigger source select 0: From PTP1I 1: From PTCK1 pin Bit 0 PT1CCLR: Select PTM Counter clear condition 0: PTM Comparatror P match 1: PTM Comparatror A match This bit is used to select the method which clears the counter. Remember that the Periodic TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the PT1CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The PT1CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode. Rev. 1.41 78 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM PTM1DL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 PTM1DL: PTM Counter Low Byte Register bit 7 ~ bit 0 PTM 10-bit Counter bit 7 ~ bit 0 PTM1DH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 PTM1DH: PTM Counter High Byte Register bit 1 ~ bit 0 PTM 10-bit Counter bit 9 ~ bit 8 PTM1AL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 PTM1AL: PTM CCRA Low Byte Register bit 7 ~ bit 0 PTM 10-bit CCRA bit 7 ~ bit 0 PTM1AH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 2 1 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 PTM1AH: PTM CCRA High Byte Register bit 1 ~ bit 0 PTM 10-bit CCRA bit 9 ~ bit 8 PTM1RPL Register Bit 7 6 5 4 3 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 PTM1RPL: PTM CCRP Low Byte Register bit 7 ~ bit 0 PTM 10-bit CCRP bit 7 ~ bit 0 Rev. 1.41 79 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM PTM1RPH Register Bit 7 6 5 4 3 2 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 1 0 Unimplemented, read as "0" Bit 1~0 PTM1RPH: PTM CCRP High Byte Register bit 1 ~ bit 0 PTM 10-bit CCRP bit 9 ~ bit 8 Periodic Type TM Operating Modes The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the PT1M1 and PT1M0 bits in the PTM1C1 register. Compare Match Output Mode To select this mode, bits PT1M1 and PT1M0 in the PTM1C1 register, should be all cleared to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the PT1CCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both the PTMA1F and PTMP1F interrupt request flags for Comparator Aand Comparator P respectively, will both be generated. If the PT1CCLR bit in the PTM1C1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the PTMA1F interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when PT1CCLR is high no PTMP1F interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to "0". If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the PTMA1F interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when a PTMA1F interrupt request flag is generated after a compare match occurs from Comparator A. The PTMP1F interrupt request flag, generated from a compare match from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the PT1IO1 and PT1IO0 bits in the PTM1C1 register. The TM output pin can be selected using the PT1IO1 and PT1IO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the PT1ON bit changes from low to high, is setup using the PT1OC bit. Note that if the PT1IO1, PT1IO0 bits are zero then no pin change will take place. Rev. 1.41 80 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Counter Value Counter overflow CCRP=0 0x3FF PT1CCLR = 0; PT1M [1:0] = 00 CCRP > 0 Counter cleared by CCRP value CCRP > 0 Counter Restart Resume CCRP Pause CCRA Stop Time PT1ON PT1PAU PT1POL CCRP Int. Flag PTMP1F CCRA Int. Flag PTMA1F PTM O/P Pin Output pin set to initial Level Low if PT1OC=0 Output not affected by PTMA1F flag. Remains High until reset by PT1ON bit Output Toggle with PTMA1F flag Here PT1IO [1:0] = 11 Toggle Output select Note PT1IO [1:0] = 10 Active High Output select Output Inverts when PT1POL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – PT1CCLR = 0 Note: 1. With PT1CCLR = 0 – a Comparator P match will clear the counter 2. The TM output pin is controlled only by the PTMA1F flag 3. The output pin is reset to initial state by a PT1ON bit rising edge Rev. 1.41 81 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Counter Value PT1CCLR = 1; PT1M [1:0] = 00 CCRA = 0 Counter overflow CCRA > 0 Counter cleared by CCRA value 0x3FF CCRA=0 Resume CCRA Pause Stop Counter Restart CCRP Time PT1ON PT1PAU PT1POL No PTMA1F flag generated on CCRA overflow CCRA Int. Flag PTMA1F CCRP Int. Flag PTMP1F PTM O/P Pin PTMP1F not generated Output pin set to initial Level Low if PT1OC=0 Output does not change Output Toggle with PTMA1F flag Here PT1IO [1:0] = 11 Toggle Output select Output not affected by PTMA1F flag. Remains High until reset by PT1ON bit Note PT1IO [1:0] = 10 Active High Output select Output Inverts when PT1POL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – PT1CCLR = 1 Note: 1. With PT1CCLR = 1 – a Comparator A match will clear the counter 2. The TM output pin is controlled only by the PTMA1F flag 3. The output pin is reset to initial state by a PT1ON rising edge 4. The PTMP1F flag is not generated when PT1CCLR = 1 Rev. 1.41 82 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Timer/Counter Mode To select this mode, bits PT1M1 and PT1M0 in the PTM1C1 register should all be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits PT1M1 and PT1M0 in the PTM1C1 register should be set to 10 respectively and also the PT1IO1 and PT1IO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM output mode, the PT1CCLR bit has no effect as the PWM period. Both of the CCRP and CCRA registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The PT1OC bit in the PTM1C1 register is used to select the required polarity of the PWM waveform while the two PT1IO1 and PT1IO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The PT1POL bit is used to reverse the polarity of the PWM output waveform. • 10-bit PWM Mode, Edge-aligned Mode CCRP Period Duty CCRP = 0~1024 CCRP=0 : period= 1024 clocks CCRP=1~1023: period=1~1023 clocks CCRA If fSYS = 16MHz, PTM clock source select fSYS/4, CCRP = 512 and CCRA = 128, The PTM PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125kHz, duty = 128/512 = 25% If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. Rev. 1.41 83 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Counter Value PT1DPX = 0; PT1M [1:0] = 10 Counter cleared by CCRP Counter Reset when PT1ON returns high CCRP Pause Resume CCRA Counter Stop if PT1ON bit low Time PT1ON PT1PAU PT1POL CCRA Int. Flag PTMA1F CCRP Int. Flag PTMP1F PTM O/P Pin (PT1OC=1) PTM O/P Pin (PT1OC=0) PWM Duty Cycle set by CCRA PWM Period set by CCRP PWM resumes operation Output controlled by Output Inverts other pin-shared function When PT1POL = 1 PWM Output Mode Note: 1. Here Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when PT1IO[1:0] = 00 or 01 4. The PT1CCLR bit has no influence on PWM operation Rev. 1.41 84 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Single Pulse Output Mode To select this mode, the required bit pairs, PT1M1 and PT1M0 should be set to 10 respectively and also the corresponding PT1IO1 and PT1IO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse output leading edge is a low to high transition of the PT1ON bit, which can be implemented using the application program. However in the Single Pulse Mode, the PT1ON bit can also be made to automatically change from low to high using the external PTCK1 pin, which will in turn initiate the Single Pulse output. When the PT1ON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The PT1ON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the PT1ON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the PT1ON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate TM interrupts. The counter can only be reset back to zero when the PT1ON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The PT1CCLR bit is also not used. Leading Edge Trailing Edge PT1ON bit 0→1 PT1ON bit 1→0 S/W Command SET“PT1ON” or PTCK1 Pin Transition S/W Command CLR“PT1ON” or CCRA Compare Match PTP1/PTP1B Output Pin Pulse Width = CCRA Value Single Pulse Generation Rev. 1.41 85 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Counter Value PT1M [1:0] = 10 ; PT1IO [1:0] = 11 Counter stopped by CCRA Counter Reset when PT1ON returns high CCRA Pause Counter Stops by software Resume CCRP Time PT1ON Software Trigger Auto. set by PTCK1 pin Cleared by CCRA match PTCK1 pin Software Trigger Software Trigger Software Software Trigger Clear PTCK1 pin Trigger PT1PAU PT1POL No CCRP Interrupts generated CCRP Int. Flag PTMP1F CCRA Int. Flag PTMA1F PTM O/P Pin (PT1OC=1) PTM O/P Pin (PT1OC=0) Output Inverts when PT1POL = 1 Pulse Width set by CCRA Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse is triggered by the PTCK1 pin or by setting the PT1ON bit high 4. A PTCK1 pin active edge will automatically set the PT1ON bit high 5. In the Single Pulse Mode, PT1IO [1:0] must be set to "11" and can not be changed. Rev. 1.41 86 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Capture Input Mode To select this mode bits PT1M1 and PT1M0 in the PTM1C1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the PTP1I or PTCK1 pin, selected by the PT1CKS bit in the PTM1C1 register. The input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the PT1IO1 and PT1IO0 bits in the PTM1C1 register. The counter is started when the PT1ON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the PTP1I or PTCK1 pin the present value in the counter will be latched into the CCRA register and a TM interrupt generated. Irrespective of what events occur on the PTP1I or PTCK1 pin the counter will continue to free run until the PT1ON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The PT1IO1 and PT1IO0 bits can select the active trigger edge on the PTP1I or PTCK1 pin to be a rising edge, falling edge or both edge types. If the PT1IO1 and PT1IO0 bits are both set high, then no capture operation will take place irrespective of what happens on the PTP1I or PTCK1 pin, however it must be noted that the counter will continue to run. As the PTP1I or PTCK1 pin is pin shared with other functions, care must be taken if the PTM is in the Capture Input Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The PT1CCLR, PT1OC and PT1POL bits are not used in this Mode. Rev. 1.41 87 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Counter Value PTnM[1:0] = 01 Counter cleared by CCRP Counter Stop Counter Reset CCRP Resume YY Pause XX Time PTnON PTnPAU Active edge Active edge Active edge PTMn Capture Pin PTPnI or PTCKn CCRA Int. Flag PTMnAF CCRP Int. Flag PTMnPF CCRA Value PTnIO [1:0] Value XX 00 - Rising edge YY 01 - Falling edge XX 10 - Both edges YY 11 - Disable Capture Capture Input Mode (n=1) Note: 1. PT1M[1:0] = 01 and active edge set by the PT1IO[1:0] bits 2. A TM Capture input pin active edge transfers counter value to CCRA 3. The PT1CCLR bit is not used 4. No output function – PT1OC and PT1POL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero Rev. 1.41 88 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The devices contain an external interrupt and internal interrupts functions. The external interrupt is generated by the action of the external INT pin, while the internal interrupts are generated by various internal functions such as the TMs, Time Base and EEPROM. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The number of registers depends upon the device chosen but fall into three categories. The first is the INTC0~INTC1 registers which setup the primary interrupts, the second is the MFI0~MFI1 registers which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external interrupt trigger edge type. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "E" for enable/disable bit or "F" for request flag. Function Enable Bit Request Flag Global EMI — — INT Pin INTE INTF — Multi-function MFnE MFnF n=0 or 1 Time Base TBnE TBnF n=0 or 1 — EEPROM TM DEE DEF STMA0E STMA0F STMP0E STMP0F PTMA1E PTMA1F PTMP1E PTMP1F Notes — Interrupt Register Bit Naming Conventions Interrupt Register Contents • HT68F002/HT68F0025 Register Name Bit 7 6 5 4 3 2 1 0 INT0S0 INTEG — — — — — — INT0S1 INTC0 — TB1F TB0F INTF TB1E TB0E INTE EMI INTC1 — — DEF MF0F — — DEE MF0E MFI0 — — — — Register Name 7 6 5 4 3 2 1 0 INTEG — — — — — — INT0S1 INT0S0 INTC0 — TB1F TB0F INTF TB1E TB0E INTE EMI INTC1 MF1F — DEF MF0F MF1E — DEE MF0E STMA0F STMP0F STMA0E STMP0E • HT68F003 Rev. 1.41 Bit MFI0 — — STMA0F STMP0F — — STMA0E STMP0E MFI1 — — PTMA1F PTMP1F — — PTMA1E PTMP1E 89 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM INTEG Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — INT0S1 INT0S0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 0 Bit 7 ~ 2 Unimplemented, read as "0" Bit 1 ~ 0 INT0S1, INT0S0: Defines INT interrupt active edge 00: Disable Interrupt 01: Rising Edge Interrupt 10: Falling Edge Interrupt 11: Dual Edge Interrupt INTC0 Register Bit 7 6 5 4 3 2 1 Name — TB1F TB0F INTF TB1E TB0E INTE EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6 TB1F: Time Base 1 Interrupt Request Flag 0: No request 1: Interrupt request Bit 5 TB0F: Time Base 0 Interrupt Request Flag 0: No request 1: Interrupt request Bit 4 INTF: INT Interrupt Request Flag 0: No request 1: Interrupt request Bit 3 TB1E : Time Base 1 Interrupt Control 0: Disable 1: Enable Bit 2 TB0E: Time Base 0 Interrupt Control 0: Disable 1: Enable Bit 1 INTE: INT Interrupt Control 0: Disable 1: Enable Bit 0 Rev. 1.41 EMI: Global Interrupt Control 0: Disable 1: Enable 90 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM INTC1 Register – HT68F002/HT68F0025 Bit 7 6 5 4 3 2 1 0 Name — — DEF MF0F — — DEE MF0E R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 DEF: Data EEPROM Interrupt Request Flag 0: No request 1: Interrupt request Bit 4 MF0F: Multi-function 0 Interrupt Request Flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1 DEE: Data EEPROM Interrupt Control 0: Disable 1: Enable Bit 0 MF0E: Multi-function 0 Interrupt Control 0: Disable 1: Enable INTC1 Register – HT68F003 Bit 7 6 5 4 3 2 1 0 Name MF1F — DEF MF0F MF1E — DEE MF0E R/W R/W — R/W R/W R/W — R/W R/W POR 0 — 0 0 0 — 0 0 Bit 7 MF1F: Multi-function 1 Interrupt Request Flag 0: No request 1: Interrupt request Bit 6 Unimplemented, read as "0" Bit 5 DEF: Data EEPROM Interrupt Request Flag 0: No request 1: Interrupt request Bit 4 MF0F: Multi-function 0 Interrupt Request Flag 0: No request 1: Interrupt request Bit 3 MF1E: Multi-function 1 Interrupt Control 0: Disable 1: Enable Bit 2 Unimplemented, read as "0" Bit 1 DEE: Data EEPROM Interrupt Control 0: Disable 1: Enable Bit 0 Rev. 1.41 MF0E: Multi-function 0 Interrupt Control 0: Disable 1: Enable 91 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM MFI0 Register Bit 7 6 5 4 3 2 1 0 Name — — STMA0F STMP0F — — STMA0E STMP0E R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7 ~ 6 Unimplemented, read as "0" Bit 5 STMA0F: STM Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4 STMP0F: STM Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3 ~ 2 Unimplemented, read as "0" Bit 1 STMA0E: STM Comparator A match interrupt control 0: Disable 1: Enable Bit 0 STMP0E: STM Comparator P match interrupt control 0: Disable 1: Enable MFI1 Register – HT68F003 only Bit 7 6 5 4 3 2 1 0 Name — — PTMA1F PTMP1F — — PTMA1E PTMP1E R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7 ~ 6 Unimplemented, read as "0" Bit 5 PTMA1F: PTM Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4 PTMP1F: PTM Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3 ~ 2 Unimplemented, read as "0" Bit 1 PTMA1E: PTM Comparator A match interrupt control 0: Disable 1: Enable Bit 0 PTMP1E: PTM Comparator P match interrupt control 0: Disable 1: Enable Rev. 1.41 92 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P or Comparator A match etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a "JMP" which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a "RETI", which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. EMI auto disabled in ISR Legend xxF Request Flag, no auto reset in ISR xxF Request Flag, auto reset in ISR xxE Enable Bits Interrupt Name Request Flags Enable Bits STM P STMP0F STMP0E STM A STMA0F STMA0E PTM P PTMP1F PTMP1E PTM A PTMA1F PTMA1E Interrupt Name INT Pin Request Flags INT0F Enable Bits INT0E Master Enable EMI Vector Time Base 0 TB0F TB0E EMI 08H Time Base 1 TB1F TB1E EMI 0CH M. Funct. 0 MF0F MF0E EMI 10H EEPROM DEF DEE EMI 14H M. Funct. 1 MF1F MF1E EMI 1CH 04H Priority High Low Interrupts contained within Multi-Function Interrupts HT68F003 only Interrupt Structure Rev. 1.41 93 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM External Interrupt The external interrupt is controlled by signal transitions on the pin INT. An external interrupt request will take place when the external interrupt request flag, INTF, is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. To allow the program to branch to the interrupt vector address, the global interrupt enable bit, EMI, and the external interrupt enable bit, INTE, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pin is pin-shared with an I/O pin, it can only be configured as external interrupt pin if its external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flag, INTF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that the pull-high resistor selection on the external interrupt pin will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Multi-function Interrupt Within these devices there are up to two Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM Interrupts. A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags, MF0F~MF1F are set. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related MultiFunction request flag, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts, namely the TM Interrupts, will not be automatically reset and must be manually reset by the application program. Rev. 1.41 94 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Time Base Interrupts The function of the Time Base Interrupts is to provide regular time signal in the form of an internal interrupt. They are controlled by the overflow signals from their respective timer functions. When these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bits, TB0E or TB1E, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to their respective vector locations will take place. When the interrupt is serviced, the respective interrupt request flag, TB0F or TB1F, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their clock sources originate from the internal clock source fTB. This fTB input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges. The clock source that generates fTB, which in turn controls the Time Base interrupt period, can originate from several different sources, as shown in the System Operating Mode section. TBC Register Bit 7 6 5 4 3 2 1 0 Name TBON TBCK TB11 TB10 — TB02 TB01 TB00 R/W R/W R/W R/W R/W — R/W R/W R/W POR 0 0 1 1 — 1 1 1 Bit 7 TBON: TB0 and TB1 Control bit 0: Disable 1: Enable Bit 6 TBCK: Select fTB Clock 0: fTBC 1: fSYS/4 Bit 5 ~ 4 TB11 ~ TB10: Select Time Base 1 Time-out Period 00: 4096/fTB 01: 8192/fTB 10: 16384/fTB 11: 32768/fTB Bit 3 Unimplemented, read as "0" Bit 2 ~ 0 TB02 ~ TB00: Select Time Base 0 Time-out Period 000: 256/fTB 001: 512/fTB 010: 1024/fTB 011: 2048/fTB 100: 4096/fTB 101: 8192/fTB 110: 16384/fTB 111: 32768/fTB                                           
               
              Time Base Interrupt Rev. 1.41 95 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM EEPROM Interrupt An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit, DEE, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective EEPROM Interrupt vector, will take place. When the EEPROM Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, and the EEPROM interrupt request flag, DEF, will also be automatically cleared. TM Interrupts The TMs each has two interrupts. All of the TM interrupts are contained within the Multi-function Interrupts. For each of the TMs there are two interrupt request flags xTMPnF and xTMAnF and two enable bits xTMPnE and xTMAnE. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P or comparator A match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the respective TM Interrupt enable bit, and associated Multi-function interrupt enable bit, MFnF, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant TM Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pin, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Rev. 1.41 96 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MF0F~MF1F, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the "CALL" instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Rev. 1.41 97 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Low Voltage Detector – LVD Each device has a Low Voltage Detector function, also known as LVD. This enables the device to monitor the power supply voltage, VDD, and provides a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be detemined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value. The ENLVD bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Bit 7 6 5 4 3 2 1 0 Name — — LVDO ENLVD — VLVD2 VLVD1 VLVD0 R/W — — R R/W — R/W R/W R/W POR — — 0 0 — 0 0 0 Bit 7 ~ 6 Unimplemented, read as "0" Bit 5 LVDO: LVD detection output. 0: No active. 1: Low voltage detected Bit 4 Rev. 1.41 ENLVD: Low Voltage Detector Control 0: Disable 1: Enable Bit 3 Unimplemented, read as "0" Bit 2~0 VLVD2 ~ VLVD0: Select LVD Voltage 000: 2.0V 001: 2.2V 010: 2.4V 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.0V 98 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V. When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is in SLEEP mode the low voltage detector will be automatically disabled. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions. VDD VLVD ENLVD LVDO tLVDS LVD Operation Rev. 1.41 99 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Application Circuits V D D 0 .0 1  F * * V D D 1 N 4 1 4 8 * R e s e t C ir c u it 1 0 k  ~ 1 0 0 k  0 .1  F 3 0 0  * R E S P A 0 ~ P A 7 0 .1 ~ 1  F V S S Note: "*" Recommended component for added ESD protection. "**" Recommended component in environments where power line noise is significant. HT68F002/HT68F0025 V D D 0 .0 1  F * * 1 N 4 1 4 8 * V D D R e s e t C ir c u it 1 0 k  ~ 1 0 0 k  0 .1  F 3 0 0  * R E S 0 .1 ~ 1  F P A 0 ~ P A 7 P B 0 ~ P B 5 V S S Note: "*" Recommended component for added ESD protection. "**" Recommended component in environments where power line noise is significant. HT68F003 Rev. 1.41 100 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 1.41 101 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction "RET" in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m]. i" instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be set as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the "HALT" instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.41 102 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rev. 1.41 103 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Mnemonic Description Cycles Flag Affected Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Read table (specific page) to TBLH and Data Memory Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note 2Note None None None No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRD [m] TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the "CLR WDT1" and "CLR WDT2" instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both "CLR WDT1" and "CLR WDT2" instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.41 104 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Instruction Definition ADC A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C ADCM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC ADD A,[m] Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C ADD A,x Description Operation Affected flag(s) Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C ADDM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C AND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z AND A,x Description Operation Affected flag(s) Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z ANDM A,[m] Description Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z Rev. 1.41 105 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM CALL addr Description Operation Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Affected flag(s) Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT1 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT2 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CPL [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z Rev. 1.41 106 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM CPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z DAA [m] Description Operation Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z HALT Description Operation Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Operation Affected flag(s) Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z Rev. 1.41 107 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM JMP addr Description Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Operation Affected flag(s) Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z OR A,x Description Operation Affected flag(s) Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z ORM A,[m] Description Operation Affected flag(s) Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z RET Description Operation Affected flag(s) Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None Rev. 1.41 108 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM RET A,x Description Operation Affected flag(s) Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None RETI Description Operation Affected flag(s) Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None RL [m] Description Operation Affected flag(s) Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None RLA [m] Description Operation Affected flag(s) Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None RLC [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C RLCA [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C RR [m] Description Operation Affected flag(s) Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None Rev. 1.41 109 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM RRA [m] Description Operation Affected flag(s) Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None RRC [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C RRCA [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C SBC A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C SBCM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C SDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None Rev. 1.41 110 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM SDZA [m] Description Operation Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Operation Affected flag(s) Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None SIZA [m] Description Operation Affected flag(s) Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None SNZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None SUB A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C Rev. 1.41 111 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C SUB A,x Description Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None SWAPA [m] Description Operation Affected flag(s) Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None SZ [m] Description Operation Affected flag(s) Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None SZA [m] Description Operation Affected flag(s) Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None SZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None Rev. 1.41 112 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM TABRD [m] Description Operation Affected flag(s) Read table (specific page) to TBLH and Data Memory The low byte of the program code (specific page) addressed by the table pointer pair (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDC [m] Description Operation Affected flag(s) Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDL [m] Description Operation Affected flag(s) Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None XOR A,[m] Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z XORM A,[m] Description Operation Affected flag(s) Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z XOR A,x Description Operation Affected flag(s) Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z Rev. 1.41 113 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/Carton Information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.41 114 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM 8-pin SOP (150mil) Outline Dimensions              Symbol Dimensions in inch Min. Nom. Max. A — 0.236 BSC — B — 0.154 BSC — 0.020 C 0.012 — C’ — 0.193 BSC — D — — 0.069 E — 0.050 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° — 8° Symbol A Rev. 1.41   Dimensions in mm Min. Nom. Max. — 6.00 BSC — B — 3.90 BSC — C 0.31 — 0.51 C’ — 4.90 BSC — D — — 1.75 E — 1.27 BSC — F 0.10 — 0.25 G 0.40 — 1.27 H 0.10 — 0.25 α 0° — 8° 115 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM 10-pin SOP (150mil) Outline Dimensions               Symbol Dimensions in inch Min. Nom. Max. — A — 0.236 BSC B — 0.154 BSC — C 0.012 — 0.018 C’ — 0.193 BSC — D — — 0.069 E — 0.039 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° — 8° Symbol Rev. 1.41   Dimensions in mm Min. Nom. Max. — A — 6.00 BSC B — 3.90 BSC — C 0.30 — 0.45 C’ — 4.90 BSC — D — — 1.75 E — 1.00 BSC — F 0.10 — 0.25 G 0.40 — 1.27 H 0.10 — 0.25 α 0° — 8° 116 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM 10-pin MSOP Outline Dimensions                                  Symbol Min. Nom. Max. A — — 0.043 A1 0.000 — 0.006 A2 0.030 0.033 0.037 B 0.007 — 0.013 C 0.003 — 0.009 D — 0.118 BSC — E — 0.193 BSC — E1 — 0.118 BSC — e — 0.020 BSC — L 0.016 0.024 0.031 L1 — 0.037 BSC — y — 0.004 — θ 0° — 8° Symbol Rev. 1.41 Dimensions in inch Dimensions in mm Min. Nom. Max. A — — 1.10 A1 0.00 — 0.15 A2 0.75 0.85 0.95 B 0.17 — 0.33 C 0.08 — 0.23 D — 3.00 BSC — E — 4.90 BSC — E1 — 3.00 BSC — e — 0.50 BSC — L 0.40 0.60 0.80 L1 — 0.95 BSC — y — 0.1 — θ 0° — 8° 117 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM 16-pin NSOP (150mil) Outline Dimensions              Symbol Dimensions in inch Min. Nom. Max. A — 0.236 BSC — B — 0.154 BSC — C 0.012 — 0.020 C’ — 0.390 BSC — D — — 0.069 E — 0.050 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° — 8° Symbol Rev. 1.41    Dimensions in mm Min. Nom. Max. A — 6.00 BSC — B — 3.90 BSC — C 0.31 — 0.51 C’ — 9.90 BSC — D — — 1.75 E — 1.27 BSC — F 0.10 — 0.25 G 0.40 — 1.27 H 0.10 — 0.25 α 0° — 8° 118 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Copyright© 2017 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw/en/home. Rev. 1.41 119 April 11, 2017