FAN6248HC/HD/LC/LD
Advanced Synchronous
Rectifier Controller for LLC
Resonant Converter
The FAN6248 is an advanced synchronous rectifier (SR) controller
that is optimized for LLC resonant converter topology with minimum
external components. It has two driver stages for driving the SR
MOSFETs which are rectifying the outputs of the secondary
transformer windings. The two gate driver stages have their own
sensing inputs and operate independently of each other. The adaptive
parasitic inductance compensation function minimizes the body diode
conduction maximizing the efficiency. The advanced control
algorithm allows stable SR operation over entire load range.
According to the operating frequency and turn-off threshold voltage,
FAN6248 has four different versions − FAN6248HCMX,
FAN6248HDMX, FAN6248LCMX, FAN6248LDMX.
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SOIC−8
CASE 751EB
MARKING DIAGRAM
Features
ZXYTT
FAN6248UV
ON
• Highly Integrated Self-contained Control of Synchronous Rectifier
•
•
•
•
•
•
•
•
•
•
•
•
•
•
with a Minimum External Component Count
Optimized for LLC Resonant Converter
Anti Shoot-through Control for Reliable SR Operation
Separate 100 V Rated Sense Inputs for Sensing the Drain and Source
Voltage of each SR MOSFET
Adaptive Parasitic Inductance Compensation to Minimize the Body
Diode Conduction
SR Current Inversion Detection under Light Load Condition
Light Load Detection to Increase Dead Time Target
Adaptive Minimum on Time for Noise Immunity
Operating Voltage Range up to 30 V
Low Start-up and Stand-by Current Consumption
Operating Frequency Range from 25 kHz up to 700 kHz
SOIC−8 Package
High Driver Output Voltage of 10.5 V to Drive All MOSFET Brands
to the Lowest RDS_ON
Low Operating Current in Green Mode (typ. 350 mA)
These Devices are Pb−Free, Halogen Free and are RoHS Compliant
= Frequency, H: High, L: Low
= VTH_OFF Level, C or D
= Assembly Plant Code
= Year Code
= Two Week Code
= Die Run Code
PIN CONNECTIONS
GATE1
1
8
GATE2
GND
2
7
VDD
VD1
3
6
VD2
VS1
4
5
VS2
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information on page 3 of
this data sheet.
Applications
•
•
•
•
•
•
U
V
Z
X
Y
TT
High Power Density Laptop Adapter
High Power Density Adapter
Large Screen LCD−TV, PDP−TV, RP−TV Power
High-efficiency Desktop and Server Power Supplies
Networking and Telecom Power Supplies
High Power LED Lighting
© Semiconductor Components Industries, LLC, 2017
January, 2018 − Rev. 2
1
Publication Order Number:
FAN6248HC/D
FAN6248HC/HD/LC/LD
M2
Optional
Roffset2
Q1
Lr
Q2
Lp
VS1 VS2
VO
VD1 VD2
Cr
G2
Cin
GND VDD
PFC
Stage
G1
Bridge
Diode
FAN6248
VAC
EMI
Filter
RO
CO
Optional
M1
LLC
Controller
Shunt
Regulator
Figure 1. Typical Application Schematic of FAN6248
VDD
7.2V
VD1_HGH
4.5/4.2V
VD2_HGH
GREEN
IOFFSET1
VTH_HGH
VD1
VTH_ON
DLY_EN
Adaptive
turn−on
debounce
D
Turn−on
Q
Q
CLR Q
D
Q CLR
Turn−on
VTH_HGH
Adaptive
turn−on
debounce
VD2
VTH_ON
Turn−off
Turn−off
VS1
IOFFSET2
DLY_EN
VTH_OFF1,2
VTH_OFF1,2
Turn−off
Trigger
Blanking
SRC_INV
SRC_INV
VS2
Turn−off
Trigger
Blanking
GATE2
GATE1
GATE1
GATE2
VD1_HGH
VD1_HGH
Green Mode
GREEN
SR Current
Inversion detect
IOFFSET1
Light Load
Detection
GND
Figure 2. Internal Block Diagram of FAN6248
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2
SRC_INV
DLY_EN
VD2_HGH
FAN6248HC/HD/LC/LD
PIN DESCRIPTION
Pin Number
Pin Name
Description
1
GATE1
2
GND
Ground
3
VD1
Synchronous rectifier drain sense input. A IOFFSET1 current source flows out of the DRAIN pin such
that an external series resistor can be used to adjust the synchronous rectifier turn-off threshold.
The IOFFSET1 current source is turned off when VDD is under-voltage or when switching is disabled in
green mode
4
VS1
Synchronous rectifier source sense input for SR1
5
VS2
Synchronous rectifier source sense input for SR2
6
VD2
Synchronous rectifier drain sense input. A IOFFSET2 current source flows out of the DRAIN pin such
that an external series resistor can be used to adjust the synchronous rectifier turn-off threshold.
The IOFFSET2 current source is turned off when VDD is under-voltage or when switching is disabled in
green mode
7
VDD
Supply Voltage
8
GATE2
Gate drive output for SR1
Gate drive output for SR2
ORDERING AND SHIPPING INFORMATION
Ordering Code
Device Marking
VTH_OFF1 / VTH_OFF2
Package
Shipping†
FAN6248HCMX
FAN6248HC
25 mV / 50 mV
SOIC−8
2500 / Tape & Reel
FAN6248HDMX
FAN6248HD
0 mV / 25 mV
SOIC−8
2500 / Tape & Reel
FAN6248LCMX
FAN6248LC
25 mV / 50 mV
SOIC−8
2500 / Tape & Reel
FAN6248LDMX
FAN6248LD
0 mV / 25 mV
SOIC−8
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
FAN6248HC/HD/LC/LD
MAXIMUM RATINGS
Symbol
VDD
Parameter
Power Supply Input Pin Voltage
Min
Max
Unit
−0.3
30
V
VD1, VD2
Drain Sense Input Pin Voltage
−1
100
V
VGATE1,
VGATE2
Gate Drive Output Pin Voltage
−0.3
30
V
VS1, VS2
Source Sense Input Pin Voltage
−0.4
0.4
V
0.625
W
165
°C/W
PD
Power Dissipation (TA = 25°C)
QJA
Thermal Resistance (Junction-to-Ambient Thermal)
TJ
TSTG
TL
ESD
Operating Junction Temperature
−40
150
°C
Storage Temperature Range
−60
150
°C
Lead Temperature (Soldering) 10 Seconds
Electrostatic Discharge
Capability
Human Body Model, ANSI / ESDA / JEDEC
JS−001−2012
Charged Device Model, JESD22−C101
260
°C
4
kV
1.75
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. All voltage values are with respect to the GND pin.
THERMAL CHARACTERISTICS
Symbol
Rating
Value
Unit
RyJT
Thermal Characteristics
22
_C/W
RqJA
Thermal Characteristics
165
_C/W
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
Parameter
VDD Pin Supply Voltage to GND (Note 2)
Min
Max
Unit
0
27
V
VD1 ,VD2
Drain Sense Input Pin Voltage
−0.7
100
V
VS1 VS2
Source Sense Input Pin Voltage
−0.4
0.4
V
Operating Ambient Temperature (Note 3)
−40
+125
°C
TA
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
2. Allowable operating supply voltage VDD can be limited by the power dissipation of FAN6248 related to switching frequency, load capacitance
and ambient temperature.
3. Allowable operating ambient temperature can be limited by the power dissipation of FAN6248 related to switching frequency, load
capacitance on GATE pin and VDD.
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4
FAN6248HC/HD/LC/LD
ELECTRICAL CHARACTERISTICS (VDD = 12 V and TJ = −40°C to +125°C unless otherwise specified)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
V
INPUT VOLTAGE
VDD_ON
VDD_OFF
VDD_GATE_ON
*
IDD_OP
Turn-On Threshold
VDD rising
4.2
4.5
4.7
Turn-Off Threshold
VDD falling
4.0
4.2
4.4
SR Gate Enable Threshold Voltage
VDD rising
Operating Current
fSW = 100 kHz, CGATE = 3.3 nF
IDD_SRARTUP
IDD_GREEN
7.2
7
8.5
10
mA
200
mA
350
500
mA
−1
0
1
mV
VDD = VDD_ON − 0.1 V
Operating Current in Green Mode
V
VDD = 12 V (no switching)
DRAIN VOLTAGE SENSING SECTION (VD1 = VD2)
VOSI*
Comparator Input Offset Voltage
IOFFSET*
IOFFSET1 and IOFFSET2
Maximum of adaptive offset
current (15 steps, 9 mA resolution)
IOFFSET=IOFFSET_STEP15
112.5
135
157.5
mA
VTH_ON
Turn-On Threshold
RDRAIN = 0 W (includes
comparator input offset voltage)
−290
−240
−190
mV
tON_DLY*
Turn on delay for de-bounce time
when turn-on delay mode is disabled
by detecting normal SR current
From VD1 falling below VTH_ON to
VGATE rising above VG_HG (With
50 mV overdrive), CGATE = 0 nF
80
ns
tON_DLY2_H*
Turn on delay for de-bounce time
when turn-on delay mode is enabled
by detecting SR current inversion for
HC and HD version
From VD1 falling below VTH_ON to
VGATE rising above VG_HG (With
50 mV overdrive), CGATE = 0 nF
850
ns
tON_DLY2_L*
Turn on delay for de-bounce time
when turn-on delay mode is enabled
by detecting SR current inversion for
LC and LD version
From VD1 falling below VTH_ON to
VGATE rising above VG_HG (With
50 mV overdrive), CGATE = 0 nF
1100
ns
VTH_OFF1_C*
First Level Turn-Off Threshold
for HC and LC version
RDRAIN = 0 W (includes
comparator input offset voltage)
25
mV
VTH_OFF2_C*
Second Level Turn-Off Threshold
for HC and LC version
RDRAIN = 0 W (includes
comparator input offset voltage)
50
mV
VTH_OFF1_D*
First Level Turn-Off Threshold
for HD and LD version
RDRAIN = 0 W (includes
comparator input offset voltage)
0
mV
VTH_OFF2_D*
Second Level Turn-Off Threshold
for HD and LD version
RDRAIN = 0 W (includes
comparator input offset voltage)
25
mV
tOFF_DLY*
Comparator Delay of VTH_OFF1
From VD1 rising above VTH_OFF to
VGATE falling below VG_LW (With
10 mV overdrive), CGATE = 0 nF
50
ns
VTH_HGH
Drain Voltage High Detect Threshold
VD1 Rising
tDB_HGH_H*
VTH_HGH Detection Blanking Time for
HC and HD version
From VD1 falling below VTH_ON
540
ns
tDB_HGH_L*
VTH_HGH Detection Blanking Time for
LC and LD version
From VD1 falling below VTH_ON
1
ms
Forced Turn-off Threshold
VD1 > VOFF_FORCE = VTH_HGH_EN
1
V
Adaptive Minimum On Time Ratio
Ratio between tON_MIN and SR
conduction time of previous
switching cycle
25
%
tON_MIN_LH*
Minimum On-Time Lower Limit
for HC and HD version
tON_MIN_LH < tON_MIN <
tON_MIN_UH
200
ns
tON_MIN_UH
Minimum On-Time Upper Limit
for HC and HD version
VOFF_FORCE*
0.80
1
1.20
V
MINIMUM ON-TIME AND MAXIMUM ON-TIME
KTON*
0.96
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5
1.2
1.44
ms
FAN6248HC/HD/LC/LD
ELECTRICAL CHARACTERISTICS (VDD = 12 V and TJ = −40°C to +125°C unless otherwise specified) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MINIMUM ON-TIME AND MAXIMUM ON-TIME
ms
tON_MIN_LL*
Minimum On-Time Lower Limit
for LC and LD version
tON_MIN_UL
Minimum On-Time Upper Limit
for LD and LD version
tSR_CNDT_H
Minimum SR Conduction Time to
enable SR for HC and HD version
tSR_CNDT_L
Minimum SR Conduction Time to
enable SR for LC and LD version
tSR_MAX_H*
Maximum SR Turn-on Time
for HC and HD version
15
ms
tSR_MAX_L*
Maximum SR Turn-on Time
for LC and LD version
30
ms
tON_MIN_LL < tON_MIN <
tON_MIN_UL
0.4
3.2
4
4.8
ms
The duration from turn-on trigger
to VDS rising above VTH_HGH
380
600
820
ns
The duration from turn-on trigger
to VDS rising above VTH_HGH
0.85
1.2
1.65
ms
REGULATED DEAD TIME
tDEAD_H*
Dead time regulation target
for HC and HD version
From VGATE falling below VG_LW
to VDS rising above VTH_HGH
280
ns
Dead time regulation target under
light load condition for HC and HD
version
From VGATE falling below VG_LW
to VDS rising above VTH_HGH
320
ns
Dead time regulation target
for LC and LD version
From VGATE falling below VG_LW
to VDS rising above VTH_HGH
320
ns
tDEAD_L_LIGHT*
Dead time regulation target under
light load condition for LC and LD
version
From VGATE falling below VG_LW
to VDS rising above VTH_HGH
360
ns
tTSDT*
Too small dead time threshold to
speed up IOFFSET change
(Speed up 2 times)
From VGATE falling below VG_LW
to VDS rising above VTH_HGH
50
ns
KINV*
Adaptive SR current inversion
detection time Ratio between TINV
and SR conduction time of previous
switching cycle
VGATE > VG_HG and VDS >
VTH_OFF
KINV = 0.25 × KTON
6.25
%
31
cycle
tDEAD_H_LIGHT*
tDEAD_L*
hINV_EXT*
Normal switching cycles without
capacitive current spike to exit SR
current inversion detection state
which has tON_DLY2
GREEN MODE CONTROL
tGRN_ENT_H
Non-Switching Period to Enter Green
Mode for HC and HD version
Non switching cycles between
burst switching bundles
60
80
100
ms
tGRN_ENT_L
Non-Switching Period to Enter Green
Mode for LC and LD version
Non switching cycles between
burst switching bundles
120
160
200
ms
tGRN_ENT_DBNC_H
De-bounce time to Enter Green Mode
for HC and HD version
De-bounce time after tGRN.ENT_H
130
180
230
ms
tGRN_ENT_DBNC_L
De-bounce time to Enter Green Mode
for LC and LD version
De-bounce time after tGRN_ENT_L
240
320
400
ms
tGRN_EXT_H
Non-Switching Period to Exit Green
for HC and HD version
Non switching cycles between
burst switching bundles
30
40
50
ms
tGRN_EXT_L
Non-Switching Period to Exit Green
Mode for LC and LD version
Non switching cycles between
burst switching bundles
60
80
100
ms
hCSW_EXT
Continuous switching cycles to exit
Green Mode for HC, HD, LC and LD
version
4
7
10
cycle
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FAN6248HC/HD/LC/LD
ELECTRICAL CHARACTERISTICS (VDD = 12 V and TJ = −40°C to +125°C unless otherwise specified) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
GREEN MODE CONTROL
tS_NORMAL_H
Switching period to be recognized as
normal switching for HC and HD
version
13
20
27
ms
tS_NORMAL_L
Switching period to be recognized as
normal switching for LC and LD
version
27
40
53
ms
9
10.5
12
V
1.5
V
OUTPUT DRIVER SECTION
VGATE_MAX
VOL
VOH
ISOURCE
ISINK
*
*
Gate Clamping Voltage
12 V < VDD < 25 V
Output Voltage Low
VDD = 12 V, VD1 = VD2 = 2 V,
IGATE = 50 mA
Output Voltage High
VDD = 12 V, IGATE = −50 mA
Peak Source Current for Turning On
VDD = 12 V, VGATE = 2 V
0.7
7
V
A
Peak Sink Current for Turning Off
VDD = 12 V, VGATE = 7 V
1.4
A
tR*
Rise Time
VDD = 12 V, CL = 3.3 nF,
VGATE = 2 V ³ 7 V
50
ns
tF*
Fall Time
VDD = 12 V, CL = 3.3 nF,
VGATE = 7 V ³ 2 V
30
ns
VG_LW*
Gate voltage considered as turned off
for adaptive dead time control
Gate falling
4
V
VG_HG*
Gate voltage considered as turned on
for adaptive dead time control
Gate rising
6
V
SWITCHING FREQUENCY
fMAX*
fMIN
*
Maximum Switching Frequency
700
Minimum Switching Frequency
kHz
25
kHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
*Not tested but guaranteed by design
KEY DIFFERENT PARAMETERS FOR FAN6248 OPTIONS
Item
FAN6248HC
FAN6248HD
FAN6248LC
FAN6248LD
tON_DLY2
850 ns
850 ns
1100 ns
1100 ns
tDB_HGH
540 ns
540 ns
1 ms
1 ms
tON_MIN_L
200 ns
200 ns
400 ns
400 ns
tON_MIN_U
1.2 ms
1.2 ms
4 ms
4 ms
tSR_CNDT
0.6 ms
0.6 ms
1.2 ms
1.2 ms
tSR_MAX
15 ms
15 ms
30 ms
30 ms
tDEAD
280 ns
280 ns
320 ns
320 ns
tDEAD_LIGHT
320 ns
320 ns
360 ns
360 ns
tGRN_ENT
80 ms
80 ms
160 ms
160 ms
tGRN_EXT
40 ms
40 ms
80 ms
80 ms
tS_NORMAL
20 ms
20 ms
40 ms
40 ms
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FAN6248HC/HD/LC/LD
5.0
4.7
4.8
4.5
VDD_OFF [V]
VDD_ON [V]
TYPICAL CHARACTERISTICS
4.6
4.4
4.2
4.0
−40
4.3
4.1
3.9
−30
−15
0
25
50
75
85
100
3.7
−40
125
−30
−15
0
25
50
75
85
100 125
85
100
125
85
100
125
Temperature [5C]
Temperature [5C]
Figure 3. VDD_ON
Figure 4. VDD_OFF
9.0
480
440
IDD_GREEN [mA]
IDD_OP [mA]
8.6
8.2
7.8
400
360
320
280
7.4
240
7.0
−40
−30
−15
0
25
50
75
85
100
200
−40
125
−30
−15
Temperature [5C]
50
75
Figure 6. IDD_GREEN
1.3
−200
1.1
−220
VTH_ON [mV]
VTH_HIGH [V]
25
Temperature [5C]
Figure 5. IDD_OP
0.9
0.7
0.5
0.3
−40
0
−240
−260
−280
−30
−15
0
25
50
75
85
100
−300
−40
125
−30
−15
0
25
50
75
Temperature [5C]
Temperature [5C]
Figure 7. VTH_HIGH
Figure 8. VTH_ON
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8
FAN6248HC/HD/LC/LD
1100
1500
1050
1400
tON_MIN_UL [ms]
tON_MIN_UH [ms]
TYPICAL CHARACTERISTICS
1000
950
900
850
−40
1300
1200
1100
−30
−15
0
25
50
75
85
100
1000
−40
125
−30
−15
Temperature [5C]
620
1.5
tSR_CNDT_L [ms]
tSR_CNDT_H [ns]
1.7
540
460
380
75
85
100
125
85
100
125
1.3
1.1
0.9
−30
−15
0
25
50
75
85
100
0.7
−40
125
−30
−15
0
25
50
75
Temperature [5C]
Temperature [5C]
Figure 11. tSR_CNDT_H
Figure 12. tSR_CNDT_L
90
180
86
172
tGRN_ENT_L [ms]
tGRN_ENT_H [ms]
50
Figure 10. tON_DLY2_L
700
82
78
74
70
−40
25
Temperature [5C]
Figure 9. tON_DLY2_H
300
−40
0
164
156
148
−30
−15
0
25
50
75
85
100
140
−40
125
Temperature [5C]
−30
−15
0
25
50
75
Temperature [5C]
Figure 13. tGRN_ENT_H
Figure 14. tGRN_ENT_L
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9
85
100
125
FAN6248HC/HD/LC/LD
48
90
44
86
tGRN_EXT_L [ms]
tGRN_EXT_H [ms]
TYPICAL CHARACTERISTICS
40
36
82
78
32
−30
−15
0
25
50
75
85
100
70
−40
125
25
50
75
Figure 16. tGRN_EXT_L
10
13
8
6
4
85
100
125
85
100
125
85
100
125
11
9
7
−30
−15
0
25
50
75
85
100
5
−40
125
−30
−15
0
25
50
75
Temperature [5C]
Temperature [5C]
Figure 17. hCSW_EXT
Figure 18. VGATE_MAX
15
0.40
13
0.32
11
0.24
VOL [V]
VOH [V]
0
Figure 15. tGRN_EXT_H
15
9
0.16
7
5
−40
−15
Temperature [5C]
12
2
−40
−30
Temperature [5C]
VGATE_MAX [v]
hCSW_EXT
28
−40
74
0.08
−30
−15
0
25
50
75
85
100
0
−40
125
Temperature [5C]
−30
−15
0
25
50
75
Temperature [5C]
Figure 19. VOH
Figure 20. VOL
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FAN6248HC/HD/LC/LD
APPLICATION INFORMATION
Present information
=instantaneous Vdrain type
Basic Operation Principle
FAN6248 controls the SR MOSFET based on the
instantaneous drain-to-source voltage sensed across DRAIN
and SOURCE pins. Before SR gate is turned on, SR body
diode operates as the conventional diode rectifier. Once the
body diode starts conducting, the drain-to-source voltage
drops below the turn-on threshold voltage VTH_ON which
triggers the turn-on of the SR gate. Then the drain-to-source
voltage is determined by the product of turn-on resistance
Rds_on of SR MOSFET and instantaneous SR current. When
the drain-to-source voltage reaches the turn-off threshold
voltage VTH_OFF as SR MOSFET current decreases to near
zero, FAN6248 turns off the gate. If a SR dead time is larger
or smaller than the dead time regulation target tDEAD ,
FAN6248 adaptively changes internal offset voltage to
compensate the dead time. In addition, to prevent cross
conduction SR operation, FAN6248 has 200 ns of turn-on
blocking time just after alternating SR gate is turned off.
Present information+Previous cycle information
= Mixed type control
SR on
V Drain
Voffset
control
S
V offset
=R offset x I offset
V SAW
SR off
Gate
S
Q
R
Q
V TH_off
Previous cycle information
=Prediction type
Figure 21. SR Turn-off Algorithm
Adaptive Dead Time Control
The stray inductances of the lead frame of SR MOSFET
and PCB pattern induce positive voltage offset across
drain-to-source voltage when SR current decreases. This
makes drain-to-source voltage of SR MOSFET larger than
the product of Rds_on and instantaneous SR current, which
results in premature turn-off of SR gate. Since the induced
offset voltage changes as load condition changes, the dead
time also changes with load variation. To compensate the
induced offset voltage, FAN6248 has a adaptive virtual
turn-off threshold voltage as shown in Figure 22 with
a combination of variable internal turn-off threshold
voltages VTH_OFF1 and VTH_OFF2 (2 steps) and modulated
offset voltage Voffset (16 steps). The virtual turn-off
threshold voltage can be expressed as:
SR Turn-off Algorithm
Since a SR turn-off method determines SR conduction
time and stable SR operation, the SR turn-off method is one
of important feature of SR controllers. The SR turn-off
method can be classified into two methods. The first method
uses present information by an instantaneous drain voltage.
This method is widely used and easy to realize, and can
prevent late turn-off. However, it may show premature
turn-off by parasitic stray inductances caused by PCB
pattern and lead frame of SR MOSFET. The second method
predicts SR conduction time by using previous cycle drain
voltage information. Since it can prevent the premature
turn-off, it is good for the system with constant operating
frequency and turn-on time. However, in case of the
frequency varying system, it may lead late turn-off so that
negative current can flow in the secondary side.
To achieve both advantages, FAN6248 adopts mixed type
control method as shown in Figure 21. Basically the
instantaneous drain voltage VDrain is compared with
VTH_OFF to turn off SR gate. Then, the offset voltage Voffset ,
which is determined by the product Roffset and Ioffset , is added
to VDrain in order to compensate the stray inductance effect
and maintain 280 ns of tDEAD regardless of parasitic
inductances. Roffset is an external resistor in Figure 1 and
Ioffset is an internal modulation current in Figure 2.
Therefore, FAN6248 can show robust operation with
minimum dead time.
Virtual V TH_OFF + V TH_OFF * V offset
(eq. 1)
In FAN6248HC(D) version, if a dead time TDEAD is larger
than 280 ns of tDEAD_H , as shown in Figure 23, Voffset is
decreased by one step in next switching cycle. As a result,
the dead time is decreased by increase of virtual VTH_OFF,
and becomes close to tDEAD_H , as shown in Figure 24. If the
dead time is smaller than tDEAD_H , the dead time is increased
by the virtual VTH_OFF decrease. Thus, the dead time is
maintained at around tDEAD_H regardless of parasitic
inductances.
V TH_ON
SR on
SR gate
S
Q
R
Q
VDrain
SR off
Virtual V TH_OFF
=V TH_OFF −Voffset
Figure 22. Virtual VTH_OFF
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11
FAN6248HC/HD/LC/LD
magnetizing inductance of the transformer is smaller than
the reflected output voltage. Thus, the secondary side SR
body diode conduction is delayed until the magnetizing
inductor voltage builds up to the reflected output voltage.
However, the primary side switching transition can cause
capacitive current spike and turn on the body diode of SR
MOSFET for a short time as shown in Figure 26, which
induces SR mis-trigger signal. Finally, the SR mis-trigger
makes inversion current in the secondary side. If a proper
algorithm is not provided to prevent the mis-trigger by the
capacitive current spike, severe SR current inversion can
happen.
To prevent the SR mis-trigger, FAN6248 has a capacitive
current spike detection method. When SR current inversion
occurs by the mis-trigger signal, the drain sensing voltage of
SR MOSFET becomes positive. In this condition, if VDS_SR
is higher than VTH_OFF for (TSRCOND × KINV ), SR current
inversion is detected. After then, FAN6248 turns off SR
immediately and increases turn-on delay to tON_DLY2 next
cycle.
I SD_SR
VDrain
Virtual V TH_OFF
VTH_ON
VGATE_SR
T DEAD > 280 ns
Figure 23. Premature SR Gate Turn-off
(TDEAD > tDEAD_H)
I SD_SR
V Drain
VDS_SR
Virtual VTH_OFF
Turn−off trigger is prohibited
during T ON_MIN
V TH_ON
VTH_HGH
VTH_OFF
VGATE_SR
VTH_ON
T DEAD 9 280 ns
TON_MIN = 25% of T SRCOND of previous cycle
Figure 24. Dead Time Control to Maintain
TDEAD 9 tDEAD_H
SR conduction time = T SRCOND
tON_DLY
Minimum Turn-on Time
VGS.SR
TDEAD
IDS_SR
When SR gate is turned on, there may be severe oscillation
in drain-to-source voltage of SR MOSFET, which results in
several mis-triggering turn-off as shown in Figure 25. To
provide stable SR control without mis-trigger, it is desirable
to have large turn-off blanking time (= minimum turn-on
time) until the drain voltage oscillation attenuates. However,
too large blanking time results in problems at light load
condition where the SR conduction time is shorter than the
minimum turn-on time. To solve this issue, FAN6248 has
adaptive minimum turn-on time where the turn-off blanking
time changes in accordance with the SR conduction time
TSRCOND measured in previous switching cycle. The SR
conduction time is measured by the time from SR gate rising
edge to the instant when drain sensing voltage VDS_SR is
higher than VTH_HGH . From the previous cycle TSRCOND
measurement result, the minimum turn-on time is defined by
25% of TSRCOND .
ISD.SR
Figure 25. Minimum Turn-on Time
IDS_SR
VDS_SR
Capacitive current spike
Capacitive current spike
t
VTH_ON
VGATE
VGATE_SR1
VGATE_SR1
Figure 26. Capacitive Current Spike at Light Load
Condition
Capacitive Current Spike Detection
As a result, SR mis-trigger is prevented. To exit the SR
current inversion detection mode, seven consecutive
switching cycles without capacitive current spike are
required.
At heavy load condition, the body diode of SR MOSFET
in LLC resonant converter starts conducting right after the
primary side switching transition takes place. However,
when the resonance capacitor voltage amplitude is not large
enough at light load condition, the voltage across the
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12
FAN6248HC/HD/LC/LD
Light Load Detection (LLD)
Virtual V TH_OFF
To guarantee stable operation under light load condition,
FAN6248 adopts a light load detection function. The
modulation current IOFFSET is mainly used for the adaptive
dead time control. When the output load is heavy,
IOFFSET_STEP declines due to large di/dt in the secondary
side current to maintain 280 ns of tDEAD in FAN6248HC(D).
On the contrary, IOFFSET_STEP increases at light load
condition by small di/dt of SR current. FAN6248 can detect
light load condition by using this IOFFSET_STEP as shown in
Figure 27. When SR turn-off threshold voltage is VTH_OFF1
and the modulation current is higher than IOFFEST_STEP8 , the
light load detection is triggered. In this mode, dead time
target becomes to 320 ns of tDEAD_LIGHT in
FAN6248HC(D) and 360 ns in FAN6248LC(D) version.
Heavy
Load
VTH_OFF2
VTH_OFF2−ROFFSET x IOFFSET_STEP1
VTH_OFF2−ROFFSET x IOFFSET_STEP2
VTH_OFF2
Range
VTH_OFF2−ROFFSET x IOFFSET_STEP13
VTH_OFF1
VTH_OFF2−ROFFSET x IOFFSET_STEP15
VTH_OFF1−ROFFSET x IOFFSET_STEP2
VTH_OFF1
Range
VTH_OFF1−ROFFSET x IOFFSET_STEP8
LDD Trigger
Light
Load
VTH_OFF1−ROFFSET x IOFFSET_STEP14
VTH_OFF1−ROFFSET x IOFFSET_STEP15
Figure 27. Light Load Detection
Green Mode
When the power supply system operates at very light load
condition, FAN6248 disables SR operation and enters into
green mode operation. Once FAN6248 is in the green mode,
all the major blocks are disabled to minimize the operating
current. When VDS_SR has no switching operation longer
than tGRN_ENT during the burst mode of the primary side
LLC controller, the green mode is enabled after
tGRN_ENT_DBNC of debounce time. After then, FAN6248
exits the green mode when the non−switching time in the
burst mode is less than tGRN_EXT_H or 7 consecutive
switching cycles are detected as shown in Figure 28.
VGATE1
Green Exit
hCSW_EXT = 7 Cycles
VDS_SR1
ISD_SR1
Figure 28. Green Mode Exit
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13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC8
CASE 751EB
ISSUE A
DOCUMENT NUMBER:
DESCRIPTION:
98AON13735G
SOIC8
DATE 24 AUG 2017
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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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