UPA2710GR

DATA SHEET MOS FIELD EFFECT TRANSISTOR µ PA2710GR SWITCHING P-CHANNEL POWER MOS FET DESCRIPTION The µPA2710GR is P-Channel MOS Field Effect Transistor designed for power management applications of notebook computers and Li-ion battery protection circuit. PACKAGE DRAWING (Unit: mm) 8 5 1, 2, 3 : Source 4 : Gate 5, 6, 7, 8 : Drain FEATURES • Low on-state resistance RDS(on)1 = 5.5 mΩ MAX. (VGS = –10 V, ID = –7.5 A) RDS(on)2 = 9.0 mΩ MAX. (VGS = –4.5 V, ID = –7.5 A) RDS(on)3 = 11 mΩ MAX. (VGS = –4.0 V, ID = –7.5 A) 5 • Low Ciss: Ciss = 4300 pF TYP. • Small and surface mount package (Power SOP8) 1 4 5.37 MAX. +0.10 –0.05 6.0 ±0.3 4.4 0.8 1.8 MAX. 1.44 0.15 0.05 MIN. 0.5 ±0.2 0.10 ORDERING INFORMATION PART NUMBER PACKAGE Power SOP8 1.27 0.78 MAX. 0.40 +0.10 –0.05 0.12 M µPA2710GR ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.) Drain to Source Voltage (VGS = 0 V) Gate to Source Voltage (VDS = 0 V) Drain Current (DC) Drain Current (pulse) Note1 Note2 Note3 VDSS VGSS ID(DC) ID(pulse) PT1 PT2 Tch Tstg –30 m20 m15 m100 2 2 150 –55 to + 150 −15 22.5 V V A A W W °C °C A mJ Source Gate Body Diode Drain EQUIVALENT CIRCUIT Total Power Dissipation Total Power Dissipation Channel Temperature Storage Temperature Single Avalanche Current Single Avalanche Energy Notes 1. 2. 3. 4. Remark Note4 Note4 IAS EAS PW ≤ 10 µs, Duty Cycle ≤ 1% 2 Mounted on ceramic substrate of 1200 mm x 2.2 mm Mounted on a glass epoxy board (1 inch x 1 inch x 0.8 mm), PW = 10 sec Starting Tch = 25°C, VDD = –15 V, RG = 25 Ω, L = 100 µH, VGS = –20 → 0 V Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. G15978EJ3V0DS00 (3rd edition) Date Published February 2003 NS CP(K) Printed in Japan The mark 5 shows major revised points. 2002 µPA2710GR 5 ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.) CHARACTERISTICS Zero Gate Voltage Drain Current Gate Leakage Current Gate Cut-off Voltage Note Note Note SYMBOL IDSS IGSS VGS(off) | yfs | RDS(on)1 RDS(on)2 RDS(on)3 TEST CONDITIONS VDS = –30 V, VGS = 0 V VGS = m20 V, VDS = 0 V VDS = –10 V, ID = –1 mA VDS = –10 V, ID = –7.5 A VGS = –10 V, ID = –7.5 A VGS = –4.5 V, ID = –7.5 A VGS = –4.0 V, ID = –7.5 A VDS = –10 V VGS = 0 V f = 1 MHz VDD = –15 V, ID = –7.5 A VGS = –10 V RG = 10 Ω MIN. TYP. MAX. UNIT –1 m100 –1.0 14 31 4.7 6.4 7.2 4300 1200 690 11 22 420 240 5.5 9.0 11 µA nA V S mΩ mΩ mΩ pF pF pF ns ns ns ns nC nC nC V ns nC –2.5 Forward Transfer Admittance Drain to Source On-state Resistance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate to Source Charge Gate to Drain Charge Body Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Ciss Coss Crss td(on) tr td(off) tf QG QGS QGD VF(S-D) trr Qrr VDD = –24 V VGS = –10 V ID = –15 A IF = 15 A, VGS = 0 V IF = 15 A, VGS = 0 V di/dt = 50 A/µs 97 12 29 0.79 119 84 Note Pulsed PW ≤350 µs, Duty Cycle≤2% TEST CIRCUIT 1 AVALANCHE CAPABILITY D.U.T. RG = 25 Ω PG VGS = –20 → 0 V − ID VDD BVDSS VDS VGS(−) 0 τ τ = 1 µs Duty Cycle ≤ 1% VDS Wave Form TEST CIRCUIT 2 SWITCHING TIME L VDD PG. D.U.T. RL VGS(−) VGS Wave Form 50 Ω RG 0 10% VGS 90% VDD VDS(−) 90% 90% 10% 10% IAS VDS 0 td(on) ton tr td(off) toff tf Starting Tch TEST CIRCUIT 3 GATE CHARGE D.U.T. IG = −2 mA 50 Ω RL VDD PG. 2 Data Sheet G15978EJ3V0DS µPA2710GR TYPICAL CHARACTERISTICS (TA = 25°C) DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA 120 TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE 2.8 Mounted on ceramic substrate of 2 1200 mm x 2.2 mm dT - Percentage of Rated Power - % PT - Total Power Dissipation - W 100 2.4 2 1.6 1.2 0.8 0.4 0 80 60 40 20 0 0 25 50 75 100 125 150 175 0 25 50 75 100 125 150 175 TA - Ambient Temperature - °C TA - Ambient Temperature - °C 5 FORWARD BIAS SAFE OPERATING AREA - 1000 PW=100 µs ID(pulse) RDS(on) Limited 1 ms ID(DC) ID - Drain Current - A - 100 - 10 10 ms DC -1 TA = 25°C Single Pulse 100 ms Power Dissipation Limited - 0.1 - 0.01 - 0.01 Mounted on ceramic substrate of 1200 mm2 x 2.2 mm - 0.1 -1 - 10 - 100 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH 1000 rth(t) - Transient Thermal Resistance - °C/W 100 Rth(ch-A) = 62.5°C/W 10 1 0.1 Mounted on ceramic substrate of 2 1200 mm x 2.2 mm Single Pulse 0.01 100 µ 1m 10 m 100 m 1 10 100 1000 PW - Pulse Width - s Data Sheet G15978EJ3V0DS 3 µPA2710GR 5 - 120 - 100 - 80 - 60 - 40 - 20 0 0 - 0.4 - 0.8 - 1.2 VGS = −1 V −4.5 V Pulsed ID - Drain Current - A DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE 5 FORWARD TRANSFER CHARACTERISTICS - 1000 Pulsed - 100 T ch = − 55°C 25°C 75°C 150°C ID - Drain Current - A −4.0 V - 10 -1 - 0.1 V DS = − 10 V - 0.01 0 -1 -2 -3 -4 -5 VDS - Drain to Source Voltage - V VGS - Gate to Source Voltage - V 5 - 2.5 GATE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE | yfs | - Forward Transfer Admittance - S 5 FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT 100 Tc h = − 55°C 25°C 75°C 150°C 10 VGS(off) - Gate Cut-off Voltage - V -2 - 1.5 -1 1 V D S = − 10 V P uls ed 0.1 - 0.1 - 0.5 P uls ed V D S = − 10 V 0 - 50 0 50 100 150 -1 - 10 - 100 Tch - Channel Temperature - °C ID - Drain Current - A 5 DRAIN TO SOURCE ON-STATE RDS(on) - Drain to Source On-state Resistance - mΩ 20 5 DRAIN TO SOURCE ON-STATE RESISTANCE vs. RDS(on) - Drain to Source On-state Resistance - mΩ GATE TO SOURCE VOLTAGE 40 RESISTANCE vs. DRAIN CURRENT P uls ed 15 30 P uls ed ID = − 7.5 A 10 V G S = − 4.0V 20 5 − 4.5 V − 10 V 10 0 - 0.1 0 0 -5 - 10 - 15 - 20 -1 - 10 - 100 ID - Drain Current - A VGS - Gate to Source Voltage - V 4 Data Sheet G15978EJ3V0DS µPA2710GR 5 DRAIN TO SOURCE ON-STATERESISTANCE vs. RDS(on) - Drain to Source On-state Resistance - mΩ CHANNEL TEMPERATURE 15 5 CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 10 00 0 10 V GS = − 4.0 V − 4.5 V − 10 V Ciss, Coss, Crss - Capacitance - pF C is s 10 00 C os s C rs s 5 P uls ed ID = − 7.5 A 0 - 50 10 0 V GS = 0 V f = 1 M Hz 10 0.0 1 0 50 100 150 0.1 1 10 10 0 Tch - Channel Temperature - °C VDS - Drain to Source Voltage - V 5 SWITCHING CHARACTERISTICS 1000 VDS - Drain to Source Voltage - V td(on), tr, td(off), tf - Switching Time - ns 5 DYNAMIC INPUT/OUTPUT CHARACTERISTICS - 30 - 15 V DD = − 24 V − 15 V −6 V VGS - Gate to Source Voltage - V td(off) tf 100 tr 10 VDD = −15 V VGS = −10 V RG = 10 Ω 1 - 0.1 -1 - 10 - 100 td(on) - 20 - 10 - 10 V GS V DS 0 0 20 40 60 80 -5 ID = − 15 A 0 100 ID - Drain Current - A QG - Gate Charge - nC 5 SOURCE TO DRAIN DIODE FORWARD VOLTAGE 1000 P uls ed V G S = − 10 V 0V 5 10000 REVERSE RECOVERY TIME vs. DIODE FORWARD CURRENT 100 trr - Reverse Recovery Time - ns IF - Diode Forward Current - A 1000 10 1 100 0.1 VGS = 0 V di/dt = 50 A /µ s 10 0.1 1 10 100 0.01 0 0.2 0.4 0.6 0.8 1 1.2 VF(S-D) - Source to Drain Voltage - V IF - Diode Forward Current - A Data Sheet G15978EJ3V0DS 5 µPA2710GR SINGLE AVALANCHE CURRENT vs. INDUCTIVE LOAD - 100 100 SINGLE AVALANCHE ENERGY DERATING FACTOR VDD = −15 V RG = 25 Ω VGS = −20 → 0 V IAS ≤ −15 A IAS - Single Avalanche Current - A Energy Derating Factor - % IAS = − 15 A - 10 E AS = 2 2.5 mJ 80 60 40 -1 V DD = − 15 V V GS = − 20 → 0 V R G = 25 Ω Starting T ch = 2 5°C 0.1 1 10 20 - 0.1 0.01 0 25 50 75 100 125 150 L - Inductive Load - mH Starting Tch - Starting Channel Temperature - °C 6 Data Sheet G15978EJ3V0DS µPA2710GR • The information in this document is current as of February, 2003. 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