Freescale Semiconductor
Technical Data
Document Number: A2T09VD250N
Rev. 0, 8/2015
RF Power LDMOS Transistor
N--Channel Enhancement--Mode Lateral MOSFET
This 65 W RF power LDMOS transistor is designed for cellular base station
applications covering the frequency range of 716 to 960 MHz.
A2T09VD250NR1
900 MHz
Typical Single--Carrier W--CDMA Performance: VDD = 48 Vdc,
IDQ(A+B) = 1000 mA, Pout = 65 W Avg., Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF.
Frequency
Gps
(dB)
D
(%)
Output PAR
(dB)
ACPR
(dBc)
IRL
(dB)
920 MHz
22.5
34.8
7.5
–34.4
–18
940 MHz
22.7
35.4
7.4
–34.2
–19
960 MHz
22.4
35.4
7.2
–34.3
–12
716–960 MHz, 65 W AVG., 48 V
AIRFAST RF POWER LDMOS
TRANSISTOR
800 MHz
TO--270WB--6A
PLASTIC
Typical Single--Carrier W--CDMA Performance: VDD = 48 Vdc,
IDQ(A+B) = 1000 mA, Pout = 65 W Avg., Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF.
Frequency
Gps
(dB)
D
(%)
Output PAR
(dB)
ACPR
(dBc)
IRL
(dB)
790 MHz
23.0
37.3
7.4
–33.0
–15
806 MHz
23.1
37.8
7.2
–33.3
–19
821 MHz
22.8
37.0
7.0
–33.8
–13
RFinA/VGSA 1
6 RFoutA/VDSA
GND 2
5 GND
RFinB/VGSB 3
4 RFoutB/VDSB
Features
Greater Negative Gate--Source Voltage Range for Improved Class C
Operation
Designed for Digital Predistortion Error Correction Systems
Optimized for Doherty Applications
(Top View)
Note: Exposed backside of the package is
the source terminal for the transistors.
Figure 1. Pin Connections
Freescale Semiconductor, Inc., 2015. All rights reserved.
RF Device Data
Freescale Semiconductor, Inc.
A2T09VD250NR1
1
Table 1. Maximum Ratings
Symbol
Value
Unit
Drain--Source Voltage
Rating
VDSS
–0.5, +105
Vdc
Gate--Source Voltage
VGS
–6.0, +10
Vdc
Operating Voltage
VDD
55, +0
Vdc
Storage Temperature Range
Tstg
–65 to +150
C
Case Operating Temperature Range
TC
–40 to +150
C
TJ
–40 to +225
C
Symbol
Value (2,3)
Unit
RJC
0.56
C/W
Operating Junction Temperature
Range (1,2)
Table 2. Thermal Characteristics
Characteristic
Thermal Resistance, Junction to Case
Case Temperature 82C, 65 W CW, 48 Vdc, IDQ(A+B) = 1000 mA, 940 MHz
Table 3. ESD Protection Characteristics
Test Methodology
Class
Human Body Model (per JESD22--A114)
2
Machine Model (per EIA/JESD22--A115)
A
Charge Device Model (per JESD22--C101)
IV
Table 4. Moisture Sensitivity Level
Test Methodology
Per JESD22--A113, IPC/JEDEC J--STD--020
Rating
Package Peak Temperature
Unit
3
260
C
Table 5. Electrical Characteristics (TA = 25C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
Zero Gate Voltage Drain Leakage Current
(VDS = 105 Vdc, VGS = 0 Vdc)
IDSS
—
—
10
Adc
Zero Gate Voltage Drain Leakage Current
(VDS = 55 Vdc, VGS = 0 Vdc)
IDSS
—
—
1
Adc
Gate--Source Leakage Current
(VGS = 5 Vdc, VDS = 0 Vdc)
IGSS
—
—
1
Adc
Gate Threshold Voltage (4)
(VDS = 10 Vdc, ID = 96 Adc)
VGS(th)
1.3
1.8
2.3
Vdc
Gate Quiescent Voltage (5)
(VDS = 48 Vdc, IDQ(A+B) = 1000 mAdc)
VGS(Q)
—
2.5
—
Vdc
Fixture Gate Quiescent Voltage (5)
(VDD = 48 Vdc, IDQ(A+B) = 1000 mAdc, Measured in Functional Test)
VGG(Q)
4.0
5.0
6.0
Vdc
Drain--Source On--Voltage (4)
(VGS = 10 Vdc, ID = 0.96 Adc)
VDS(on)
0.1
0.21
0.5
Vdc
Characteristic
Off Characteristics (4)
On Characteristics
1.
2.
3.
4.
5.
Continuous use at maximum temperature will affect MTTF.
MTTF calculator available at http://www.freescale.com/rf/calculators.
Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.freescale.com/rf and search for AN1955.
Each side of device measured separately.
Side A and Side B are tied together for this measurement.
A2T09VD250NR1
2
RF Device Data
Freescale Semiconductor, Inc.
Table 5. Electrical Characteristics (TA = 25C unless otherwise noted) (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
Functional Tests (1) (In Freescale Test Fixture, 50 ohm system) VDD = 48 Vdc, IDQ(A+B) = 1000 mA, Pout = 65 W Avg., f = 920 MHz,
Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF. ACPR measured in 3.84 MHz
Channel Bandwidth @ 5 MHz Offset.
Power Gain
Gps
21.0
22.5
24.0
dB
Drain Efficiency
D
31.0
34.8
—
%
Output Peak--to--Average Ratio @ 0.01% Probability on CCDF
Adjacent Channel Power Ratio
PAR
6.8
7.5
—
dB
ACPR
—
–34.4
–31.5
dBc
IRL
—
–18
–10
dB
Input Return Loss
Load Mismatch (In Freescale Test Fixture, 50 ohm system) IDQ(A+B) = 1000 mA, f = 940 MHz, 12 sec(on), 10% Duty Cycle
VSWR 10:1 at 52 Vdc, 363 W Pulsed CW Output Power
(3 dB Input Overdrive from 308 W Pulsed CW Rated Power)
No Device Degradation
Typical Performance (In Freescale Test Fixture, 50 ohm system) VDD = 48 Vdc, IDQ(A+B) = 1000 mA, 920–960 MHz Bandwidth
Pout @ 1 dB Compression Point, CW
P1dB
—
240
—
W
Pout @ 3 dB Compression Point (2)
P3dB
—
326
—
W
—
19
—
VBWres
—
90
—
MHz
Gain Flatness in 40 MHz Bandwidth @ Pout = 65 W Avg.
GF
—
0.3
—
dB
Gain Variation over Temperature
(–30C to +85C)
G
—
0.013
—
dB/C
P1dB
—
0.007
—
dB/C
AM/PM
(Maximum value measured at the P3dB compression point across
the 920–960 MHz frequency range)
VBW Resonance Point
(IMD Third Order Intermodulation Inflection Point)
Output Power Variation over Temperature
(–30C to +85C)
Table 6. Ordering Information
Device
A2T09VD250NR1
Tape and Reel Information
R1 Suffix = 500 Units, 44 mm Tape Width, 13--inch Reel
Package
TO--270WB--6A
1. Part internally input matched.
2. P3dB = Pavg + 7.0 dB where Pavg is the average output power measured using an unclipped W--CDMA single--carrier input signal where
output PAR is compressed to 7.0 dB @ 0.01% probability on CCDF.
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
3
D69443
A2T09VD250N
Rev. 0
VGG
R1
C16
R2
R3
C5
C8
C20
C7
C23*
C3
C10*
CUT OUT AREA
C1
C4
C2
C9
VDD
C18
C6
C11*
C15
C13
C14
C12
C22*
C21
R4
R6
C17
R5
C19
*C10, C11, C22 and C23 are mounted vertically.
Figure 2. A2T09VD250NR1 Test Circuit Component Layout
Table 7. A2T09VD250NR1 Test Circuit Component Designations and Values
Part
Description
Part Number
Manufacturer
C1
3.3 pF Chip Capacitor
ATC800B3R3BT500XT
ATC
C2
2.7 pF Chip Capacitor
ATC800B2R7BT500XT
ATC
C3, C4
4.3 pF Chip Capacitors
ATC800B4R3BT500XT
ATC
C5, C6, C7, C15, C16, C17
47 pF Chip Capacitors
ATC800B470JT500XT
ATC
C8, C9
1 F Chip Capacitors
C3216X7R2A105M160AA
TDK
C10, C11
12 pF Chip Capacitors
ATC800B120JT500XT
ATC
C12
5.1 pF Chip Capacitor
ATC800B5R1BT500XT
ATC
C13
4.7 pF Chip Capacitor
ATC800B4R7BT500XT
ATC
C14
5.6 pF Chip Capacitor
ATC800B5R6BT500XT
ATC
C18, C19
10 F Chip Capacitors
C5750X7S2A106M230KB
TDK
C20, C21
220 F, 100 V Electrolytic Capacitors
EEVFK2A221M
Panasonic
C22, C23
1.7 pF Chip Capacitor
ATC800B1R7BT500XT
ATC
R1, R2, R5, R6
1 k, 1/4 W Chip Resistors
WCR1206-1KF
Welwyn
R3, R4
10 , 1/4 W Chip Resistors
WCR1206-10RF
Welwyn
PCB
Rogers RO4350B, 0.020, r = 3.66
D69443
MTL
A2T09VD250NR1
4
RF Device Data
Freescale Semiconductor, Inc.
TYPICAL CHARACTERISTICS
30
24
25
23
–33
5
–34
0
Gps
PARC
22
ACPR
21
20
–35
–36
IRL
19
18
820
840
860
–37
880
900
920
f, FREQUENCY (MHz)
940
960
–38
980
–5
–10
–15
–20
–2
–2.2
–2.4
–2.6
–2.8
PARC (dB)
35
IRL, INPUT RETURN LOSS (dB)
40
ACPR (dBc)
Gps, POWER GAIN (dB)
VDD = 48 Vdc, Pout = 65 W (Avg.), IDQ(A+B) = 1000 mA
27 Single--Carrier
W--CDMA, 3.84 MHz Channel Bandwidth
26 Input Signal PAR = 9.9 dB @ 0.01%
D
Probability on CCDF
25
D, DRAIN
EFFICIENCY (%)
45
28
–3
IMD, INTERMODULATION DISTORTION (dBc)
Figure 3. Single--Carrier Output Peak--to--Average Ratio Compression
(PARC) Broadband Performance @ Pout = 65 Watts Avg.
–10
VDD = 48 Vdc, Pout = 130 W (PEP)
IDQ(A+B) = 1000 mA, Two--Tone Measurements
(f1 + f2)/2 = Center Frequency of 940 MHz
–20
IM3--U
–30
IM3--L
–40
IM5--U
IM5--L
IM7--U
–50
IM7--L
–60
1
10
100
200
TWO--TONE SPACING (MHz)
23
0
22.5
22
21.5
21
20.5
VDD = 48 Vdc, IDQ(A+B) = 1000 mA
f = 940 MHz, Single--Carrier W--CDMA
70
–25
60
–30
ACPR
–1
–2
–1 dB = 38.3 W
–5
20
–2 dB = 54.5 W
40
Gps
–3 dB = 72.7 W
–3
–4
50
D
3.84 MHz Channel Bandwidth
Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF
40
60
80
Pout, OUTPUT POWER (WATTS)
30
–40
–45
20
–50
10
120
–55
PARC
100
–35
ACPR (dBc)
1
D DRAIN EFFICIENCY (%)
23.5
OUTPUT COMPRESSION AT 0.01%
PROBABILITY ON CCDF (dB)
Gps, POWER GAIN (dB)
Figure 4. Intermodulation Distortion Products
versus Two--Tone Spacing
Figure 5. Output Peak--to--Average Ratio
Compression (PARC) versus Output Power
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
5
TYPICAL CHARACTERISTICS
Gps, POWER GAIN (dB)
24
22
940 MHz
20
14
30
ACPR
20
10
920 MHz
960 MHz 940 MHz
1
–10
40
920 MHz
16
50
960 MHz
940 MHz
960 MHz
18
0
D
Gps
920 MHz
60
10
Pout, OUTPUT POWER (WATTS) AVG.
100
0
200
–20
–30
–40
ACPR (dBc)
VDD = 48 Vdc, IDQ(A+B) = 1000 mA, Single--Carrier W--CDMA
3.84 MHz Channel Bandwidth, Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF
D, DRAIN EFFICIENCY (%)
26
–50
–60
Figure 6. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
26
5
GAIN (dB)
22
20
0
Gain
–5
VDD = 28 Vdc
Pin = 0 dBm
IDQ(A+B) = 1000 mA
–10
18
–15
16
14
600
IRL (dB)
24
–20
IRL
700
800
900
1000 1100
f, FREQUENCY (MHz)
1200
1300
–25
1400
Figure 7. Broadband Frequency Response
A2T09VD250NR1
6
RF Device Data
Freescale Semiconductor, Inc.
Table 8. Single Side Load Pull Performance — Maximum Power Tuning
VDD = 48 Vdc, IDQ = 500 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
920
2.52 – j4.76
2.19 + j4.75
940
2.88 – j5.34
2.22 + j5.10
960
3.53 – j5.36
2.36 + j5.64
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
3.04 + j0.55
21.4
52.5
178
61.2
–14
2.93 + j0.37
21.4
52.5
178
61.8
–14
2.87 + j0.07
21.3
52.4
174
60.3
–12
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
920
2.52 – j4.76
2.01 + j5.09
3.37 + j0.34
19.4
53.2
208
62.3
–20
940
2.88 – j5.34
2.06 + j5.48
3.24 + j0.13
19.3
53.2
207
62.2
–19
960
3.53 – j5.36
2.19 + j6.04
3.19 – j0.10
19.2
53.1
204
61.5
–18
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 9. Single Side Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 48 Vdc, IDQ = 500 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
920
2.52 – j4.76
1.87 + j4.79
2.65 + j2.94
23.8
50.8
121
71.4
–20
940
2.88 – j5.34
1.85 + j5.18
2.40 + j2.86
24.0
50.4
111
71.9
–21
960
3.53 – j5.36
1.99 + j5.66
2.32 + j2.45
23.7
50.5
112
70.9
–19
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
3.13 + j2.50
21.3
52.1
162
72.0
–26
1.83 + j5.50
2.80 + j2.46
21.5
51.7
149
72.1
–26
1.95 + j6.05
2.65 + j2.16
21.4
51.7
147
71.4
–25
f
(MHz)
Zsource
()
Zin
()
920
2.52 – j4.76
1.83 + j5.10
940
2.88 – j5.34
960
3.53 – j5.36
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
7
P1dB – TYPICAL LOAD PULL CONTOURS — 940 MHz
5
5
48.5
50
3
50.5
E
51
2
51.5
1
52
P
0
58
4
IMAGINARY ()
IMAGINARY ()
4
49.5
49
56
60
3
E
70
2
68
1
66
64
62
P
0
60
58
56
–1
–2
–1
50
1
1.5
2
2.5
3
3.5
4
REAL ()
4.5
5
–2
6
5.5
Figure 8. P1dB Load Pull Output Power Contours (dBm)
5
4
4
IMAGINARY ()
E
23.5
IMAGINARY ()
24
24.5
23
2
22.5
1
P
0
22
21.5
21
1
1.5
2
2.5
3
3.5
4
REAL ()
2
4.5
3
2.5
3.5
4
REAL ()
4.5
5
5.5
6
–12
–24
3
E
–22
2
–20
1
–16
–18
–14
P
0
–1
–2
1.5
Figure 9. P1dB Load Pull Efficiency Contours (%)
5
3
1
–1
5
5.5
6
Figure 10. P1dB Load Pull Gain Contours (dB)
NOTE:
–2
1
1.5
2
2.5
3
3.5
4
REAL ()
4.5
5
5.5
6
Figure 11. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T09VD250NR1
8
RF Device Data
Freescale Semiconductor, Inc.
P3dB – TYPICAL LOAD PULL CONTOURS — 940 MHz
5
5
49
49.5
50
50.5
51.5
3
52
E
2
52.5
1
0
51.5
P
–1
–2
53
1.5
2
3
2.5
3.5
4
REAL ()
4.5
5
68
4
64
62
60
58
56
1
2
IMAGINARY ()
20.5
E
20
1
19.5
P
0
2.5
3
3.5
4
REAL ()
4.5
5
5.5
6
Figure 14. P3dB Load Pull Gain Contours (dB)
NOTE:
3.5
4
REAL ()
4.5
5
5.5
6
–32
–26
–24
–16
–20
–28
3
–30
–18
–22
E
2
1
P
–1
18.5
2
3
2.5
0
19
–1
2
4
22
22.5
1.5
Figure 13. P3dB Load Pull Efficiency Contours (%)
21
3
1.5
66
P
5
21.5
1
70
1
–2
6
5.5
5
IMAGINARY ()
E
2
–1
Figure 12. P3dB Load Pull Output Power Contours (dBm)
–2
3
0
51
1
56
4
51
IMAGINARY ()
IMAGINARY ()
4
–2
–16
1
1.5
2
2.5
3
3.5
4
REAL ()
4.5
5
5.5
6
Figure 15. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
9
D69443
A2T09VD250N
Rev. 0
R1
VGG
R2
R3
C5
C8
VDD
C18
C16
C20
C7
C22*
CUT OUT AREA
C3
C1
C4
C2
C15
C13
C10*
C11*
C14
C12
C23*
C9
C6
C21
R4
R6
C17
C19
R5
*C10, C11, C22 and C23 are mounted vertically.
Figure 16. A2T09VD250NR1 Test Circuit Component Layout — 790–821 MHz
Table 10. A2T09VD250NR1 Test Circuit Component Designations and Values — 790–821 MHz
Part
Description
Part Number
Manufacturer
C1
3.3 pF Chip Capacitor
ATC800B3R3BT500XT
ATC
C2
3.9 pF Chip Capacitor
ATC800B3R9BT500XT
ATC
C3, C4, C13, C14
6.8 pF Chip Capacitors
ATC800B6R8BT500XT
ATC
C5, C6, C7, C15, C16, C17
47 pF Chip Capacitors
ATC800B470JT500XT
ATC
C8, C9
1 F Chip Capacitors
C3216X7R2A105M160AA
TDK
C10, C11
18 pF Chip Capacitors
ATC800B180JT500XT
ATC
C12
6.2 pF Chip Capacitor
ATC800B6R2BT500XT
ATC
C18, C19
10 F Chip Capacitors
C5750X7S2A106M230KB
TDK
C20, C21
220 F, 100 V Electrolytic Capacitors
EEVFK2A221M
Panasonic
C22, C23
0.5 pF Chip Capacitors
ATC800B0R5BT500XT
ATC
R1, R2, R5, R6
1 k, 1/4 W Chip Resistors
WCR1206-1KF
Welwyn
R3, R4
10 , 1/4 W Chip Resistors
WCR1206-10RF
Welwyn
PCB
Rogers RO4350B, 0.020, r = 3.66
D69443
MTL
A2T09VD250NR1
10
RF Device Data
Freescale Semiconductor, Inc.
TYPICAL CHARACTERISTICS — 790–821 MHz
22
21
30
D
Gps
25
ACPR
20
19
–32
0
–33
–4
–34
18
PARC
17
16
760
–36
Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF
IRL
780
–35
800
820
840 860 880 900
f, FREQUENCY (MHz)
920
–12
–16
–20
–37
960
940
–8
–1.5
–2
–2.5
–3
–3.5
PARC (dB)
23
IRL, INPUT RETURN LOSS (dB)
Gps, POWER GAIN (dB)
24
ACPR (dBc)
25
D, DRAIN
EFFICIENCY (%)
45
VDD = 48 Vdc, Pout = 65 W (Avg.), IDQ(A+B) = 1000 mA
Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth 40
35
26
–4
Figure 17. Single--Carrier Output Peak--to--Average Ratio
Compression (PARC) Broadband Performance @ Pout = 65 Watts Avg.
Gps, POWER GAIN (dB)
24
22
Gps
806 MHz
821 MHz
790 MHz
18
30
20
10
Pout, OUTPUT POWER (WATTS) AVG.
1
–10
ACPR
10
821 MHz 806 MHz
14
50
40
790 MHz
16
0
D
790 MHz 821 MHz 806 MHz
20
60
100
0
200
–20
–30
–40
ACPR (dBc)
VDD = 48 Vdc, IDQ(A+B) = 1000 mA, Single--Carrier W--CDMA
3.84 MHz Channel Bandwidth, Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF
D, DRAIN EFFICIENCY (%)
26
–50
–60
Figure 18. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
Gain
GAIN (dB)
22
5
VDD = 48 Vdc
Pin = 0 dBm
0
IDQ(A+B) = 1000 mA
20
–5
18
–10
16
–15
14
IRL (dB)
24
–20
IRL
12
500
600
700
800
900
1000
f, FREQUENCY (MHz)
1100
1200
–25
1300
Figure 19. Broadband Frequency Response
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
11
Table 11. Single Side Load Pull Performance — Maximum Power Tuning
VDD = 48 Vdc, IDQ = 501 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
790
3.03 – j2.71
2.16 + j2.10
806
3.30 – j2.82
2.16 + j2.40
821
3.27 – j3.34
2.10 + j2.70
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
3.38 + j1.69
21.3
52.8
193
64.9
–12
3.29 + j1.70
21.3
52.7
187
63.4
–11
3.34 + j1.67
21.4
52.7
185
63.5
–12
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
790
3.03 – j2.71
1.99 + j2.30
3.58 + j1.49
19.2
53.4
221
65.9
–15
806
3.30 – j2.82
2.00 + j2.62
3.66 + j1.41
19.2
53.4
217
64.6
–15
821
3.27 – j3.34
1.94 + j2.93
3.67 + j1.47
19.3
53.3
215
65.7
–16
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 12. Single Side Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 48 Vdc, IDQ = 501 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
790
3.03 – j2.71
1.81 + j2.34
3.66 + j5.16
24.0
50.5
113
75.8
–17
806
3.30 – j2.82
1.82 + j2.60
3.53 + j4.98
24.0
50.6
114
74.9
–17
821
3.27 – j3.34
1.86 + j2.84
3.63 + j4.24
23.5
51.2
133
74.0
–15
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
4.26 + j3.66
21.0
52.5
177
75.2
–19
1.84 + j2.75
4.19 + j4.15
21.3
52.1
161
74.3
–20
1.81 + j3.04
4.12 + j3.87
21.2
52.2
166
73.8
–20
f
(MHz)
Zsource
()
Zin
()
790
3.03 – j2.71
1.86 + j2.40
806
3.30 – j2.82
821
3.27 – j3.34
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T09VD250NR1
12
RF Device Data
Freescale Semiconductor, Inc.
P1dB – TYPICAL LOAD PULL CONTOURS — 806 MHz
7
7
6
IMAGINARY ()
5
49.5
50
50.5
E
51.5
3
52
2
P
52.5
1
1
2
3
4
REAL ()
6
5
70
68
3
66
2
–1
7
P
64
60
62
58
2
1
3
4
REAL ()
6
5
7
Figure 21. P1dB Load Pull Efficiency Contours (%)
7
7
24.5
5
23.5
24
23
4
22.5
3
22
P
21.5
1
2
3
4
REAL ()
–22
–16
5
–14
E
–12
4
3
2
P
–10
1
21
0
1
–20
5
E
2
–18
–24
6
IMAGINARY ()
25
6
IMAGINARY ()
72
4
0
Figure 20. P1dB Load Pull Output Power Contours (dBm)
–1
E
1
0
–1
74
5
51
4
62 60
6
IMAGINARY ()
49
48.5
0
6
7
Figure 22. P1dB Load Pull Gain Contours (dB)
NOTE:
–1
1
2
3
4
REAL ()
5
6
7
Figure 23. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
13
P3dB – TYPICAL CARRIER LOAD PULL CONTOURS — 806 MHz
8
49.5
7
4
IMAGINARY ()
51.5
E
52
3
53
52.5
2
P
1
0
4
3
5
REAL ()
6
7
70
66
68
2
–2
8
64
62
60
P
58
3
2
4
5
REAL ()
6
7
8
Figure 25. P3dB Load Pull Efficiency Contours (%)
8
8
22.5
6
22
5
20.5
3
20
2
19.5
P
1
3
4
5
REAL ()
6
–26
4
–22
–16
E
–14
3
–12
2
P
0
18.5
–1
–20
–24
5
1
19
0
2
–18
6
21
E
4
7
21.5
IMAGINARY ()
7
IMAGINARY ()
72
3
–1
Figure 24. P3dB Load Pull Output Power Contours (dBm)
–2
E
4
0
51 51.5
2
5
1
52
–1
58
6
51
5
IMAGINARY ()
7
50.5
6
–2
8
50
–10
–1
8
7
Figure 26. P3dB Load Pull Gain Contours (dB)
NOTE:
–2
2
3
4
5
REAL ()
6
7
8
Figure 27. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T09VD250NR1
14
RF Device Data
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
15
A2T09VD250NR1
16
RF Device Data
Freescale Semiconductor, Inc.
A2T09VD250NR1
RF Device Data
Freescale Semiconductor, Inc.
17
PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS
Refer to the following resources to aid your design process.
Application Notes
AN1955: Thermal Measurement Methodology of RF Power Amplifiers
Engineering Bulletins
EB212: Using Data Sheet Impedances for RF LDMOS Devices
Software
Electromigration MTTF Calculator
RF High Power Model
s2p File
Development Tools
Printed Circuit Boards
To Download Resources Specific to a Given Part Number:
1. Go to http://www.freescale.com/rf
2. Search by part number
3. Click part number link
4. Choose the desired resource from the drop down menu
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
0
Aug. 2015
Description
Initial Release of Data Sheet
A2T09VD250NR1
18
RF Device Data
Freescale Semiconductor, Inc.
How to Reach Us:
Home Page:
freescale.com
Web Support:
freescale.com/support
Information in this document is provided solely to enable system and software
implementers to use Freescale products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based on the
information in this document.
Freescale reserves the right to make changes without further notice to any products
herein. Freescale makes no warranty, representation, or guarantee regarding the
suitability of its products for any particular purpose, nor does Freescale assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in Freescale data sheets and/or
specifications can and do vary in different applications, and actual performance may
vary over time. All operating parameters, including “typicals,” must be validated for
each customer application by customer’s technical experts. Freescale does not convey
any license under its patent rights nor the rights of others. Freescale sells products
pursuant to standard terms and conditions of sale, which can be found at the following
address: freescale.com/SalesTermsandConditions.
Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast is a trademark of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners.
E 2015 Freescale Semiconductor, Inc.
A2T09VD250NR1
Document
Number:
RF
Device
Data A2T09VD250N
Rev. 0, 8/2015Semiconductor, Inc.
Freescale
19
工商网监
湘ICP备2023018690号
