MC100ES6226AC

MOTOROLA Freescale Semiconductor, Inc.Order Number: MC100ES6226/D SEMICONDUCTOR TECHNICAL DATA 2.5/3.3V Differential LVPECL 1:9 Clock Distribution Buffer Rev 1, 12/2001 MC100ES6226 Freescale Semiconductor, Inc... and Clock Divider The Motorola MC100ES6226 is a bipolar monolithic differential clock distribution buffer and clock divider. Designed for most demanding clock distribution systems, the MC100ES6226 supports various applications that require a large number of outputs to drive precisely aligned clock signals. Using SiGe technology and a fully differential architecture, the device offers superior digitial signal characteristics and very low clock skew error. Target applications for this clock driver are high performance c l oc k dis t r ibut io n s y s te ms fo r c o m p u ti n g , netw ork i ng and telecommunication systems. 2.5V/3.3V DIFFERENTIAL LVPECL 1:9 CLOCK DISTRIBUTION BUFFER AND CLOCK DIVIDER Features: Fully differential architecture from input to all outputs • • • • • • • • • • SiGe technology supports near-zero output skew Selectable 1:1 or 1:2 frequency outputs LVPECL compatible differential clock inputs and outputs LVCMOS compatible control inputs Single 3.3V or 2.5V supply Max. 35 ps maximum output skew (within output bank) Max. 50 ps maximum device skew Supports DC operation and up to 3 GHz (typ.) clock signals Synchronous output enable eliminating output runt pulse generation and metastability • Standard 32 lead LQFP package FA SUFFIX 32–LEAD LQFP PACKAGE CASE 873A • Industrial temperature range Functional Description MC100ES6226 is designed for very skew critical differential clock distribution systems and supports clock frequencies from DC up to 3.0 GHz. Typical applications for the MC100ES6226 are primary clock distribution systems on backplanes of high-performance computer, networking and telecommunication systems, as well as on-board clocking of OC-3, OC-12 and OC-48 speed communication systems. The MC100ES6226 can be operated from a 3.3V or 2.5V positive supply without the requirement of a negative supply line. Each of the output banks of three differential clock output pairs may be independently configured to distribute the input frequency or half of the input frequency. The FSEL0 and FSEL1 clock frequency selects are asychronous control inputs. Any changes of the control inputs require a MR pulse for resynchronization of the ÷2 outputs.  Motorola, Inc. 2001 For More Information On This Product, 1 Go to: www.freescale.com Freescale Semiconductor, Inc. MC100ES6226 Bank A VCC QA0 QA0 QA1 QA1 QA2 QA2 ÷1 CLK CLK ÷2 Bank B QB0 QB0 QB1 QB1 QB2 QB2 MR Freescale Semiconductor, Inc... FSEL0 FSEL1 Bank C QC0 QC0 QC1 QC1 QC2 QC2 Sync OE QB0 QB0 VCC QB1 QB1 QB2 QB2 VCC Figure 1. MC100ES6226 Logic Diagram 24 23 22 21 20 19 18 17 QA2 25 16 QC0 QA2 26 15 QC0 VCC 27 14 QC1 QA1 28 13 QC1 MC100ES6226 QA0 31 10 QC2 VCC 32 9 VCC 1 2 3 4 5 6 7 8 MR QC2 OE 11 VCC 30 CLK QA0 CLK VCC GND 12 FSEL1 29 FSEL0 QA1 Figure 2. 32–Lead Package Pinout (Top View) MOTOROLA For More Information On This Product, 2 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MC100ES6226 TABLE 1: PIN CONFIGURATION Freescale Semiconductor, Inc... Pin I/O Type Function CLK, CLK Input LVPECL Differential reference clock signal input OE Input LVCMOS Output enable MR Input LVCMOS Device reset FSEL0, FSEL1 Input LVCMOS Output frequency divider select QA[0-2], QA[0-2] QB[0-2], QB[0-2] QC[0-2], QC[0-2] Output LVPECL Differential clock outputs (banks A, B and C) GND Supply GND Negative power supply VCC Supply VCC Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation TABLE 2: FUNCTION TABLE Control Default 0 0 Qx[0-2], Qx[0-2] are active. Deassertion of OE can be asynchronous to the reference clock without generation of output runt pulses Qx[0-2] = L, Qx[0-2] =H (outputs disabled). Assertion of OE can be asynchronous to the reference clock without generation of output runt pulses MR 0 Normal operation Device reset (asynchronous) FSEL0, FSEL1 00 See Following Table OE 1 TABLE 3: Output Frequency Select Control FSEL0 0 FSEL1 0 1 1 0 1 1 0 QC0 to QC2 QA0 to QA2 fQA0:2 = fCLK fQA0:2 = fCLK QB0 to QB2 fQB0:2 = fCLK fQB0:2 = fCLK fQC0:2 = fCLK fQC0:2 = fCLK ÷ 2 fQA0:2 = fCLK fQA0:2 = fCLK ÷ 2 fQB0:2 = fCLK ÷ 2 fQB0:2 = fCLK ÷ 2 fQC0:2 = fCLK ÷ 2 fQC0:2 = fCLK ÷ 2 TABLE 4: ABSOLUTE MAXIMUM RATINGSa Symbol Min Max Unit VCC Supply Voltage -0.3 3.6 V VIN DC Input Voltage -0.3 VCC+0.3 V DC Output Voltage -0.3 VCC+0.3 V DC Input Current ±20 mA DC Output Current ±50 mA 125 °C VOUT IIN IOUT TS Characteristics Storage temperature -65 Condition a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. TIMING SOLUTIONS For More Information On This Product, 3 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC100ES6226 TABLE 5: GENERAL SPECIFICATIONS Symbol Characteristics Min Unit ESD Protection (Machine model) 200 V HBM ESD Protection (Human body model) 2000 V CDM ESD Protection (Charged device model) 1000 V Latch-up immunity 200 mA CIN θJA Freescale Semiconductor, Inc... Max Output termination voltage LU Thermal resistance junction to ambient JESD 51-3, single layer test board θJC Thermal resistance junction to case Operating junction temperatureb (continuous operation) MTBF = 9.1 years 0 Condition V 4.0 JESD 51-6, 2S2P multilayer test board a. b. Typ VCC - 2a VTT MM pF Inputs 83.1 73.3 68.9 63.8 57.4 86.0 75.4 70.9 65.3 59.6 °C/W °C/W °C/W °C/W °C/W Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 59.0 54.4 52.5 50.4 47.8 60.6 55.7 53.8 51.5 48.8 °C/W °C/W °C/W °C/W °C/W Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 23.0 26.3 °C/W MIL-SPEC 883E Method 1012.1 110 °C Output termination voltage VTT = 0V for VCC = 2.5V operation is supported but the power consumption of the device will increase. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110°C junction temperature allowing the MC100ES6226 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES6226 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. MOTOROLA For More Information On This Product, 4 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MC100ES6226 TABLE 6: DC CHARACTERISTICS (VCC = 3.3V ± 5% and 2.5V ± 5%, TJ = 0°C to +110°C)a Symbol Characteristics Min Typ Max Unit 0.8 0.7 V Condition LVCMOS control inputs (OE, FSEL0, FSEL1, MR) VIL Input voltage low VIH Input voltage high IIN Input Currentb VCC = 3.3 V VCC = 2.5 V VCC = 3.3 V VCC = 2.5 V 2.2 1.7 V ±150 µA VIN = VCC or VIN = GND LVPECL clock inputs (CLK, CLK)c Freescale Semiconductor, Inc... VPP VCMR DC differential input voltaged 0.1 1.3 V Differential operation Differential cross point voltagee 1.0 VCC-0.3 TBD V Differential operation ±150 µA VIN = TBD or VIN = TBD VCC-0.8 VCC-1.4 V Termination 50 V Termination 50 VIH VIL Input high voltage TBD Input low voltage TBD IIN Input Current TBD LVPECL clock outputs (QA[2:0], QB[2:0], QC[2:0]) VOH VOL Output High Voltage VCC-1.1 VCC-1.8 Output Low Voltage W to VTT W to VTT Supply current a. b. c. d. e. IGND Maximum Quiescent Supply Current without output termination current 65 110 mA GND pin ICC Maximum Quiescent Supply Current with output termination current 325 400 mA All VCC Pins AC characterisitics are design targets and pending characterization. Input have internal pullup/pulldown resistors which affect the input current. Clock inputs driven by LVPECL compatible signals. VPP is the minimum differential input voltage swing required to maintain AC characteristic. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. TIMING SOLUTIONS For More Information On This Product, 5 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC100ES6226 TABLE 7: AC CHARACTERISTICS (VCC = 3.3V ± 5% and 2.5V ± 5%, TJ = 0°C to +110°C)a b Symbol VPP VCMR VX,OUT VO(P-P) Freescale Semiconductor, Inc... fCLK tPD Characteristics Differential input voltagec (peak-to-peak) Differential input crosspoint voltaged Differential output crosspoint voltage Min Typ Max Unit 0.2 0.3 1.3 V VCC-0.3 VCC-1.1 V 0.72 0.55 0.37 0.95 0.95 0.95 3000e V V V MHz 500 800 ps Differential 11 12 4 25 25 20 60 ps ps ps ps Differential ps Differential 1.0 VCC-1.45 Differential output voltage (peak-to-peak) fO < 300 MHz fO < 1.5 GHz fO < 2.7 GHz Input Frequency 0.45 0.3 TBD Propagation Delay CLK to Qx[] 475 0 tsk(O) Output-to-output skew (within QA[2:0]) (within QB[2:0]) (within QC[2:0]) (within device) tsk(PP) tJIT(CC) Output-to-output skew (part-to-part) 325 Output cycle-to-cycle jitter single frequency configuration ÷1/÷2 frequency configuration TBD TBD DCO Output duty cycle tr, tf tPDLf tPLDg a. b. c. d. e. f. g. V FSEL0 = FSEL1 FSEL0 ≠ FSEL1 Qx = ÷1, fO < 300 MHz Qx = ÷1, fO > 300 MHz 48 45 50 50 52 55 % % Qx = ÷2, fO < 300 MHz Qx = ÷2, fO > 300 MHz 49 47.5 50 50 51 52.5 % % Output Rise/Fall Time Condition DCfref= 50% 0.05 200 ns 20% to 80% Output disable time 2.5⋅T + tPD 4.5⋅T + tPD ns T=CLK period Output enable time 3⋅T + tPD 5⋅T + tPD ns T=CLK period AC characterisitics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50Ω to VTT. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. The MC100ES6226 is fully operational up to 3.0 GHz and is characterized up to 2.7 GHz. Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high). Propagation delay OE assertion to output enabled (active). CLK CLK 50% OE tPDL (OE to Qx) tPLD (OE to Qx) Qx Qx Outputs disabled Figure 3. MC100ES6226 output disable/enable timing MOTOROLA For More Information On This Product, 6 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MC100ES6226 Differential Pulse Generator Z = 50 ZO = 50Ω ZO = 50Ω W RT = 50Ω DUT MC100ES6226 RT = 50Ω VTT VTT Freescale Semiconductor, Inc... Figure 4. MC100ES6226 AC test reference APPLICATIONS INFORMATION Maintaining Lowest Device Skew The MC100ES6226 guarantees low output-to-output bank skew of 35 ps and a part-to-part skew of max. TBD ps. To ensure low skew clock signals in the application, both outputs of any differential output pair need to be terminated identically, even if only one output is used. When fewer than all nine output pairs are used, identical termination of all output pairs within the output bank is recommended. If an entire output bank is not used, it is recommended to leave all of these outputs open and unterminated. This will reduce the device power consumption while maintaining minimum output skew. Power Supply Bypassing The MC100ES6226 is a mixed analog/digital product. The differential architecture of the MC100ES6226 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VCC pins should be bypassed by high-frequency ceramic capacitors connected TIMING SOLUTIONS to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth. VCC VCC 33...100 nF 0.1 nF MC100ES6226 Figure 5. VCC Power Supply Bypass For More Information On This Product, 7 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC100ES6226 Freescale Semiconductor, Inc... NOTES MOTOROLA For More Information On This Product, 8 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MC100ES6226 Freescale Semiconductor, Inc... NOTES TIMING SOLUTIONS For More Information On This Product, 9 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC100ES6226 Freescale Semiconductor, Inc... NOTES MOTOROLA For More Information On This Product, 10 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MC100ES6226 OUTLINE DIMENSIONS A –T–, –U–, –Z– FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A 4X A1 32 0.20 (0.008) AB T–U Z 25 1 –U– –T– B V AE B1 DETAIL Y 17 8 V1 AE DETAIL Y 9 4X –Z– 9 0.20 (0.008) AC T–U Z S1 S DETAIL AD G –AB– 0.10 (0.004) AC AC T–U Z –AC– BASE METAL ÉÉ ÉÉ ÉÉ ÉÉ F 8X M_ R J M N D 0.20 (0.008) SEATING PLANE SECTION AE–AE H W K X DETAIL AD TIMING SOLUTIONS Q_ 0.250 (0.010) C E GAUGE PLANE Freescale Semiconductor, Inc... P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED AT DATUM PLANE –AB–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –AC–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –AB–. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X For More Information On This Product, 11 Go to: www.freescale.com MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MC100ES6226 Motorola reserves the right to make changes without further notice to any products herein. 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MOTOROLA and the logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. E Motorola, Inc. 2001. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852–26668334 Technical Information Center: 1–800–521–6274 HOME PAGE: http://www.motorola.com/semiconductors/ MOTOROLA ◊ More Information For On This Product, 12 Go to: www.freescale.com MC100ES6226/D TIMING SOLUTIONS