ADP3120A
Dual Bootstrapped, 12 V
MOSFET Driver with Output
Disable
The ADP3120A is a single Phase 12 V MOSFET gate drivers
optimized to drive the gates of both high−side and low−side power
MOSFETs in a synchronous buck converter. The high−side and
low−side driver is capable of driving a 3000 pF load with a 45 ns
propagation delay and a 25 ns transition time.
With a wide operating voltage range, high or low side MOSFET
gate drive voltage can be optimized for the best efficiency. Internal
adaptive nonoverlap circuitry further reduces switching losses by
preventing simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate VBST voltages as
high as 35 V, with transient voltages as high as 40 V. Both gate outputs
can be driven low by applying a low logic level to the Output Disable
(OD) pin. An Undervoltage Lockout function ensures that both driver
outputs are low when the supply voltage is low, and a Thermal
Shutdown function provides the IC with overtemperature protection.
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MARKING
DIAGRAMS
8
8
1
1
•
All−In−One Synchronous Buck Driver
Bootstrapped High−Side Drive
One PWM Signal Generates Both Drives
Anticross Conduction Protection Circuitry
OD for Disabling the Driver Outputs Meets CPU VR Requirement
when Used with Patented FlexModet Controller
These are Pb−Free Devices
1
A
L
Y
W
G
8
L3C
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
BST
1
8
DRVH
IN
OD
SWN
PGND
VCC
DRVL
Applications
1
• Multiphase Desktop CPU Supplies
• Single−Supply Synchronous Buck Converters
1
DFN8
MN SUFFIX
CASE 506BJ
Features
•
•
•
•
•
3120A
ALYW
G
SO−8
D SUFFIX
CASE 751
8
BST
IN
DRVH
SWN
OD
PGND
VCC
DRVL
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
ADP3120AJRZ
SO−8
(Pb−Free)
98 Units / Rail
ADP3120AJRZ−RL
SO−8
(Pb−Free)
2500 / Tape &
Reel
ADP3120AJCPZ−RL
DFN8
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2012
August, 2018 − Rev. 5
1
Publication Order Number:
ADP3120A/D
ADP3120A
OD
3
VCC
TSD
1
BST
8
DRVH
7
SWN
4
VCC
5
DRVL
6
PGND
UVLO
IN
2
FALLING
EDGE
DELAY
FALLING
EDGE
DELAY
START
STOP
MONITOR
MONITOR
NON−OVERLAP
TIMERS
MIN DRVL
OFF TIMER
Figure 1. Block Diagram
PIN DESCRIPTION
SO−8
DFN8
Symbol
Description
1
1
BST
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds
this bootstrap voltage for the high−side MOSFET as it is switched. The recommended capacitor value
is between 100 nF and 1.0 mF. An external diode is required with the ADP3120A.
2
2
IN
Logic−Level Input. This pin has primary control of the drive outputs.
3
3
OD
Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.
4
4
VCC
Input Supply. A 1.0 mF ceramic capacitor should be connected from this pin to PGND.
5
5
DRVL
Output drive for the lower MOSFET.
6
6
PGND
Power Ground. Should be closely connected to the source of the lower MOSFET.
7
7
SWN
Switch Node. Connect to the source of the upper MOSFET.
8
8
DRVH
Output drive for the upper MOSFET.
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2
ADP3120A
MAXIMUM RATINGS
Rating
Value
Unit
Operating Ambient Temperature, TA
−20 to 85
°C
Operating Junction Temperature, TJ (Note 1)
−20 to 150
°C
45
123
°C/W
°C/W
7.5
55
°C/W
°C/W
−65 to 150
°C
260 peak
°C
1
−
Package Thermal Resistance: SO−8
Junction−to−Case, RqJC
Junction−to−Ambient, RqJA (2−Layer Board)
Package Thermal Resistance: DFN8 (Note 2)
Junction−to−Case, RqJC (From die to exposed pad)
Junction−to−Ambient, RqJA
Storage Temperature Range, TS
Lead Temperature Soldering (10 sec): Reflow (SMD styles only)
Pb−Free (Note 3)
JEDEC Moisture Sensitivity Level
SO−8 (260 peak profile)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Internally limited by thermal shutdown, 150°C min.
2. 2 layer board, 1 in2 Cu, 1 oz thickness.
3. 60−180 seconds minimum above 237°C.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
MAXIMUM RATINGS
NOTE:
Pin Symbol
Pin Name
VMAX
VMIN
VCC
Main Supply Voltage Input
15 V
−0.3 V
PGND
Ground
0V
0V
BST
Bootstrap Supply Voltage Input
35 V wrt/PGND
40 V < 50 ns wrt/PGND
15 V wrt/SW
−0.3 V wrt/SW
SW
Switching Node
(Bootstrap Supply Return)
35 V
40 V < 50 ns
−5.0 V
−10 V < 200 ns
DRVH
High−Side Driver Output
BST + 0.3 V
−0.3 V wrt/SW
−2.0 V < 200 ns wrt/SW
DRVL
Low−Side Driver Output
VCC + 0.3 V
−0.3 V DC
−5.0 V < 200 ns
IN
DRVH and DRVL Control Input
6.5 V
−0.3 V
OD
Output Disable
6.5 V
−0.3 V
All voltages are with respect to PGND except where noted.
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3
ADP3120A
ELECTRICAL CHARACTERISTICS (Note 4) (VCC = 12 V, TA = −20°C to +85°C, TJ = 0°C to +125°C unless otherwise noted.)
Characteristic
Symbol
Condition
Min
Typ
Max
Unit
Supply
Supply Voltage Range
VCC
−
4.6
−
13.2
V
Supply Current
ISYS
BST = 12 V, IN = 0 V
−
0.7
2.0
mA
Input Voltage High
VOD_HI
−
2.0
−
−
V
Input Voltage Low
VOD_LO
−
−
−
0.8
V
−
−
400
−
mV
No internal pullup or pulldown resistors
−1.0
−
+1.0
mA
OD Input
Hysteresis
Input Current
PWM Input
Input Voltage High
VPWM_HI
−
2.0
−
−
V
Input Voltage Low
VPWM_LO
−
−
−
0.8
V
Hysteresis
−
−
−
400
−
mV
Input Current
−
No internal pullup or pulldown resistors
−1.0
−
+1.0
mA
Output Resistance, Sourcing Current
−
BST − SW = 12 V; TA = −20°C to 85°C
BST − SW = 12 V; TA = 25°C
−
2.2
−
3.9
3.3
W
Output Resistance, Sinking Current
−
BST − SW = 12 V; TA = −20°C to 85°C
BST − SW = 12 V; TA = 25°C
−
1.0
−
2.6
1.8
W
Output Resistance, Unbiased
−
BST − SW = 0 V
−
15
−
kW
trDRVH
tfDRVH
BST − SW = 12 V, CLOAD = 3.0 nF
(See Figure 3)
−
20
11
40
30
ns
tpdhDRVH
BST − SW = 12 V, CLOAD = 3.0 nF
(See Figure 3)
BST − SW = 12 V, CLOAD = 3.0 nF
(See Figure 3)
32
45
70
ns
25
35
20
25
35
55
High−Side Driver
Transition Times
Propagation Delay Times (Note 5)
tpdlDRVH
tpdlOD
tpdhOD
(See Figure 2)
(See Figure 2)
−
SW to PGND
−
15
−
kW
Output Resistance, Sourcing Current
−
TA = −20°C to 85°C
TA = 25°C
−
1.8
−
3.9
3.3
W
Output Resistance, Sinking Current
−
TA = −20°C to 85°C
TA = 25°C
−
1.0
−
2.6
1.8
W
Output Resistance, Unbiased
−
VCC = PGND
−
15
−
kW
trDRVL
tfDRVL
CLOAD = 3.0 nF, (See Figure 3)
−
16
11
35
30
ns
tpdhDRVL
CLOAD = 3.0 nF, (See Figure 3)
(Note 6, tpdhDRVL only)
−
12
35
ns
15
45
20
20
35
35
SW Pulldown Resitance
Low−Side Driver
Transition Times
Propagation Delay Times (Note 5)
tpdlDRVL
tpdlOD
tpdhOD
(See Figure 2)
(See Figure 2)
−
DRVH − SW = 0
−
85
−
ns
UVLO Startup
−
−
3.9
4.3
4.5
V
UVLO Shutdown
−
−
3.7
4.1
4.3
V
Hysteresis
−
−
0.1
0.2
0.4
V
Timeout Delay
Undervoltage Lockout
4. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
5. For propagation delays, “tpdh” refers to the specified signal going high; “tpdl” refers to it going low.
6. Guaranteed by design; not tested in production.
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4
ADP3120A
APPLICATIONS INFORMATION
Theory of Operation
Likewise, when the PWM input pin goes low, DRVH will
go low after the propagation delay (tpdDRVH). The time to
turn off the high−side MOSFET (tfDRVH) is dependent on
the total gate charge of the high−side MOSFET. A timer will
be triggered once the high−side mosfet has stopped
conducting, to delay (tpdhDRVL) the turn on of the
low−side MOSFET
The ADP3120A are single phase MOSFET drivers
designed for driving two N−channel MOSFETs in a
synchronous buck converter topology. The ADP3120A will
operate from 5.0 V or 12 V, but have been optimized for high
current multi−phase buck regulators that convert 12 V rail
directly to the core voltage required by complex logic chips.
A single PWM input signal is all that is required to properly
drive the high−side and the low−side MOSFETs. Each driver
is capable of driving a 3 nF load at frequencies up to 1 MHz.
Power Supply Decoupling
The ADP3120A can source and sink relatively large
currents to the gate pins of the external MOSFETs. In order
to maintain a constant and stable supply voltage (VCC) a low
ESR capacitor should be placed near the power and ground
pins. A 1 mF to 4.7 mF multi layer ceramic capacitor (MLCC)
is usually sufficient.
Low−Side Driver
The low−side driver is designed to drive a
ground−referenced low RDS(on) N−Channel MOSFET. The
voltage rail for the low−side driver is internally connected to
the VCC supply and PGND.
Input Pins
High−Side Driver
The PWM input and the Output Disable pins of the
ADP3120A have internal protection for Electro Static
Discharge (ESD), but in normal operation they present a
relatively high input impedance. If the PWM controller does
not have internal pulldown resistors, they should be added
externally to ensure that the driver outputs do not go high
before the controller has reached its under voltage lockout
threshold. The NCP5381 controller does include a passive
internal pulldown resistor on the drive−on output pin.
The high−side driver is designed to drive a floating low
RDS(on) N−channel MOSFET. The gate voltage for the high
side driver is developed by a bootstrap circuit referenced to
Switch Node (SW) pin.
The bootstrap circuit is comprised of an external diode,
and an external bootstrap capacitor. When the ADP3120A
are starting up, the SW pin is at ground, so the bootstrap
capacitor will charge up to VCC through the bootstrap diode
See Figure 4. When the PWM input goes high, the high−side
driver will begin to turn on the high−side MOSFET using the
stored charge of the bootstrap capacitor. As the high−side
MOSFET turns on, the SW pin will rise. When the high−side
MOSFET is fully on, the switch node will be at 12 V, and the
BST pin will be at 12 V plus the charge of the bootstrap
capacitor (approaching 24 V).
The bootstrap capacitor is recharged when the switch
node goes low during the next cycle.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(CBST) and the internal (or an external) diode. Selection of
these components can be done after the high−side MOSFET
has been chosen. The bootstrap capacitor must have a
voltage rating that is able to withstand twice the maximum
supply voltage. A minimum 50 V rating is recommended.
The capacitance is determined using the following equation:
CBST +
Safety Timer and Overlap Protection Circuit
It is very important that MOSFETs in a synchronous buck
regulator do not both conduct at the same time. Excessive
shoot−through or cross conduction can damage the
MOSFETs, and even a small amount of cross conduction
will cause a decrease in the power conversion efficiency.
The ADP3120A prevent cross conduction by monitoring
the status of the external mosfets and applying the
appropriate amount of “dead−time” or the time between the
turn off of one MOSFET and the turn on of the other
MOSFET.
When the PWM input pin goes high, DRVL will go low
after a propagation delay (tpdlDRVL). The time it takes for
the low−side MOSFET to turn off (tfDRVL) is dependent on
the total charge on the low−side MOSFET gate. The
ADP3120A monitor the gate voltage of both MOSFETs and
the switchnode voltage to determine the conduction status of
the MOSFETs. Once the low−side MOSFET is turned off an
internal timer will delay (tpdhDRVH) the turn on of the
high−side MOSFET
QGATE
DVBST
where QGATE is the total gate charge of the high−side
MOSFET, and DVBST is the voltage droop allowed on the
high−side MOSFET drive. For example, a NTD60N03 has
a total gate charge of about 30 nC. For an allowed droop of
300 mV, the required bootstrap capacitance is 100 nF. A
good quality ceramic capacitor should be used.
The bootstrap diode must be rated to withstand the
maximum supply voltage plus any peak ringing voltages
that may be present on SW. The average forward current can
be estimated by:
IF(AVG) + QGATE
fMAX
where fMAX is the maximum switching frequency of the
controller. The peak surge current rating should be checked
in−circuit, since this is dependent on the source impedance
of the 12 V supply and the ESR of CBST.
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5
ADP3120A
OD
VOD_HI
VOD_LO
tpdlOD
tpdhOD
90%
DRVH
or
DRVL
10%
Figure 2. Output Disable Timing Diagram
VPWM_HI
VPWM_LO
IN
tpdlDRVL
DRVL
tfDRVL
90%
90%
2V
10%
10%
tpdhDRVH
trDRVH
tpdlDRVH
90%
trDRVL
tfDRVH
90%
DRVH−SW
2V
10%
10%
tpdhDRVL
SW
Figure 3. Nonoverlap Timing Diagram
12 V
12 V
ADP3120A
4
Output Enable
PWM in
BST
DRVH
3
SW
OD
DRVL
2
IN PGND
Vcc
1
8
7
5
6
Vout
Figure 4. ADP3120A Example Circuit
FlexMode is a trademark of Analog Devices, Inc.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 3x3, 0.5P
CASE 506BJ−01
ISSUE O
1
SCALE 2:1
PIN 1
REFERENCE
2X
0.10 C
2X
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
0.10 C
EDGE OF PACKAGE
A
B
D
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30
MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L1
DETAIL A
E
OPTIONAL
CONSTRUCTION
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
L
TOP VIEW
DETAIL A
OPTIONAL
CONSTRUCTION
DETAIL B
0.05 C
DATE 08 NOV 2007
A
8X
0.05 C
NOTE 4
8X
8X
(A3)
SIDE VIEW
A1
D2
L
1
C
DETAIL A
4
8
5
e
8X
ÉÉ
ÉÉ
1
MOLD CMPD
DETAIL B
E2
K
GENERIC
MARKING DIAGRAM*
SEATING
PLANE
EXPOSED Cu
OPTIONAL
CONSTRUCTION
b
0.10 C A B
BOTTOM VIEW
0.05 C
NOTE 3
SOLDERMASK DEFINED
MOUNTING FOOTPRINT
1.85
8X
0.35
8X
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
1.64
1.84
3.00 BSC
1.35
1.55
0.50 BSC
0.20
−−−
0.30
0.50
0.00
0.03
XXXXX
XXXXX
ALYWG
G
8
XXXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
3.30
1.55
0.63
0.50
PITCH
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON25786D
DFN8 3X3, 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
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