FDBL86361_F085

MOSFET - POWERTRENCH) N-Channel 80 V, 300 A, 1.4 mW FDBL86361-F085 Features • • • • • www.onsemi.com Typical RDS(on) = 1.1 m at VGS = 10 V, ID = 80 A Typical Qg(tot) = 172 nC at VGS = 10 V, ID = 80 A UIS Capability AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant D Applications • • • • • G Automotive Engine Control PowerTrain Management Solenoid and Motor Drivers Integrated Starter/Alternator Primary Switch for 12 V Systems S N−Channel MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Parameter Ratings Unit VDSS Drain−to−Source Voltage 80 V VGS Gate−to−Source Voltage ±20 V 300 A ID Drain Current − Continuous (VGS = 10), TC = 25°C (Note 1) MARKING DIAGRAM Pulsed Drain Current, TC = 25°C See Figure 4 EAS Single Pulse Avalanche Energy (Note 2) 820 mJ PD Power Dissipation 429 W Derate Above 25°C 2.86 W/°C −55 to +175 °C 0.35 °C/W 43 °C/W TJ, TSTG Operating and Storage Temperature RJC Thermal Resistance, Junction to Case RJA Maximum Thermal Resistance, Junction to Ambient (Note 3) H−PSOF8L CASE 100CU Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Current is limited by bondwire configuration. 2. Starting TJ = 25°C, L = 0.4 mH, IAS = 64 A, VDD = 40 V during inductor charging and VDD = 0 V during time in avalanche. 3. RJA is the sum of the junction−to−case and case−to−ambient thermal resistance, where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design, while RJA is determined by the board design. The maximum rating presented here is based on mounting on a 1 in2 pad of 2oz copper. $Y&Z&3&K FDBL 86361 $Y &Z &3 &K FDBL86361 = ON Semiconductor Logo = Assembly Plant Code = Numeric Date Code = Lot Code = Specific Device Code ORDERING INFORMATION Device Top Mark Package Shipping{ FDBL86361 FDBL86361 H−PSOF8L 2000 Units/ −F085 Tape&Reel *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2014 December, 2019 − Rev. 5 1 Publication Order Number: FDBL86361−F085/D FDBL86361−F085 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Conditions Min. Typ. Max. Unit OFF CHARACTERISTICS BVDSS IDSS IGSS Drain−to−Source Breakdown Voltage ID = 250 A, VGS = 0 V 80 − − V Drain−to−Source Leakage Current VDS = 80 V, VGS = 0 V TJ = 25°C − − 1 A TJ = 175°C (Note 4) − − 1 mA − − ±100 nA 2.0 3.0 4.0 V TJ = 25°C − 1.1 1.4 m TJ = 175°C (Note 4) − 2.4 3.1 m − 12800 − pF − 1925 − pF − 139 − pF − 2.7 −  − 172 188 nC − 23 27 nC − 51 − nC − 34 − nC − − 128 ns Gate−to−Source Leakage Current VGS = ±20 V ON CHARACTERISTICS VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 A RDS(on) Drain to Source on Resistance ID = 80 A, VGS = 10 V DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Qg(ToT) Qg(th) VDS = 40 V, VGS = 0 V, f = 1 MHz Gate Resistance f = 1 MHz Total Gate Charge at 10 V VGS = 0 to 10 V Threshold Gate Charge VGS = 0 to 2 V Qgs Gate−to−Source Gate Charge Qgd Gate−to−Drain “Miller” Charge VDD = 64 V ID = 80 A SWITCHING CHARACTERISTICS ton Turn−On Time td(on) Turn−On Delay tr td(off) tf toff VDD = 40 V, ID = 80 A, VGS = 10 V, RGEN = 6  − 42 − ns Rise Time − 73 − ns Turn−Off Delay − 87 − ns Fall Time − 48 − ns Turn−Off Time − − 193 ns ISD = 80 A, VGS = 0 V − − 1.25 V ISD = 40 A, VGS = 0 V − − 1.2 V IF = 80 A, dISD/dt = 100 A/s, VDD = 64 V − 117 136 ns − 205 269 nC DRAIN−SOURCE DIODE CHARACTERISTIC VSD Source−to−Drain Diode Voltage trr Reverse−Recovery Time Qrr Reverse−Recovery Charge Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. The maximum value is specified by design at TJ = 175°C. Product is not tested to this condition in production. www.onsemi.com 2 FDBL86361−F085 TYPICAL CHARACTERISTICS Power Dissipation Multiplier 1.2 400 VGS = 10 V Current limited by package ID, Drain Current [A] 1.0 0.8 0.6 0.4 Current limited by silicon 300 200 100 0.2 0.0 0 25 50 75 100 125 150 0 175 25 50 75 TC, Case Temperature [5C] ZqJC, Normalized Thermal Impedance Figure 1. Normalized Power Dissipation vs. Case Temperature 2 100 125 150 175 200 TC, Case Temperature [5C] Figure 2. Maximum Continuous Drain Current vs. Case Temperature DUTY CYCLE − DESCENDING ORDER 1 D = 0.50 0.20 0.10 0.05 0.02 0.01 0.1 PDM t1 t2 NOTES: Duty factor: D = t1/t2 Peak TJ = PDM × ZJC (t) × RJC (t) + TC SINGLE PULSE 0.01 10−5 10−4 10−3 10−2 10−1 100 101 t, Rectangular Pulse Duration (s) Figure 3. Normalized Maximum Transient Thermal Impedance IDM, Peak Current [A] 10000 VGS = 10 V 1000 TC = 25°C For temperatures above 25°C derate peak current as follows: 100 I + I2 SINGLE PULSE 10 10−5 10−4 10−3 10−2 10−1 t, Rectangular Pulse Duration (s) Figure 4. Peak Current Capability www.onsemi.com 3 ƪǸ 175 * T 150 100 C ƫ 101 FDBL86361−F085 TYPICAL CHARACTERISTICS (continued) 2000 1000 IAS, Avalanche Current [A] ID, Drain Current [A] 2000 1000 100 Operation in this area may be limited by rDS(on) 10 100 us 1 ms 1 SINGLE PULSE TJ = max rated TC = 25°C 0.1 0.1 1 10 10 ms 100 ms 100 If R = 0 tAV = (L)(IAS) / (1.3 × Rated BVDSS − VDD) If R ≠ 0 tAV = (L/R)ln[(IAS × R) / (1.3 × Rated BVDSS − VDD) + 1] 100 Starting TJ = 25°C 10 Starting TJ = 150°C 1 0.001 500 0.01 1 0.1 VDS, Drain to Source Voltage [V] 100 10 1000 10000 tAV, Time in Avalanche [ms] Refer to ON Semiconductor Application Notes AN7514 and AN7515. Figure 5. Forward Bias Safe Operating Area 300 IS, Reverse Drain Current [A] VDD = 5 V 180 TJ = 25°C 120 TJ = 175°C 60 0 TJ = −55°C 2 3 4 5 10 TJ = 175°C 1 TJ = 25°C 0.1 0.01 0.001 0.0 7 0.2 0.4 0.6 0.8 1.0 VSD, Body Diode Forward Voltage [V] Figure 7. Transfer Characteristics Figure 8. Forward Diode Characteristics 150 5V 100 5V 1 2 3 4 VGS 15 V Top 10 V 8V 7V 6V 5.5 V 5 V Bottom 200 80 s Pulse Width TJ = 25°C 50 1.2 250 VGS 15 V Top 10 V 8V 7V 6V 5.5 V 5 V Bottom 200 0 VGS = 0 V 100 VGS, Gate to Source Voltage [V] 250 0 6 ID, Drain Current [A] ID, Drain Current [A] 300 Pulse duration = 80 s Duty cycle = 0.5% MAX 240 ID, Drain Current [A] Figure 6. Unclamped Inductive Switching Capability 150 100 50 0 5 VDS, Drain to Source Voltage [V] 80 s Pulse Width TJ = 175°C 0 1 2 3 4 VDS, Drain to Source Voltage [V] Figure 9. Saturation Characteristics Figure 10. Saturation Characteristics www.onsemi.com 4 5 FDBL86361−F085 TYPICAL CHARACTERISTICS (continued) ID = 80 A 2.4 Pulse duration = 80 s Duty cycle = 0.5% MAX Normalized Drain to Source On−Resistance rDS(on), Drain to Source On−Resistance [mW] 20 16 12 TJ = 175°C TJ = 25°C 8 4 0 4 6 8 Pulse duration = 80 s Duty cycle = 0.5% MAX 2.0 1.6 1.2 ID = 80 A VGS = 10 V 0.8 0.4 −80 10 −40 0 VGS, Gate to Source Voltage [V] 1.10 VGS = VDS ID = 250 A 1.2 0.9 0.6 0.3 0.0 −80 −40 0 40 80 120 160 0.95 0.90 −80 200 −40 VGS, Gate to Source Voltage [V] Capacitance [pF] Coss 100 Crss 10 40 80 120 160 200 Figure 14. Normalized Drain to Source Breakdown Voltage vs. Junction Temperature Ciss 1 0 TJ, Junction Temperature [5C] 10 10 0.1 200 1.00 100000 f = 1 MHz VGS = 0 V 160 1.05 Figure 13. Normalized Gate Threshold Voltage vs. Temperature 1000 120 ID = 5 mA TJ, Junction Temperature [5C] 10000 80 Figure 12. Normalized RDSON vs. Junction Temperature Normalized Drain to Source Breakdown Voltage Normalized Gate Threshold Voltage Figure 11. RDSON vs. Gate Voltage 1.5 40 TJ, Junction Temperature [5C] VDD = 40 V 8 VDD = 48 V VDD = 32 V 6 4 2 0 100 ID = 80 A 0 20 40 60 80 100 120 140 160 180 Qg, Gate Charge [nC] VDS, Drain to Source Voltage [V] Figure 15. Capacitance vs. Drain to Source Voltage Figure 16. Gate Charge vs. Gate to Source Voltage POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS H−PSOF8L 11.68x9.80 CASE 100CU ISSUE B DATE 20 MAY 2022 GENERIC MARKING DIAGRAM* AYWWZZ XXXXXXXX XXXXXXXX A Y WW ZZ XXXX DOCUMENT NUMBER: DESCRIPTION: = Assembly Location = Year = Work Week = Assembly Lot Code = Specific Device Code 98AON13813G H−PSOF8L 11.68x9.80 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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