FDBL9406L-F085

MOSFET - Power, Single N-Channel 40 V, 1.1 mW, 240 A FDBL9406L-F085 Features • • • • • Small Footprint (TOLL) for Compact Design Low RDS(on) to Minimize Conduction Losses Low QG and Capacitance to Minimize Driver Losses AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com V(BR)DSS RDS(ON) MAX 1.1 mW @ 10 V 40 V 1.78 mW @ 4.5 V MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current RqJC (Notes 1, 3) Power Dissipation RqJC (Note 1) Continuous Drain Current RqJA (Notes 1, 2, 3) Steady State Value Unit VDSS 40 V VGS ±20 V TC = 25°C ID 240 A TC = 25°C PD 300 W TC = 100°C Steady State D (9) G (1) TA = 100°C A 43 31 3.5 IDM 2755 A TJ, Tstg −55 to +175 °C IS 100 A Single Pulse Drain−to−Source Avalanche Energy (IL(pk) = 85 A; L = 60 mH) EAS 217 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C TA = 25°C TA = 100°C TC = 25°C, tp = 10 ms Operating Junction and Storage Temperature Range Source Current (Body Diode) N−CHANNEL MOSFET 150 ID PD Pulsed Drain Current 80 A S (2−8) TA = 25°C Power Dissipation RqJA (Notes 1, 2) Symbol ID MAX W 1.7 MO−299A CASE 100CU MARKING DIAGRAM &Z&3&K FDBL 9406L Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE MAXIMUM RATINGS Parameter Symbol Value Unit Junction−to−Case − Steady State RqJC 0.5 °C/W Junction−to−Ambient − Steady State (Note 2) RqJA 43 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. Current is limited by bondwire configuration. 2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. © Semiconductor Components Industries, LLC, 2018 December, 2019 − Rev. 1 1 &Z &3 &K FDBL9406L = Assembly Plant Code = Numeric Date Code = Lot Code = Specific Device Code ORDERING INFORMATION See detailed ordering and shipping information on page 7 of this data sheet. Publication Order Number: FDBL9406L−F085/D FDBL9406L−F085 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Test Conditions Min Typ Max Unit Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 40 − − V Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ − 19.3 − mV/°C VGS = 0 V, VDS = 40 V, TJ = 25°C − − 1 mA VGS = 0 V, VDS = 40 V, TJ = 175°C − − 1 mA IGSS VDS = 0 V, VGS = ±20 V − − ±100 nA VGS(th) VGS = VDS, ID = 250 mA 1 1.9 3 V − −6.5 − mV/°C VGS = 10 V, ID = 80 A − 0.9 1.1 mW VGS = 4.5 V, ID = 40 A − 1.25 1.78 VGS = 0 V, f = 1 MHz, VDS = 20 V − 8600 − pF Parameter OFF CHARACTERISTICS Zero Gate Voltage Drain Current Zero Gate Voltage Drain Current IDSS ON CHARACTERISTICS (Note 4) Gate Threshold Voltage Threshold Temperature Coefficient Drain−to−Source On Resistance VGS(th)/TJ RDS(on) CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance Ciss Output Capacitance Coss − 2380 − pF Reverse Transfer Capacitance Crss − 106 − pF Gate Resistance Total Gate Charge Threshold Gate Charge Rg VGS = 0.5 V, f = 1 MHz − 2 − W QG(TOT) VGS = 4.5 V, VDS = 32 V, ID = 80 A − 58 − nC VGS = 10 V, VDS = 32 V, ID = 80 A − 121 − Qg(th) VGS = 0 to 1 V − 7 − Gate−to−Source Gate Charge Qgs VDD = 32 V, ID = 80 A − 26 − Gate−to−Drain “Miller” Charge Qgd − 19 − Plateau Voltage VGP − 3.2 − V − 22 − ns SWITCHING CHARACTERISTICS Turn-On Delay Time td(on) VDD = 20 V, ID = 80 A, VGS = 10 V, RGEN = 6 W Turn-On Rise Time tr − 22 − ns Turn-Off Delay Time td(off) − 134 − ns tf − 44 − ns ISD = 80 A, VGS = 0 V − 0.81 1.25 V ISD = 40 A, VGS = 0 V − 0.77 1.2 V VGS = 0 V, dISD/dt = 100 A/ms IS = 80 A − 77 − ns − 38 − Turn-Off Fall Time DRAIN−SOURCE DIODE CHARACTERISTICS Source−to−Drain Diode Voltage Reverse Recovery Time VSD TRR Charge Time ta Discharge Time tb − 39 − QRR − 95 − Reverse Recovery Charge nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 5. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 2 FDBL9406L−F085 TYPICAL CHARACTERISTICS POWER DISSIPATION MULTIPLIER 1.2 450 400 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 ZqJC, NORMALIZED THERMAL IMPEDANCE 0 Current Limited by Package 350 300 250 VGS = 10 V 200 150 100 50 0 25 50 75 100 125 150 0 175 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (°C) TC, CASE TEMPERATURE (°C) Figure 1. Normalized Power Dissipation vs. Case Temperature Figure 2. Maximum Continuous Drain Current vs. Case Temperature 2 1 50% Duty Cycle 20% PDM 10% 0.1 5% t1 2% t2 1% ZqJC(t) = r(t) x RqJC Peak TJ = PDM x ZqJC(t) + TC Duty Cycle, D = t1/t2 Single Pulse 0.01 0.00001 0.0001 0.001 0.01 0.1 1 10 t, RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance VGS = 10 V 1000 1000 TC = 25°C For temperatures above 25°C derate peak current as follows: I + I 25 ƪǸ ID, DRAIN CURRENT (A) IDM, PEAK CURRENT (A) 5000 ƫ 175 * T C 150 Single Pulse 100 0.00001 0.0001 0.001 0.01 0.1 1 100 100 ms 10 Operation in this area may be limited by RDS(on) 1 0.1 10 Operation in this area may be limited by package 0.1 1 ms 10 ms Single Pulse 100 ms TJ = Max Rated TC = 25°C 1 10 t, RECTANGULAR PULSE DURATION (s) −VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 4. Peak Current Capability Figure 5. Forward Bias Safe Operating Area www.onsemi.com 3 100 FDBL9406L−F085 TYPICAL CHARACTERISTICS ID, DRAIN CURRENT (A) 100 TJ(initial) = 25°C 10 TJ(initial) = 150°C NOTE: Refer to ON Semiconductor Application Notes AN7514 and AN7515 0.001 0.01 400 0.1 1 10 100 1000 50 TJ = 175°C 1 TJ = −55°C 2 3 4 Figure 7. Transfer Characteristics 350 VGS = 10 V to 4 V 3.5 V 300 TJ = 175°C 0.1 0.01 250 200 150 100 Pulse Width = 250 ms TJ = 25°C 50 TJ = −55°C TJ = 25°C 0 0.2 0.4 0.6 0.8 0 1.2 0.5 1.0 1.5 2.0 Figure 8. Forward Diode Characteristics Figure 9. Saturation Characteristics 10 VGS = 10 V 4 3 VGS = 6 V to 3.5 V 2 1 0 0 VDS, DRAIN−SOURCE VOLTAGE (V) Pulse Width = 250 ms TJ = 25°C 5 1.0 VSD, BODY DIODE FORWARD VOLTAGE (V) 6 RDS(on), NORMALIZED DRAIN− SOURCE ON−RESISTANCE TJ = 25°C 100 Figure 6. Unclamped Inductive Switching Capability 1 0 150 VGS, GATE−TO−SOURCE VOLTAGE (V) 10 0.001 200 tAV, TIME IN AVALANCHE (mS) VGS = 0 V 100 Pulse Duration = 250 ms Duty Cycle = 0.5% Max VDS = 5 V 250 0 ID, DRAIN CURRENT (A) 1 IS, REVERSE DRAIN CURRENT (A) 300 If R = 0 tAV = (L)(IAS)/(1.3*Rated BVDSS − VDD) If R ≠ 0 tAV = (L/R)In[(IAS*R)/(1.3*Rated BVDSS − VDD) +1] RDS(on), ON−RESISTANCE (mW) IAS, AVALANCHE CURRENT (A) 500 50 100 150 200 250 300 ID = 80 A 8 6 4 0 350 TJ = 175°C 2 TJ = 25°C 2 3 4 5 6 7 8 ID, DRAIN CURRENT (A) VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 10. Normalized RDS(on) vs. Drain Current Figure 11. RDS(on) vs. Gate Voltage www.onsemi.com 4 9 10 FDBL9406L−F085 TYPICAL CHARACTERISTICS 1.4 NORMALIZED GATE THRESHOLD VOLTAGE RDS(on), NORMALIZED DRAIN− SOURCE ON−RESISTANCE 1.8 VGS = 10 V ID = 80 A 1.6 1.4 1.2 1.0 0.8 0.6 −80 −40 0 40 80 120 160 NORMALIZED DRAIN−TO−SOURCE BREAKDOWN VOLTAGE 1.2 1.0 0.8 0.6 0.4 −80 200 −40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 12. Normalized RDS(on) vs. Junction Temperature Figure 13. Normalized Gate Threshold Voltage vs. Temperature 1.10 100,000 ID = 5 mA CISS 10,000 CAPACITANCE (pF) 1.06 1.02 0.98 0.94 −80 VGS, GATE−TO−SOURCE VOLTAGE (V) VGS = VDS ID = 1 mA −40 0 40 80 120 160 200 COSS 1000 CRSS 100 10 VGS = 0 V f = 100 KHz 0.1 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 14. Normalized Drain−to−Source Breakdown Voltage vs. Junction Temperature Figure 15. Capacitance vs. Drain−to−Source Voltage VDD = 20 V 8 6 VDD = 16 V VDD = 24 V 4 2 0 10 TJ, JUNCTION TEMPERATURE (°C) 10 0 1 28 56 84 112 140 Qg, GATE CHARGE (nC) Figure 16. Gate Charge vs. Gate−to−Source Voltage www.onsemi.com 5 40 FDBL9406L−F085 PACKAGE MARKING AND ORDERING INFORMATION Part Number Top Marking Package Reel Size Tape Width Quantity FDBL9406L−F085 FDBL9406L H−PSOF8L (Pb-Free / Halogen Free) 13″ 24 mm 2000 Units †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS H−PSOF8L 11.68x9.80 CASE 100CU ISSUE A DATE 06 JAN 2020 GENERIC MARKING DIAGRAM* AYWWZZ XXXXXXXX XXXXXXXX A Y WW ZZ XXXX DOCUMENT NUMBER: DESCRIPTION: = Assembly Location = Year = Work Week = Assembly Lot Code = Specific Device Code 98AON13813G H−PSOF8L 11.68x9.80 *This information is generic. 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