FDMC86106LZ

FDMC86106LZ N-Channel Shielded Gate PowerTrench® MOSFET 100 V, 7.5 A, 103 mΩ Features General Description „ Shielded Gate MOSFET Technology This N-Channel logic Level MOSFETs are produced using Fairchild Semiconductor‘s advanced PowerTrench® process that incorporates Shielded Gate technology. This process has been optimized for the on-state resistance and yet maintain superior switching performance. G-S zener has been added to enhance ESD voltage level. „ Max rDS(on) = 103 mΩ at VGS = 10 V, ID = 3.3 A „ Max rDS(on) = 153 mΩ at VGS = 4.5 V, ID = 2.7 A „ HBM ESD protection level > 3 KV typical (Note 4) „ 100% UIL Tested „ RoHS Compliant Application „ DC - DC Conversion Bottom Top 8 1 7 6 D D D D 5 S D S D S D G D G S S S 2 3 4 MLP 3.3x3.3 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current -Continuous (Package limited) ID TC = 25 °C -Continuous (Silicon limited) TC = 25 °C -Continuous TA = 25 °C PD TJ, TSTG Units V ±20 V 7.5 9.6 (Note 1a) -Pulsed 3.3 A 15 Single Pulse Avalanche Energy EAS Ratings 100 (Note 3) Power Dissipation TC = 25 °C Power Dissipation TA = 25 °C 12 19 (Note 1a) Operating and Storage Junction Temperature Range 2.3 -55 to +150 mJ W °C Thermal Characteristics RθJC Thermal Resistance, Junction to Case RθJA Thermal Resistance, Junction to Ambient 6.5 (Note 1a) 53 °C/W Package Marking and Ordering Information Device Marking FDMC86106Z Device FDMC86106LZ ©2011 Fairchild Semiconductor Corporation FDMC86106LZ Rev.C2 Package Power 33 1 Reel Size 13 ’’ Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDMC86106LZ N-Channel Shielded Gate PowerTrench® MOSFET November 2013 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±10 μA 2.2 V 100 V 73 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C VGS = 10 V, ID = 3.3 A 79 rDS(on) Static Drain to Source On Resistance VGS = 4.5 V, ID = 2.7 A 105 153 VGS = 10 V, ID = 3.3 A, TJ = 125 °C 136 178 gFS Forward Transconductance 1.0 VDS = 5 V, ID = 3.3 A 1.8 -6 mV/°C 103 11 mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance VDS = 50 V, VGS = 0 V, f = 1 MHz 232 310 pF 45 60 pF 2.4 5 pF Ω 0.7 Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg(TOT) Total Gate Charge Qg(TOT) Total Gate Charge Qgs Total Gate Charge Qgd Gate to Drain “Miller” Charge VDD = 50 V, ID = 3.3 A, VGS = 10 V, RGEN = 6 Ω VGS = 0 V to 10 V VGS = 0 V to 4.5 V VDD = 50 V, ID = 3.3 A 4.5 10 1.3 10 ns ns 10 20 ns 1.4 10 ns 4 6 nC 2 3 nC 0.8 nC 0.7 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 3.3 A (Note 2) 0.85 1.3 VGS = 0 V, IS = 2 A (Note 2) 0.82 1.2 IF = 3.3 A, di/dt = 100 A/μs V 33 54 ns 23 38 nC NOTES: 1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. b. 125 °C/W when mounted on a minimum pad of 2 oz copper a. 53 °C/W when mounted on a 1 in2 pad of 2 oz copper SS SF DS DF G SS SF DS DF G 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3. Starting TJ = 25 °C; N-ch: L = 1.0 mH, IAS = 5.0 A, VDD = 90 V, VGS = 10 V. 4. The diode connected between gate and source serves only as protection against ESD. No gate overvoltage rating is implied. ©2011 Fairchild Semiconductor Corporation FDMC86106LZ Rev.C2 2 www.fairchildsemi.com FDMC86106LZ N-Channel Shielded Gate PowerTrench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted 5 VGS = 10 V VGS = 4.5 V NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) 15 VGS = 4 V 12 9 VGS = 3.5 V 6 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 3 V 3 0 0 1 2 3 4 VGS = 3 V VGS = 3.5 V 4 VGS = 4 V 3 VGS = 4.5 V 2 1 0 5 0 3 Figure 1. On Region Characteristics 500 ID = 3.3 A VGS = 10 V ID = 3.3 A SOURCE ON-RESISTANCE (mΩ) 12 15 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 400 1.8 rDS(on), DRAIN TO NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 9 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 2.2 1.6 1.4 1.2 1.0 300 200 TJ = 125 oC 100 0.8 0.6 -75 -50 IS, REVERSE DRAIN CURRENT (A) VDS = 5 V 9 6 TJ = 25 oC 3 TJ = -55 oC 0 1 2 3 4 5 20 10 6 8 10 VGS = 0 V 1 TJ = 150 oC 0.1 TJ = 25 oC 0.01 0.001 0.0 6 VGS, GATE TO SOURCE VOLTAGE (V) TJ = -55 oC 0.2 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics ©2011 Fairchild Semiconductor Corporation FDMC86106LZ Rev.C2 4 Figure 4. On-Resistance vs Gate to Source Voltage PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX TJ = 150 oC 2 VGS, GATE TO SOURCE VOLTAGE (V) 15 12 TJ = 25 oC 0 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) Figure 3. Normalized On Resistance vs Junction Temperature ID, DRAIN CURRENT (A) 6 ID, DRAIN CURRENT (A) VDS, DRAIN TO SOURCE VOLTAGE (V) 2.0 VGS = 10 V PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX Figure 6. Source to Drain Diode Forward Voltage vs Source Current 3 www.fairchildsemi.com FDMC86106LZ N-Channel Shielded Gate PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 1000 ID = 3.3 A VDD = 25 V 8 Ciss CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 50 V 6 VDD = 75 V 4 100 Coss 10 2 f = 1 MHz VGS = 0 V 0 0 1 2 3 4 1 0.1 5 1 Figure 7. Gate Charge Characteristics 100 Figure 8. Capacitance vs Drain to Source Voltage -1 10 9 8 7 6 5 10 Ig, GATE LEAKAGE CURRENT (A) IAS, AVALANCHE CURRENT (A) 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) TJ = 25 oC 4 TJ = 100 oC 3 2 TJ = 125 oC 1 0.001 -2 10 VGS = 0 V -3 10 -4 10 TJ = 125 oC -5 10 -6 10 TJ = 25 oC -7 10 -8 10 -9 0.01 0.1 1 10 10 0 tAV, TIME IN AVALANCHE (ms) 4 8 12 16 20 24 28 32 36 VGS, GATE TO SOURCE VOLTAGE (V) Figure 9. Unclamped Inductive Switching Capability Figure 10. Gate Leakage Current vs Gate to Source Voltage 10 20 10 8 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) Crss VGS = 10 V 6 Limited by package 4 VGS = 4.5 V 2 o 50 75 100 125 150 o TC, CASE TEMPERATURE ( C) 0.1 10 ms 100 ms SINGLE PULSE TJ = MAX RATED 1s RθJA = 125 oC/W 10 s DC 1 10 100 400 VDS, DRAIN to SOURCE VOLTAGE (V) Figure 12. Forward Bias Safe Operating Area Figure 11. Maximum Continuous Drain Current vs Case Temperature ©2011 Fairchild Semiconductor Corporation FDMC86106LZ Rev.C2 1 ms THIS AREA IS LIMITED BY rDS(on) 0.01 TA = 25 oC 0.005 0.1 RθJC = 6.5 C/W 0 25 100 us 1 4 www.fairchildsemi.com FDMC86106LZ N-Channel Shielded Gate PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted P(PK), PEAK TRANSIENT POWER (W) 500 100 10 SINGLE PULSE o RθJA = 125 C/W o 1 TA = 25 C 0.5 -4 10 -3 -2 10 -1 10 10 1 100 10 1000 t, PULSE WIDTH (sec) Figure 13. Single Pulse Maximum Power Dissipation 2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 125 C/W 0.001 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 14. Junction-to-Ambient Transient Thermal Response Curve ©2011 Fairchild Semiconductor Corporation FDMC86106LZ Rev.C2 5 www.fairchildsemi.com FDMC86106LZ N-Channel Shielded Gate PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted A 0.10 C 2X 8 B (3.40) 2.37 5 0.45(4X) 2.15 (1.70) (0.40) KEEP OUT AREA (0.65) PIN1 IDENT A 0.65 0.10 C TOP VIEW 0.70(4X) 1 4 0.42(8X) 1.95 2X 0.8MAX 0.10 C (0.20) 0.08 C 0.05 0.00 SIDE VIEW RECOMMENDED LAND PATTERN C SEATING PLANE 2.27+0.05 1 4 0.45+0.05 (4X) (0.40) (1.20) 2.05+0.05 0.45+0.05 (3X) A 8 0.65 5 1.95 0.32+0.05 (8X) 0.10 0.05 NOTES: A.EXCEPT AS NOTED, PACKAGE CONFORMS TO JEDEC REGISTRATION MO-240 VARIATION BA.. B.DIMENSIONS ARE IN MILLIMETERS. C.DIMENSIONS AND TOLERANCES PER ASME Y14.5M,1994. D.SEATING PLANE IS DEFINED BY TERMINAL TIPS ONLY E.BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH PROTRUSIONS NOR GATEBURRS. F.FLANGE DIMENSIONS INCLUDE INTERTERMINAL FLASH OR PROTRUSION. INTERTERMINAL FLASH OR PROTRUSION SHALL NOT EXCEED 0.25MM PER SIDE. G.IT IS RECOMMENDED TO HAVE NO TRACES OR VIA WITHIN THE KEEP OUT AREA. H.DRAWING FILENAME: MKT-MLP08Trev3. I.GENERAL RADII FOR ALL CORNERS SHALL BE 0.20MM MAX. J.FAIRCHILD SEMICONDUCTOR. C A B C BOTTOM VIEW ©2011 Fairchild Semiconductor Corporation FDMC86106LZ Rev.C2 6 www.fairchildsemi.com FDMC86106LZ N-Channel Shielded Gate PowerTrench® MOSFET Dimensional Outline and Pad Layout tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts, have full traceability, meet Fairchild’s quality standards for handing and storage and provide access to Fairchild’s full range of up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I66 ©2011 Fairchild Semiconductor Corporation FDMC86106LZ Rev.C2 7 www.fairchildsemi.com FDMC86106LZ N-Channel Shielded Gate PowerTrench® MOSFET TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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