MC100LVEL40DWG

3.3/5 V ECL Differential Phase-Frequency Detector MC100LVEL40 Description The MC100LVEL40 is a three state phase frequency−detector intended for phase−locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design significantly reduces the dead zone of the detector. For proper operation, the input edge rate of the R and V inputs should be less than 5 ns. The device is designed to work with a 3.3 V power supply. When the reference (R) and the feedback (FB) inputs are unequal in frequency and/or phase the differential up (U) and down (D) outputs will provide pulse streams which when subtracted and integrated provide an error voltage for control of a VCO. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. For application information, refer to AND8040/D, “Phase Lock Loop Operation.” The 100 Series Contains Temperature Compensation. Features • • 20 1 SO−20 DW SUFFIX CASE 751D MARKING DIAGRAM 20 100LVEL40 AWLYYWWG 1 • 250 MHz Typical Bandwidth • PECL Mode Operating Range: • www.onsemi.com VCC = 3.0 V to 5.5 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V Internal Input Pulldown Resistor This Devices are Pb−Free, Halogen Free and are RoHS Compliant A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device MC100LVEL40DWG © Semiconductor Components Industries, LLC, 2008 March, 2021 − Rev. 11 1 Package Shipping SOIC−20 (Pb−Free) 38 Units / Tube Publication Order Number: MC100LVEL40/D MC100LVEL40 NC VCCO U U VEE D D 20 18 17 16 15 14 19 VCCO NC NC 12 11 13 1 2 3 4 5 6 7 8 9 10 NC NC R R VBB FB FB VCC NC NC Table 1. PIN DESCRIPTION PIN FUNCTION U, U D, D FB, FB R, R VBB VCC, VCCO VEE NC ECL Up Differential Outputs ECL Down Differential Outputs ECL Feedback Differential Inputs ECL Reference Differential Inputs Reference Voltage Output Positive Supply Negative Supply No Connect Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. 20−Lead Pinout (Top View) R S R Q U U R VBB VEE D D R FB S FB Q Figure 2. Logic Diagram Table 2. ATTRIBUTES Characteristics Value ESD Protection Human Body Model > 2 kV Moisture Sensitivity (Note 1) Pb−Free Pkg SOIC−20 Level 3 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 356 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2 MC100LVEL40 Table 3. MAXIMUM RATINGS Symbol Rating Unit VCC PECL Mode Power Supply Parameter VEE = 0 V Condition 1 Condition 2 8 to 0 V VEE NECL Mode Power Supply VCC = 0 V −8 to 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 to 0 −6 to 0 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ±0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−20 SOIC−20 90 306 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−20 30 to 35 °C/W Tsol Wave Solder (Pb−Free) 265 °C VI v VCC VI w VEE Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Table 4. LVPECL DC CHARACTERISTICS VCC = 3.3 V, VEE = 0 V (Note 2) −40°C Symbol Characteristic Min 25°C Typ Max 38 45 Min 85°C Typ Max 38 47 Min Typ Max Unit 38 47 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 3) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mV VOL Output LOW Voltage (Note 3) 1470 1605 1745 1490 1595 1380 1490 1595 1680 mV VIH Input HIGH Voltage (Single−Ended) 2135 2420 2135 2420 2135 2420 mV VIL Input LOW Voltage (Single−Ended) 1490 1825 1490 1825 1490 1825 mV VBB Output Voltage Reference 1.92 2.04 1.92 2.04 1.92 2.04 V Input HIGH Voltage Common Mode Range (Note 7) Vpp < 500 mV Vpp y 500 mV 1.3 1.5 3.3 3.3 1.2 1.4 3.3 3.3 1.2 1.4 3.3 3.3 V V 150 mA VIHCMR IIH Input HIGH Current IIL Input LOW Current Others R, FB 150 0.5 −300 150 0.5 −300 0.5 −300 mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 2. Input and output parameters vary 1:1 with VCC. VEE can vary ± 0.3 V. 3. Outputs are terminated through a 50 W resistor to VCC − 2 V. 4. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. www.onsemi.com 3 MC100LVEL40 Table 5. LVNECL DC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V (Note 5) −40°C Symbol Min Characteristic 25°C Typ Max 38 45 Min 85°C Typ Max 38 47 Min Typ Max Unit 38 47 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 6) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV VOL Output LOW Voltage (Note 6) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV VIH Input HIGH Voltage (Single−Ended) −1165 −880 −1165 −880 −1165 −880 mV VIL Input LOW Voltage (Single−Ended) −1810 −1475 −1810 −1475 −1810 −1475 mV VBB Output Voltage Reference −1.38 −1.26 −1.38 −1.26 −1.38 −1.26 V Input HIGH Voltage Common Mode Range (Note 7) Vpp < 500 mV Vpp y 500 mV −2.0 −1.8 −0.4 −0.4 −2.1 −1.9 −0.4 −0.4 −2.1 −1.9 −0.4 −0.4 V V 150 mA VIHCMR IIH Input HIGH Current IIL Input LOW Current Others R, FB 150 0.5 −300 150 0.5 −300 0.5 −300 mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 5. Input and output parameters vary 1:1 with VCC. VEE can vary ± 0.3 V. 6. All loading with 50 W resistor to VCC − 2 V. 7. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. Table 6. AC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V or VCC = 0 V; VEE = −3.3 V (Note 8) −40°C Symbol Fmax Characteristic Maximum Toggle Frequency tPLH tPHL Propagation Delay VPP Input Swing (Differential Configuration) (Note 9) tJITTER tr, tf Min R to U, FB to D Max Min TBD Typ 85°C Max Min TBD Typ Max TBD Unit GHz 430 1200 630 1400 450 1250 650 1450 480 1370 680 1590 ps 150 1000 150 1000 150 1000 mV 475 175 475 175 Cycle−to−Cycle Jitter Output Rise/Fall Times Typ 25°C TBD 175 TBD TBD ps 475 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 8. VEE can vary ± 0.3 V. 9. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈ 40. www.onsemi.com 4 MC100LVEL40 Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).or its subsidiaries in the United States and/or other countries. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−20 WB CASE 751D−05 ISSUE H DATE 22 APR 2015 SCALE 1:1 A 20 q X 45 _ M E h 0.25 H NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 1 10 20X B b 0.25 M T A S B DIM A A1 b c D E e H h L q S L A 18X e SEATING PLANE A1 c T GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 20 20X 20X 1.30 0.52 20 XXXXXXXXXXX XXXXXXXXXXX AWLYYWWG 11 1 11.00 1 XXXXX A WL YY WW G 10 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ 98ASB42343B SOIC−20 WB = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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