MC100LVEL92
5V Triple PECL Input to
LVPECL Output Translator
Description
The MC100LVEL92 is a triple PECL input to LVPECL output
translator. The device receives standard PECL signals and translates
them to differential LVPECL output signals.
To accomplish the PECL to LVPECL level translation, the
MC100LVEL92 requires three power rails. The VCC supply is to be
connected to the standard 5 V PECL supply, the LVCC supply is to be
connected to the 3.3 V LVPECL supply, and Ground is connected to
the system ground plane. Both the VCC and LVCC should be bypassed
to ground with 0.01 mF capacitors.
The PECL VBB pin, an internally generated voltage supply, is
available to this device only. For single-ended input conditions, the
unused differential input is connected to VBB as a switching reference
voltage. VBB may also rebias AC coupled inputs. When used,
decouple VBB and VCC via a 0.01 mF capacitor and limit current
sourcing or sinking to 0.5 mA. When not used, VBB should be
left open.
Features
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SOIC−20 WB
DW SUFFIX
CASE 751D
MARKING DIAGRAM*
20
• 500 ps Propagation Delays
• 5 V and 3.3 V Supplies Required
• ESD Protection: Human Body Model; > 2 kV,
•
•
•
•
•
•
•
•
•
•
100LVEL92
AWLYYWWG
Machine Model; > 200 V
The 100 Series Contains Temperature Compensation
LVPECL Operating Range: LVCC = 3.0 V to 3.8 V
PECL Operating Range: VCC = 4.5 V to 5.5 V
Internal Input Pulldown Resistors
Q Output will Default LOW with Inputs Open or < GND + 1.3 V
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity: Level 3 (Pb−Free)
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index 28 to 34
Transistor Count = 247 devices
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
MC100LVEL92DWG
Package
Shipping†
SOIC−20 WB
(Pb-Free)
38 Units/Tube
MC100LVEL92DWR2G SOIC−20 WB 1000/Tape & Reel
(Pb-Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 13
1
Publication Order Number:
MC100LVEL92/D
MC100LVEL92
VCC
Q0
Q0 LVCC
Q1
Q1
20
19
18
16
15
17
LVCC Q2
14
13
LVPECL
LVPECL
PECL
PECL
PECL
2
3
D0
D0
4
5
6
D1
D1
7
VBB PECL
1
VCC
VBB PECL
LVPECL
Q2
VCC
12
11
8
9
10
D2
D2
GND
Table 1. PIN DESCRIPTION
PIN
FUNCTION
Dn, Dn
Qn, Qn
PECL VBB
LVCC
VCC
GND
PECL Inputs
LVPECL Outputs
PECL Reference Voltage Output
LVPECL Power Supply
PECL Power Supply
Common Ground Rail
Warning: All VCC, LVCC, and GND pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. Logic Diagram and Pinout: SO−20 WB (Top View)
Table 2. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Power Supply
GND = 0 V
8 to 0
V
LVCC
LVPECL Power Supply
GND = 0 V
8 to 0
V
VI
PECL Input Voltage
GND = 0 V
6 to 0
V
Iout
Output Current
Continuous
Surge
50
100
mA
IBB
PECL VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction-to-Ambient)
0 lfpm
500 lfpm
SOIC−20 WB
90
60
°C/W
qJC
Thermal Resistance (Junction-to-Case)
Standard Board
SOIC−20 WB
30 to 35
°C/W
Tsol
Wave Solder (Pb-Free)
< 2 to 3 sec @ 260°C
265
°C
VI ≤ VCC
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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2
MC100LVEL92
Table 3. PECL INPUT DC CHARACTERISTICS (VCC = 5.0 V; LVCC = 3.3 V; GND = 0 V Note 1))
−40°C
Symbol
IVCC
Characteristic
Min
Typ
PECL Power Supply Current
25°C
Max
Min
Typ
12
85°C
Max
Min
Typ
12
Max
Unit
12
mA
VIH
Input HIGH Voltage (Single-Ended)
3835
4120
3835
4120
3835
4120
mV
VIL
Input LOW Voltage (Single-Ended)
3190
3515
3190
3525
3190
3525
mV
Output Voltage Reference
3.62
3.74
3.62
3.74
3.62
3.74
V
PECL VBB
VIHCMR
Input HIGH Voltage Common Mode
Range (DIfferential) (Note 2)
Vpp < 500 mV
Vpp ≥ 500 mV
IIH
Input HIGH Current
IIL
Input LOW Current
D
D
V
1.3
1.5
4.8
4.8
1.2
1.4
4.8
4.8
150
0.5
−600
1.2
1.4
4.8
4.8
150
0.5
−600
150
mA
mA
0.5
−600
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input parameters vary 1:1 with VCC. VCC can vary 4.5 V to 5.5 V.
2. VIHCMR min varies 1:1 with GND. VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin
and 1.0 V.
Table 4. LVPECL OUTPUT DC CHARACTERISTICS (VCC = 5.0 V; LVCC = 3.3 V; GND = 0 V (Note 1))
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
20
85°C
Max
Min
ILVCC
LVPECL Power Supply Current
VOH
Output HIGH Voltage (Note 2)
2215
2295
2420
2275
2345
2420
2275
VOL
Output LOW Voltage (Note 2)
1470
1605
1745
1490
1595
1680
1490
Typ
Max
Unit
21
mA
2345
2420
mV
1595
1680
mV
20
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Output parameters vary 1:1 with LVCC. VCC can vary 3.0 V to 3.8 V.
2. Outputs are terminated through a 50 W resistor to LVCC − 2.0 V.
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3
MC100LVEL92
Table 5. AC CHARACTERISTICS (VCC = 5.0 V; LVCC = 3.3 V; GND = 0 V (Note 1))
−40°C
Symbol
Characteristic
Min
fmax
Maximum Toggle Frequency
tPLH
tPHL
Propagation Delay
Diff
D to Q
S.E.
25°C
Typ
Max
Min
TBD
85°C
Typ
Max
Min
TBD
Typ
Max
Unit
GHz
TBD
490
590
690
510
610
710
530
630
730
440
590
740
460
610
760
480
630
780
20
20
25
100
200
20
20
25
100
200
20
20
25
100
200
ps
tSKEW
Skew
Output-to-Output (Note 2)
Part-to-Part (Diff) (Note 2)
Duty Cycle (Diff) (Note 3)
tJITTER
Cycle-to-Cycle Jitter
VPP
Input Swing (Note 4)
150
1000
150
1000
150
1000
mV
Output Rise/Fall Times Q
(20% − 80%)
270
530
270
530
270
530
ps
tr
tf
TBD
TBD
ps
ps
TBD
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. LVCC can vary 3.0 V to 3.8 V; VCC can vary 4.5 V to 5.5 V. Outputs are terminated through a 50ĂW resistor to LVCC − 2.0 V.
2. Skews are valid across specified voltage range, part-to-part skew is for a given temperature.
3. Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.
4. VPP(min) is the minimum input swing for which AC parameters are guaranteed. The device has a DC gain of ≈40.
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
ECLinPS is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
DATE 22 APR 2015
SCALE 1:1
A
20
q
X 45 _
M
E
h
0.25
H
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
b
0.25
M
T A
S
B
DIM
A
A1
b
c
D
E
e
H
h
L
q
S
L
A
18X
e
SEATING
PLANE
A1
c
T
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
20
20X
20X
1.30
0.52
20
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
11
1
11.00
1
XXXXX
A
WL
YY
WW
G
10
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
98ASB42343B
SOIC−20 WB
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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