MC74HC541A
Octal 3-State Noninverting
Buffer/Line Driver/Line
Receiver
High–Performance Silicon–Gate CMOS
The MC74HC541A is identical in pinout to the LS541. The device
inputs are compatible with Standard CMOS outputs. External pull–up
resistors make them compatible with LSTTL outputs.
The HC541A is an octal noninverting buffer/line driver/line
receiver designed to be used with 3–state memory address drivers,
clock drivers, and other bus–oriented systems. This device features
inputs and outputs on opposite sides of the package and two ANDed
active–low output enables.
The HC541A is similar in function to the HC540A, which has
inverting outputs.
•
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2 to 6V
Low Input Current: 1 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 134 FETs or 33.5 Equivalent Gates
VCC OE2
20
19
Y1
18
Y2
17
Y3
16
Y4
15
Y5
14
Y6
13
Y7
12
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MARKING
DIAGRAMS
20
MC74HC541AN
AWLYYWW
1
PDIP–20
N SUFFIX
CASE 783
20
HC541A
AWLYYWW
1
SO–20
DW SUFFIX
CASE 751D
Y8
11
20
1
1
2
3
4
5
6
7
8
9
10
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
HC541A
ALYW
TSSOP–20
DT SUFFIX
CASE 948E
Figure 1. Pinout: 20–Lead Packages (Top View)
A
L, WL
Y, YY
W, WW
FUNCTION TABLE
Inputs
Assembly Location
Wafer Lot
Year
Work Week
Output Y
OE1
OE2
A
L
L
H
X
L
L
X
H
L
H
X
X
ORDERING INFORMATION
L
H
Z
Z
Device
Semiconductor Components Industries, LLC, 2001
Package
Shipping
PDIP–20
1440/Box
MC74HC541ADW
SOIC–WIDE
38/Rail
MC74HC541ADWR2
SOIC–WIDE
1000/Reel
MC74HC541ADT
TSSOP–20
75/Rail
MC74HC541ADTR2
TSSOP–20
2500/Reel
MC74HC541AN
X = Don’t Care
Z = High Impedance
May, 2001 – Rev. 3
=
=
=
=
1
Publication Order Number:
MC74HC541A/D
MC74HC541A
A1
A2
A3
Data
Inputs
A4
A5
A6
A7
A8
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
Output OE1 1
Enables OE2
19
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
PIN 20 = VCC
PIN 10 = GND
Figure 2. Logic Diagram
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2
Noninverting
Outputs
MC74HC541A
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Value
Unit
0.5 to 7.0
V
0.5 VI 0.5
V
0.5 VO 0.5
V
VCC
DC Supply Voltage
VI
DC Input Voltage
VO
DC Output Voltage
IIK
DC Input Diode Current
20
mA
IOK
DC Output Diode Current
35
mA
IO
DC Output Sink Current
35
mA
ICC
DC Supply Current per Supply Pin
75
mA
IGND
DC Ground Current per Ground Pin
75
mA
TSTG
Storage Temperature Range
65 to 150
C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature under Bias
JA
Thermal Resistance
PD
Power Dissipation in Still Air at 85C
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ESD Withstand Voltage
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
> 4000
> 300
> 1000
V
ILatch–Up
Latch–Up Performance
Above VCC and Below GND at 85C (Note 6)
300
mA
(Note 2)
260
C
150
C
PDIP
SOIC
TSSOP
67
96
128
C/W
PDIP
SOIC
TSSOP
750
500
450
mW
Level 1
Oxygen Index: 30% – 35%
UL–94–VO (0.125 in)
1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated
conditions is not implied.
2. IO absolute maximum rating must be observed.
3. Tested to EIA/JESD22–A114–A.
4. Tested to EIA/JESD22–A115–A.
5. Tested to JESD22–C101–A.
6. Tested to EIA/JESD78.
7. For high frequency or heavy load considerations, see the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage
(Referenced to GND)
2.0
6.0
V
VIN, VOUT
DC Input Voltage, Output Voltage
(Referenced to GND)
0
VCC
V
TA
Operating Temperature Range, All Package Types
55
125
C
tr, tf
Input Rise/Fall Time
(Figure 3)
0
0
0
1000
500
400
ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
8. Unused inputs may not be left open. All inputs must be tied to a high–logic voltage level or a low–logic input voltage level.
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3
MC74HC541A
DC CHARACTERISTICS (Voltages Referenced to GND)
VCC
Symbol
Parameter
Condition
Guaranteed Limit
V
55C to 25C
85C
125C
Unit
VIH
Minimum High–Level Input
Voltage
VOUT = 0.1 V
|IOUT| ≤ 20 A
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL
Maximum Low–Level Input
Voltage
VOUT = VCC – 0.1 V
|IOUT| ≤ 20 A
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
VOH
Minimum High–Level Output
Voltage
VIN = VIL
|IOUT| ≤ 20 A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
|IOUT| ≤ 3.6 mA
|IOUT| ≤ 6.0 mA
|IOUT| ≤ 7.8 mA
VIN = VIL
VOL
Maximum Low–Level Output
Voltage
VIN = VIH
|IOUT| ≤ 20 A
|IOUT| ≤ 3.6 mA
|IOUT| ≤ 6.0 mA
|IOUT| ≤ 7.8 mA
VIN = VIH
V
IIN
Maximum Input Leakage Current
VIN = VCC or GND
6.0
0.1
1.0
1.0
A
IOZ
Maximum Three–State Leakage
Current
Output in High Impedance State
VIN = VIL or VIH
VOUT = VCC or GND
6.0
0.5
5.0
10.0
A
ICC
Maximum Quiescent Supply
Current (per Package)
VIN = VCC or GND
IOUT = 0 A
6.0
4
40
160
A
9. Information on typical parametric values can be found in the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
VCC
Symbol
Parameter
Guaranteed Limit
V
55C to 25C
85C
125C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 3 and 5)
2.0
3.0
4.5
6.0
80
30
18
15
100
40
23
20
120
55
28
25
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)
2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)
2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 3 and 5)
2.0
3.0
4.5
6.0
60
22
12
10
75
28
15
13
90
34
18
15
ns
CIN
Maximum Input Capacitance
10
10
10
pF
COUT
Maximum Three–State Output Capacitance (High Impedance State Output)
15
15
15
pF
10. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High–Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD
Power Dissipation Capacitance (Per Buffer) (Note 11)
35
11. Used to determine the no–load dynamic power consumption: P D = CPD VCC
Semiconductor High–Speed CMOS Data Book (DL129/D).
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4
2f
pF
+ ICC VCC . For load considerations, see the ON
MC74HC541A
tf
tr
VCC
90%
INPUT A
50%
10%
GND
tPHL
tPLH
90%
50%
10%
OUTPUT Y
tTHL
tTLH
Figure 3. Switching Waveform
VCC
OE1 or OE2
50%
50%
GND
tPZL
tPLZ
OUTPUT Y
HIGH
IMPEDANCE
50%
10%
tPZH
VOL
tPHZ
VOH
90%
OUTPUT Y
50%
HIGH
IMPEDANCE
Figure 4. Switching Waveform
TEST
POINT
TEST
POINT
OUTPUT
OUTPUT
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CL *
*Includes all probe and jig capacitance
1 k
CL *
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ and tPZH.
*Includes all probe and jig capacitance
Figure 5. Test Circuit
Figure 6. Test Circuit
PIN DESCRIPTIONS
device functions as an non–inverting buffer. When a high
voltage is applied to either input, the outputs assume the high
A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8, 9)
impedance state.
Data input pins. Data on these pins appear in non–inverted
form on the corresponding Y outputs, when the outputs are
OUTPUTS
enabled.
INPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11)
CONTROLS
Device outputs. Depending upon the state of the output
enable pins, these outputs are either non–inverting outputs
or high–impedance outputs.
OE1, OE2 (PINS 1, 19)
Output enables (active–low). When a low voltage is
applied to both of these pins, the outputs are enabled and the
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5
MC74HC541A
To 7 Other Buffers
VCC
One of Eight
Buffers
INPUT A
OUTPUT Y
OE1
OE2
Figure 7. Logic Detail
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6
MC74HC541A
PACKAGE DIMENSIONS
PDIP
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738–03
ISSUE E
–A–
20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
M
–T–
J
K
SEATING
PLANE
20 PL
0.25 (0.010)
N
E
G
F
D
M
T B
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0
15
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0
15
0.51
1.01
20 PL
0.25 (0.010)
M
T A
M
SO–20
DW SUFFIX
CASE 751D–05
ISSUE F
A
20
X 45
h
1
10
20X
B
B
0.25
M
T A
S
B
S
A
L
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
11
B
M
D
18X
e
A1
SEATING
PLANE
C
T
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7
DIM
A
A1
B
C
D
E
e
H
h
L
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0
7
MC74HC541A
PACKAGE DIMENSIONS
TSSOP
DT SUFFIX
20 PIN PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X
0.15 (0.006) T U
2X
K REF
0.10 (0.004)
S
M
20
L/2
T U
V
S
K
K1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
11
J J1
B
–U–
L
PIN 1
IDENT
1
0.15 (0.006) T U
S
SECTION N–N
10
0.25 (0.010)
N
S
M
A
–V–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
N
F
DETAIL E
–W–
C
D
G
H
DETAIL E
0.100 (0.004)
–T– SEATING
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0
8
PLANE
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MC74HC541A/D