NB6L72MMNG

NB6L72M 2.5V / 3.3V Differential 2 X 2 Crosspoint Switch with CML Outputs Multi−Level Inputs w/ Internal Termination Description http://onsemi.com MARKING DIAGRAM* 1 1 QFN−16 MN SUFFIX CASE 485G 16 NB6L 72M ALYWG G The NB6L72M is a high−bandwidth fully differential 2 x 2 Crosspoint Switch with internal source termination and CML output structure, optimized for low skew and minimal jitter.. The differential inputs incorporate internal 50 W termination resistors and will accept LVPECL, CML, LVDS, LVCMOS, or LVTTL logic levels. The SELECT inputs are single −ended and can be driven with LVCMOS/LVTTL. The 16 mA differential CML outputs provide matching internal 50 W terminations and 400 mV output swings when externally terminated with a 50 W resistor to VCC. The device is offered in a small 3 mm x 3 mm 16−pin QFN package. The NB6L72M is a member of the ECLinPS MAX™ family of high performance products. Features • • • • • • • • • • Maximum Input Clock Frequency > 3.0 GHz Maximum Input Data Rate > 5 Gb/s 360 ps Typical Propagation Delay 65 ps Typical Rise and Fall Times Differential CML Outputs, 400 mV peak−to−peak, typical Operating Range: VCC = 2.375 V to 3.63 V with GND = 0 V Internal Input and Output Termination Resistors, 50 W Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices −40°C to +85°C Ambient Operating Temperature These are Pb−Free Devices A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. © Semiconductor Components Industries, LLC, 2007 January, 2007 − Rev. 1 1 Publication Order Number: NB6L72M/D NB6L72M VTD0 D0 D0 D1 D1 50 W VTD1 SEL0 75 kW 2 SEL1 75 kW 2 50 W 2 2 2 Q1 Q1 VCC GND 2 2 50 W 50 W 2 2 2 Q0 Q0 + Figure 1. Logic/Block Diagram http://onsemi.com 2 NB6L72M GND 16 SEL0 D0 D0 VTD0 1 2 NB6L72M 3 4 5 VTD1 6 D1 7 D1 8 SEL1 10 9 Q1 GND Q0 15 Q0 14 VCC 13 12 11 VCC Q1 Exposed Pad (EP) Table 1. INPUT/OUTPUT SELECT TRUTH TABLE SEL0* L H L H SEL1* L L H H Q0 D0 D1 D0 D1 Q1 D0 D0 D1 D1 *Defaults LOW when left open Figure 2. Pin Configuration (Top View) Table 2. PIN DESCRIPTION Pin 1 2 Name SEL0 D0 I/O LVTTL,LVCMOS Input LVPECL, CML, LVDS, LVTTL, LVCMOS, Input LVPECL, CML, LVDS, LVTTL, LVCMOS, Input − − LVPECL, CML, LVDS, LVTTL, LVCMOS, Input LVPECL, CML, LVDS, LVTTL, LVCMOS, Input LVTTL,LVCMOS Input − CML Output CML Output − − CML Output CML Output − − Description Select Logic Input control that selects D0 or D1 to output Q0. See Table 1, Select Input Function Table. Pin defaults LOW when left open Noninverted Differential Input. Note 1 3 D0 Inverted Differential Input. Note 1 4 5 6 VTD0 VTD1 D1 Internal 50 W Termination Pin. Note 1. Internal 50 W termination pin. Note 1. Noninverted Differential Input. Note 1. 7 D1 Inverted Differential Input. Note 1 8 9 10 11 12 13 14 15 16 − SEL1 GND Q1 Q1 VCC VCC Q0 Q0 GND EP Select Logic Input control that selects D0 or D1 to output Q1. See Table 1, Select Input Function Table. Pin defaults LOW when left open Negative Supply Voltage Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC. Positive Supply Voltage Positive Supply Voltage Inverted Differential Reset Input. Typically Terminated with 50 W Resistor to VCC. Noninverted Differential Reset Input. Typically Terminated with 50 W Resistor to VCC. Negative Supply Voltage The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to GND on the PC board. 1. In the differential configuration when the input termination pin (VTDn, VTDn) are connected to a common termination voltage or left open, and if no signal is applied on Dn/Dn input, then the device will be susceptible to self−oscillation. 2. All VCC and GND pins must be externally connected to a power supply for proper operation. http://onsemi.com 3 NB6L72M Table 3. ATTRIBUTES Characteristics ESD Protection Moisture Sensitivity Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test For additional information, see Application Note AND8003/D. Human Body Model Machine Model 16−QFN Oxygen Index: 28 to 34 Value > 2 kV > 200V Level 1 UL 94 V−0 @ 0.125 in Table 4. MAXIMUM RATINGS Symbol VCC VIO VINPP IIN IOUT TA Tstg qJA qJC Tsol Parameter Positive Power Supply Positive Input/Output Voltage Differential Input Voltage |D − D| Static Surge Continuous Surge QFN−16 Condition 1 GND = 0 V GND = 0 V −0.5 v VIo v VCC + 0.5 Condition 2 Rating 4.0 4.0 2.8 45 80 25 50 −40 to +85 −65 to +150 0 lfpm 500 lfpm (Note 3) QFN−16 QFN−16 QFN−16 42 35 4 265 Unit V V V mA mA mA mA °C °C °C/W °C/W °C/W °C Input Current Through RT (50 W Resistor) Output Current (CML Output) Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 3) Thermal Resistance (Junction−to−Case) Wave Solder Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 4 NB6L72M Table 5. DC CHARACTERISTICS, Multi−Level Inputs VCC = 2.375 V to 3.63 V, GND = 0 V, TA = −40°C to +85°C Symbol POWER SUPPLY CURRENT ICC VOH Power Supply Current (Inputs and Outputs Open) 60 80 105 mA Characteristic Min Typ Max Unit CML OUTPUTS (Notes 5 and 6) Output HIGH Voltage VCC = 3.3 V VCC = 2.5 V VCC = 3.3 V VCC = 2.5 V VCC − 40 3260 2460 VCC − 500 2800 2000 VCC − 10 3290 2490 VCC − 400 2900 2100 VCC 3300 2500 VCC − 300 3000 2200 mV VOL Output LOW Voltage mV DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figures 6 and 8) Vth VIH VIL VISE VIHD VILD VID VCMR IIH IIL VIH VIL IIH IIL RTIN RTOUT Input Threshold Reference Voltage Range (Note 7) Single−Ended Input HIGH Voltage Single−Ended Input LOW Voltage Single−Ended Input Voltage Amplitude (VIH − VIL) Differential Input HIGH Voltage Differential Input LOW Voltage Differential Input Voltage Swing (Dn, Dn) (VIHD − VILD) (Note 15) Input Common Mode Range (Differential Configuration) (Note 9) Input HIGH Current Dn/Dn, (VTDn/VTDn Open) Input LOW Current Dn/Dn, (VTDn/VTDn Open) 1125 Vth + 75 GND 150 VCC − 75 VCC Vth − 75 2800 mV mV mV mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figures 7 and 9) (Note 8) 1200 GND 150 1125 −10 −50 VCC VCC − 150 2800 VCC – 75 50 10 mV mV mV mV mA mA SINGLE−ENDED LVCMOS/LVTTL CONTROL INPUTS Single−Ended Input HIGH Voltage Single−Ended Input LOW Voltage Input HIGH Current Input LOW Current 2000 GND −10 −150 VCC 800 10 0 mV mV mA mA TERMINATION RESISTORS Internal Input Termination Resistor Internal Output Termination Resistor 40 40 50 50 60 60 W W NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. CML outputs loaded with 50 W to VCC for proper operation. 5. Input and output parameters vary 1:1 with VCC. 6. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously. 7. Vth is applied to the complementary input when operating in single−ended mode. 8. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 9. VCMR minimum varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 5 NB6L72M Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.63 V, GND = 0 V, or VCC = 0 V, GND = −2.375 V to −3.63 V, TA = −40°C to +85°C; (Note 10) Symbol VOUTPP tPLH, tPHL tSKEW Characteristic Output Voltage Amplitude (@ VINPPmin) (Note 15) (See Figure 4) Propagation Delay (@0.5GHz) Duty Cycle Skew (Note 11) Within Device Skew Device to Device Skew (Note 12) Output Clock Duty Cycle (Reference Duty Cycle = 50%) RMS Random Clock Jitter (Note 13) Peak−to−Peak Data Dependent Jitter (Note 14) Input Voltage Swing/Sensitivity (Differential Configuration) (Note 15) Output Rise/Fall Times @ 0.5 GHz, (20% − 80%), Q, Q fin ≤ 3.0 GHz fin ≤ 3.0 GHz fin = 2.5 Gb/s fin = 3.0 Gb/s 150 65 40 fin ≤ 3 GHz Dn to Qn SELn to Qn Min 250 230 Typ 380 360 480 20 25 85 60 0.5 15 25 2800 120 Max Unit mV ps ps 6.0 50 0.2 5.0 8.0 tDC tJITTER % ps VINPP tr, tf mV ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Measured by forcing VINPP (minimum) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps (20% − 80%). 11. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5GHz. 12. Device to device skew is measured between outputs under identical transition @ 0.5 GHz. 13. Additive RMS jitter with 50% duty cycle clock signal. 14. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS23. 15. Input and output voltage swing is a single−ended measurement operating in differential mode. http://onsemi.com 6 NB6L72M VTD 50 W D VCC RC RC I D 50 W VTD Figure 3. Input Structure VIH Vth VIL D VCC Vthmax VIHmax VILmax VIH Vth VIL VIHmin VILmin Vth D Vth Vthmin GND Figure 4. Differential Input Driven Single−Ended Figure 5. Vth Diagram D D D D VID = |VIHD(D) − VILD(D)| VIHD VILD Figure 6. Differential Inputs Driven Differentially Figure 7. Differential Inputs Driven Differentially VCC VIHD(MAX) VILD(MAX) D D VINPP = VIH(D) − VIL(D) VCMR VIHD VID = VIHD − VILD VILD VIHD(MIN) Q Q tPD VOUTPP = VOH(Q) − VOL(Q) tPD GND VILD(MIN) Figure 8. VCMR Diagram Figure 9. AC Reference Measurement http://onsemi.com 7 NB6L72M VCC VCC VCC VCC ZO = 50 W LVPECL Driver VT = VCC − 2 V ZO = 50 W NB6L72M D 50 W 50 W D LVDS Driver ZO = 50 W VT = Open ZO = 50 W NB6L72M D 50 W 50 W D GND GND GND GND Figure 10. LVPECL Interface Figure 11. LVDS Interface VCC VCC ZO = 50 W CML Driver VT = VCC ZO = 50 W NB6L72M D 50 W 50 W D GND GND Figure 12. Standard 50 W Load CML Interface VCC VCC VCC VCC ZO = 50 W Differential Driver VT = VREFAC* ZO = 50 W NB6L72M D 50 W 50 W D Single−Ended Driver ZO = 50 W VT = VREFAC* NB6L72M D 50 W 50 W D (Open) GND Figure 13. Capacitor−Coupled Differential Interface (VT Connected to VREFAC) GND GND Figure 14. Capacitor−Coupled Single−Ended Interface (VT Connected to VREFAC) GND *VREFAC bypassed to ground with a 0.01 mF capacitor http://onsemi.com 8 NB6L72M VCC VOUTPP OUTPUT VOLTAGE AMPLITUDE (mV) (TYPICAL) 400 300 50 W 50 W Q 200 Q 100 0 0 1 2 3 GND 16 mA fout, CLOCK OUTPUT FREQUENCY (GHz) Figure 15. Output Voltage Amplitude (VOUTPP) versus Output Frequency at Ambient Temperature (Typical) VTT Figure 16. CML Output Structure 50 W Z = 50 W DUT Driver Device Q Z = 50 W Q 50 W D Receiver Device D Figure 17. Typical CML Termination for Output Driver and Device Evaluation ORDERING INFORMATION Device NB6L72MMNG NB6L72MMNR2G Package QFN−16 (Pb−free) QFN−16 (Pb−free) Shipping † 123 Units / Rail 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 9 NB6L72M PACKAGE DIMENSIONS 16 PIN QFN MN SUFFIX CASE 485G−01 ISSUE C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG DIM A A1 A3 b D D2 E E2 e K L MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 D A B PIN 1 LOCATION 0.15 C 0.15 C 0.10 C 16 X 0.08 C 16X L NOTE 5 4 16X K 1 16 16X 13 b BOTTOM VIEW 0.10 C A B 0.05 C NOTE 3 ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Japan : ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. ÇÇ ÇÇ TOP VIEW (A3) SIDE VIEW D2 5 E A A1 SEATING PLANE C SOLDERING FOOTPRINT* e 8 EXPOSED PAD 9 0.575 0.022 E2 e 3.25 0.128 0.30 0.012 EXPOSED PAD 12 3.25 0.128 1.50 0.059 0.50 0.02 0.30 0.012 SCALE 10:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 10 NB6L72M/D