NB7V72MMNG

NB7V72M 1.8V / 2.5V Differential 2 x 2 Crosspoint Switch with CML Outputs Clock/Data Buffer/Translator Multi−Level Inputs w/ Internal Termination Description http://onsemi.com MARKING DIAGRAM* 1 16 NB7V 72M ALYWG G The NB7V72M is a high bandwidth, low voltage, fully differential 2 x 2 crosspoint switch with CML outputs. The NB7V72M design is optimized for low skew and minimal jitter as it produces two identical copies of Clock or Data operating up to 5 GHz or 6.5 Gb/s, respectively. As such, the NB7V72M is ideal for SONET, GigE, Fiber Channel, Backplane and other clock/data distribution applications. The differential IN/IN inputs incorporate internal 50 W termination resistors and will accept LVPECL, CML, or LVDS logic levels (see Figure 10). The 16 mA differential CML outputs provide matching internal 50 W terminations and produce 400 mV output swings when externally terminated with a 50 W resistor to VCC (see Figure 11). The NB7V72M is the 1.8 V/2.5 V CML version of the NB7L72M and is offered in a low profile 3x3 mm 16−pin QFN package. Application notes, models, and support documentation are available at www.onsemi.com. The NB7V72M is a member of the GigaComm™ family of high performance clock products. Features 1 QFN−16 MN SUFFIX CASE 485G A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. + SEL0 IN0 VT0 IN0 0 1 Q0 Q0 • • • • • • • • • • • • Maximum Input Data Rate > 6.5 Gb/s Data Dependent Jitter < 15 ps pk−pk Maximum Input Clock Frequency > 5 GHz Random Clock Jitter < 0.8 ps RMS, Max 150 ps Typical Propagation Delay 30ps Typical Rise and Fall Times Differential CML Outputs, 400 mV peak−to−peak, typical Operating Range: VCC = 1.71 V to 2.625 V with GND = 0 V Internal 50 W Input Termination Resistors QFN−16 Package, 3mm x 3mm −40°C to +85°C Ambient Operating Temperature These are Pb−Free Devices IN1 VT1 IN1 SEL1 + 0 1 Q1 Q1 Figure 1. Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. © Semiconductor Components Industries, LLC, 2009 October, 2009 − Rev. 1 1 Publication Order Number: NB7V72M/D NB7V72M VT0 16 IN0 IN0 IN1 IN1 1 2 NB7V72M 3 4 5 VT1 6 7 8 VCC 10 9 Q1 Q1 SEL0 GND VCC 15 14 13 12 11 Q0 Q0 Exposed Pad (EP) Table 1. INPUT/OUTPUT SELECT TRUTH TABLE SEL0* L L H H SEL1* L H L H Q0 IN0 IN0 IN1 IN1 Q1 IN0 IN1 IN0 IN1 *Defaults HIGH when left open SEL1 GND Figure 2. Pin Configuration (Top View) Table 2. PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 − Name IN0 IN0 IN1 IN1 VT1 SEL1 GND VCC Q1 Q1 Q0 Q0 VCC GND SEL0 VT0 EP − CML Output CML Output CML Output CML Output − − LVCMOS Input − − I/O LVPECL, CML, LVDS Input LVPECL, CML, LVDS Input LVPECL, CML, LVDS Input LVPECL, CML, LVDS Input − LVCMOS Input Noninverted Differential Input. (Note 1) Inverted Differential Input. (Note 1) Inverted Differential Input. (Note 1) Noninverted Differential Input. (Note 1) Internal 50 W Termination Pin for IN1 and IN1 Input Select logic pin for IN0 or IN1 Inputs to Q1 output. See Table 1, Input/Output Select Truth Table; pin defaults HIGH when left open. Negative Supply Voltage Positive Supply Voltage Noninverted Differential Output. (Note 1) Inverted Differential Output. (Note 1) Inverted Differential Output. (Note 1) Noninverted Differential Output. (Note 1) Positive Supply Voltage Negative Supply Voltage Input Select logic pin for IN0 or IN1 Inputs to Q0 output. See Table 1, Input/Output Select Truth Table; pin defaults HIGH when left open. Internal 50 W Termination Pin for IN0 and IN0 The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to the die, and is recommended to be electrically and thermally connected to GND on the PC board. Description 1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and if no signal is applied on INx/INx input, then the device will be susceptible to self−oscillation. 2. All VCC and GND pins must be externally connected to a power supply for proper operation. http://onsemi.com 2 NB7V72M Table 3. ATTRIBUTES Characteristics ESD Protection RPU − Input Pullup Resistor Moisture Sensitivity Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test For additional information, see Application Note AND8003/D. 16−QFN Oxygen Index: 28 to 34 Human Body Model Machine Model Value > 4 kV > 200 V 75kΩ Level 1 UL 94 V−0 @ 0.125 in 210 Table 4. MAXIMUM RATINGS Symbol VCC VIN VINPP IIN TA Tstg qJA qJC Tsol Positive Power Supply Positive Input Voltage Differential Input Voltage |IN − IN| Input Current Through RT (50 Ω Resistor) Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 3) Thermal Resistance (Junction−to−Case) (Note 3) Wave Solder Pb−Free 0 lfpm 500 lfpm QFN−16 QFN−16 QFN−16 Parameter Condition 1 GND = 0 V GND = 0 V Condition 2 Rating 3.0 −0.5 to VCC +0.5 1.89 $40 −40 to +85 −65 to +150 42 35 4 265 Unit V V V mA °C °C °C/W °C/W °C/W °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB7V72M Table 5. DC CHARACTERISTICS, Multi−Level Inputs VCC = 1.71 V to 2.625 V, GND = 0 V, TA = −40°C to +85°C (Note 4) Symbol POWER SUPPLY CURRENT ICC Power Supply Current (Inputs and Outputs Open) VCC = 2.5 V VCC = 1.8 V 120 80 145 110 170 140 mA Characteristic Min Typ Max Unit CML OUTPUTS VOH Output HIGH Voltage (Note 5) VCC = 2.5 V VCC = 1.8 V VCC = 2.5 V VCC = 1.8 V VCC – 40 2460 1760 VCC – 650 1850 1150 VCC – 20 2480 1780 VCC – 400 2100 1400 VCC 2500 1800 VCC – 300 2200 1500 mV VOL Output LOW Voltage (Note 5) mV DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Note 6) (Figures 5 and 7) Vth VIH VIL VISE VIHD VILD VID VCMR IIH IIL VIH VIL IIH IIL RTIN RTOUT Input Threshold Reference Voltage Range (Note 7) Single−Ended Input HIGH Voltage Single−Ended Input LOW Voltage Single−Ended Input Voltage (VIH − VIL) Differential Input HIGH Voltage (INn, INn) Differential Input LOW Voltage (INn, INn) Differential Input Voltage (INn, INn) (VIHD − VILD) Input Common Mode Range (Differential Configuration, Note 9) (Figure 9) Input HIGH Current INn, INn (VTIN/VTIN Open) Input LOW Current INn, INn (VTIN/VTIN Open) 1050 Vth + 100 GND 200 VCC − 100 VCC Vth − 100 VCC − GND VCC VCC − 100 1200 VCC − 50 150 150 mV mV mV mV DIFFERENTIAL DATA/CLOCK INPUTS DRIVEN DIFFERENTIALLY (Figures 6 and 8) (Note 8) 1100 GND 100 1050 −150 −150 mV mV mV mV mA mA CONTROL INPUTS (SEL0, SEL1) Input HIGH Voltage for Control Pins Input LOW Voltage for Control Pins Input HIGH Current Input LOW Current VCC x 0.65 GND −150 −150 20 5 VCC VCC x 0.35 150 150 mV mV mA mA TERMINATION RESISTORS Internal Input Termination Resistor Internal Output Termination Resistor 40 40 50 50 60 60 W W NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Input and output parameters vary 1:1 with VCC. 5. CML outputs loaded with 50 W to VCC for proper operation. 6. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously. 7. Vth is applied to the complementary input when operating in single−ended mode. 8. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 9. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 NB7V72M Table 6. AC CHARACTERISTICS VCC = 1.71 V to 2.625 V; GND = 0 V; TA = −40°C to 85°C (Note 10) Symbol fMAX fDATAMAX VOUTPP tPLH, tPHL tPLH TC tSKEW tDC tjitter VINPP tr,, tf Characteristic Maximum Input Clock Frequency Maximum Operating Data Rate (PRBS23) Output Voltage Amplitude (@ VINPPmin) fin ≤ 5 GHz (See Figures 3 and 10, Note 11) Propagation Delay to Differential Outputs, @ 1GHz, Measured at Differential Cross−point Propagation Delay Temperature Coefficient Output−to−Output Skew (within device) (Note 12) Device−to−Device Skew (tpdmax – tpdmin) Output Clock Duty Cycle (Reference Duty Cycle = 50%) fin v 5GHz RJ – Output Random Jitter (Note 13) fin v 5 GHz DJ – Deterministic Jitter (Note 14) v9 Gbps Input Voltage Swing (Differential Configuration) (Note 15) Output Rise/Fall Times @ 1 GHz (20% − 80%), Qn, Qn 100 20 30 45 50 0.5 INn/INn to Qn/Qn VCC = 2.5 V VCC = 1.8 V Min 5 4.5 6.5 200 110 400 150 50 30 50 55 0.8 10 1200 50 200 Typ Max Unit GHz Gbps mV ps Dfs/°C ps % ps RMS ps pk−pk mV ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Measured using a 400 mV source, 50% duty cycle clock source. All output loading with external 50 W to VCC. Input edge rates w40 ps (20% − 80%). 11. Output voltage swing is a single−ended measurement operating in differential mode. 12. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when the delays are measured from cross−point of the inputs to the cross−point of the outputs. 13. Additive RMS jitter with 50% duty cycle clock signal. 14. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23. 15. Input voltage swing is a single−ended measurement operating in differential mode. 500 OUTPUT VOLTAGE AMPLITUDE (mV) 450 Q AMP (mV) 400 350 INn 300 250 200 VTn 50 W INn 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 fin, Clock Input Frequency (GHz) 50 W VCC Figure 3. CLOCK Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typ) Figure 4. Input Structure http://onsemi.com 5 NB7V72M VIH Vth VIL IN Vth IN IN IN Figure 5. Differential Input Driven Single−Ended Figure 6. Differential Inputs Driven Differentially VCC Vthmax VIHmax VILmax VIH Vth VIL VIHmin VILmin VID = |VIHD(IN) − VILD(IN)| VIHD VILD Vth Vthmin GND IN IN Figure 7. Vth Diagram VCC VCMmax IN VCMR IN VCMmin GND VIHDmax VILDmax VIHDtyp VID = VIHD − VILD VILDtyp VIHDmin VILDmin IN IN Q Q Figure 8. Differential Inputs Driven Differentially VINPP = VIH(IN) − VIL(IN) VOUTPP = VOH(Q) − VOL(Q) tPHL tPLH Figure 9. VCMR Diagram Figure 10. AC Reference Measurement NB7V72M VCC Receiver VCC (Receiver) 50 W 50 W Q 50 W Q 50 W 16 mA GND Figure 11. Typical CML Output Structure and Termination http://onsemi.com 6 NB7V72M VCC 50 W Z = 50 W DUT Driver Device Q Z = 50 W Q 50 W D Receiver Device D Figure 12. Typical Termination for CML Output Driver and Device Evaluation VCC VCC VCC VCC ZO = 50 W LVPECL Driver VT = VCC − 2 V ZO = 50 W NB7V72M IN 50 W 50 W IN LVDS Driver ZO = 50 W VT = Open ZO = 50 W NB7V72M IN 50 W 50 W IN GND VCC Figure 13. LVPECL Interface GND VCC GND VCC Figure 14. LVDS Interface GND VCC ZO = 50 W CML Driver VT = VCC ZO = 50 W NB7V72M IN 50 W 50 W IN Differential Driver ZO = 50 W VT = VREFAC* ZO = 50 W IN IN NB7V72M 50 W 50 W GND GND GND Figure 15. Standard 50 W Load CML Interface *VREFAC bypassed to ground with a 0.01 mF capacitor Figure 16. Capacitor−Coupled Differential Interface (VT Connected to External VREFAC) GND ORDERING INFORMATION Device NB7V72MMNG NB7V72MMNHTBG NB7V72MMNTXG Package QFN−16 (Pb−free) QFN−16 (Pb−free) QFN−16 (Pb−free) Shipping† 123 Units / Rail 100 / Tape & Reel 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 7 NB7V72M PACKAGE DIMENSIONS 16 PIN QFN CASE 485G−01 ISSUE D D A B L L1 DETAIL A L PIN 1 LOCATION E EXPOSED Cu ALTERNATE TERMINAL CONSTRUCTIONS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG 0.15 C 0.15 C TOP VIEW A1 0.10 C DETAIL B (A3) A ALTERNATE CONSTRUCTIONS DETAIL B 16 X 0.08 C SIDE VIEW A1 C SEATING PLANE 16X L DETAIL A 5 4 D2 8 e EXPOSED PAD 9 NOTE 5 0.575 0.022 16X K 1 16 16X 13 E2 12 e 3.25 0.128 b BOTTOM VIEW 0.50 0.02 0.30 0.012 SCALE 10:1 mm inches 0.10 C A B 0.05 C NOTE 3 GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC). *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 8 ÇÇ ÇÇ ÉÉ ÉÉ ÉÉ ÉÉ ÇÇÇ ÇÇÇ ÇÇÇ MOLD CMPD A3 DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 0.00 0.15 SOLDERING FOOTPRINT* 3.25 0.128 0.30 0.012 EXPOSED PAD 1.50 0.059 NB7V72M/D