NB7L72MMNG

NB7L72M 2.5V / 3.3V Differential 2 x 2 Crosspoint Switch with CML Outputs Clock/Data Buffer/Translator Multi−Level Inputs w/ Internal Termination Description http://onsemi.com MARKING DIAGRAM* 1 1 QFN−16 MN SUFFIX CASE 485G 16 NB7L 72M ALYWG G The NB7L72M is a high bandwidth, low voltage, fully differential 2 x 2 crosspoint switch with CML outputs. The NB7L72M design is optimized for low skew and minimal jitter as it produces two identical copies of Clock or Data operating up to 7 GHz or 10 Gb/s, respectively. As such, the NB7L72M is ideal for SONET, GigE, Fiber Channel, Backplane and other clock/data distribution applications. The differential IN/IN inputs incorporate internal 50 W termination resistors and will accept LVPECL, CML, or LVDS logic levels (see Figure 11). The 16 mA differential CML outputs provide matching internal 50 W terminations and produce 400 mV output swings when externally terminated with a 50 W resistor to VCC (see Figure 9). The NB7L72M is the 2.5 V/3.3 V version of the and NB7V72M and is offered in a low profile 3x3 mm 16−pin QFN package. Application notes, models, and support documentation are available at www.onsemi.com. The NB7L72M is a member of the GigaComm™ family of high performance clock products. Features A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. + SEL0 IN0 VT0 IN0 0 1 Q0 Q0 • • • • • • • • • • • • Maximum Input Data Rate > 10 Gb/s Data Dependent Jitter < 10 ps pk−pk Maximum Input Clock Frequency > 7 GHz Random Clock Jitter < 0.5 ps RMS, Max 150 ps Typical Propagation Delay 30 ps Typical Rise and Fall Times Differential CML Outputs, 400 mV peak−to−peak, typical Operating Range: VCC = 2.375 V to 3.6 V with GND = 0 V Internal 50 W Input Termination Resistors QFN−16 Package, 3mm x 3mm −40°C to +85°C Ambient Operating Temperature These are Pb−Free Devices IN1 VT1 IN1 SEL1 + 0 1 Q1 Q1 Figure 1. Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. © Semiconductor Components Industries, LLC, 2008 September, 2008 − Rev. 1 1 Publication Order Number: NB7L72M/D NB7L72M VT0 16 IN0 IN0 IN1 IN1 1 2 NB7L72M 3 4 5 VT1 6 7 8 VCC 10 9 Q1 Q1 SEL0 GND VCC 15 14 13 12 11 Q0 Q0 Exposed Pad (EP) Table 1. INPUT/OUTPUT SELECT TRUTH TABLE SEL0* L L H H SEL1* L H L H Q0 IN0 IN0 IN1 IN1 Q1 IN0 IN1 IN0 IN1 *Defaults HIGH when left open SEL1 GND Figure 2. Pin Configuration (Top View) Table 2. PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 − Name IN0 IN0 IN1 IN1 VT1 SEL1 GND VCC Q1 Q1 Q0 Q0 VCC GND SEL0 VT0 EP − CML Output CML Output CML Output CML Output − − LVCMOS Input − − I/O LVPECL, CML, LVDS Input LVPECL, CML, LVDS Input LVPECL, CML, LVDS Input LVPECL, CML, LVDS Input − LVCMOS Input Noninverted Differential Input. (Note 1) Inverted Differential Input. (Note 1) Inverted Differential Input. (Note 1) Noninverted Differential Input. (Note 1) Internal 50 W Termination Pin for IN1 and IN1. Input Select logic pin for IN0 or IN1 Inputs to Q1 output. See Table 1, Input/Output Select Truth Table; pin defaults HIGH when left open. Negative Supply Voltage Positive Supply Voltage Noninverted Differential Output. (Note 1) Inverted Differential Output. (Note 1) Inverted Differential Output. (Note 1) Noninverted Differential Output. (Note 1) Positive Supply Voltage Negative Supply Voltage Input Select logic pin for IN0 or IN1 Inputs to Q0 output. See Table 1, Input/Output Select Truth Table; pin defaults HIGH when left open. Internal 50 W Termination Pin for IN0 and IN0 The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to the die, and is recommended to be electrically and thermally connected to GND on the PC board. Description 1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and if no signal is applied on INx/INx input, then the device will be susceptible to self−oscillation. 2. All VCC and GND pins must be externally connected to a power supply for proper operation. http://onsemi.com 2 NB7L72M Table 3. ATTRIBUTES Characteristics ESD Protection RPU − Input Pullup Resistor Moisture Sensitivity (Note 3) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. QFN−16 Oxygen Index: 28 to 34 Human Body Model Machine Model Value > 4 kV > 200 V 75 kW Level 1 UL 94 V−0 @ 0.125 in 212 Table 4. MAXIMUM RATINGS Symbol VCC VIN VINPP IIN IOUT TA Tstg qJA qJC Tsol Positive Power Supply Positive Input Voltage Differential Input Voltage |IN − IN| Input Current Through RT (50 W Resistor) Output Current Through RT (50 W Resistor) Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 4) Thermal Resistance (Junction−to−Case) (Note 4) Wave Solder Pb−Free 0 lfpm 500 lfpm QFN−16 QFN−16 QFN−16 Parameter Condition 1 GND = 0 V GND = 0 V Condition 2 Rating 4.0 −0.5 to VCC +0.5 1.89 $40 $40 −40 to +85 −65 to +150 42 35 4 265 Unit V V V mA mA °C °C °C/W °C/W °C/W °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB7L72M Table 5. DC CHARACTERISTICS, Multi−Level Inputs VCC = 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C (Note 5) Symbol POWER SUPPLY CURRENT VCC ICC VOH Power Supply Voltage Power Supply Current (Inputs and Outputs Open) VCC = 2.5 V VCC = 3.3 V 2.375 3.0 80 2.5 3.3 135 2.625 3.6 175 V mA Characteristic Min Typ Max Unit CML OUTPUTS Output HIGH Voltage (Note 6) VCC = 3.3 V VCC = 2.5 V VCC = 3.3 V VCC = 2.5 V VCC – 40 3260 2460 VCC – 650 2650 VCC – 600 1900 VCC – 20 3280 2480 VCC – 500 2800 VCC – 500 2000 VCC 3300 2500 VCC – 400 2900 VCC – 350 2150 mV VOL Output LOW Voltage (Note 6) mV DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Note 7) (Figures 5 and 7) Vth VIH VIL VISE VIHD VILD VID VCMR IIH IIL VIH VIL IIH IIL RTIN RTOUT Input Threshold Reference Voltage Range (Note 8) Single−Ended Input HIGH Voltage Single−Ended Input LOW Voltage Single−Ended Input Voltage (VIH − VIL) Differential Input HIGH Voltage (INn, INn) Differential Input LOW Voltage (INn, INn) Differential Input Voltage (INn, INn) (VIHD − VILD) Input Common Mode Range (Differential Configuration, Note 10) (Figure 9) Input HIGH Current INn, INn (VTIN/VTIN Open) Input LOW Current INn, INn (VTIN/VTIN Open) 1050 Vth + 100 GND 200 VCC − 100 VCC Vth − 100 2800 mV mV mV mV DIFFERENTIAL DATA/CLOCK INPUTS DRIVEN DIFFERENTIALLY (Figures 6 and 8) (Note 9) 1100 GND 100 950 −150 −150 VCC VCC − 100 1200 VCC − 50 150 150 mV mV mV mV mA mA CONTROL INPUTS (SEL0, SEL1) Input HIGH Voltage for Control Pins Input LOW Voltage for Control Pins Input HIGH Current Input LOW Current 2.0 GND −150 −150 VCC 0.8 150 150 mV mV mA mA TERMINATION RESISTORS Internal Input Termination Resistor Internal Output Termination Resistor 40 40 50 50 60 60 W W NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. 6. CML outputs loaded with 50 W to VCC for proper operation. 7. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously. 8. Vth is applied to the complementary input when operating in single−ended mode. 9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 NB7L72M Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V; GND = 0 V; TA = −40°C to 85°C (Note 11) Symbol fMAX fDATAMAX VOUTPP tPLH, tPHL tPLH TC tSKEW tDC tjitter VINPP tr,, tf Characteristic Maximum Input Clock Frequency Maximum Operating Data Rate (PRBS23) Output Voltage Amplitude (@ VINPPmin) (See Figures 3 and 10, Note 12) Propagation Delay to Differential Outputs, @ 1GHz, Measured at Differential Cross−point Propagation Delay Temperature Coefficient Output−to−Output Skew (within device) (Note 13) Device−to−Device Skew (tpdmax – tpdmin) Output Clock Duty Cycle (Reference Duty Cycle = 50%) fin v 8.5GHz RJ – Output Random Jitter (Note 14) DJ – Deterministic Jitter (Note 15) Input Voltage Swing (Differential Configuration) (Note 16) Output Rise/Fall Times @ 1 GHz (20% − 80%), Q, Q fin v 8.5 GHz v 10 Gbps 100 25 30 45 50 0.2 fin ≤ 8.5 GHz INn/INn to Qn/Qn SELn to Qn/Qn VOUT w 250 mV VOUT w 200 mV Min 7.0 8.5 10 200 110 400 150 50 10 20 55 0.5 10 1200 50 180 Typ Max Unit GHz Gbps mV ps Dfs/°C ps % ps RMS ps pk−pk mV ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Measured using a 400 mV source, 50% duty cycle clock source. All output loading with external 50 W to VCC. Input edge rates w40 ps (20% − 80%). 12. Output voltage swing is a single−ended measurement operating in differential mode. 13. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when the delays are measured from cross−point of the inputs to the cross−point of the outputs. 14. Additive RMS jitter with 50% duty cycle clock signal. 15. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23. 16. Input voltage swing is a single−ended measurement operating in differential mode. 500 OUTPUT VOLTAGE AMPLITUDE (mV) 450 Q AMP (mV) 400 350 INn 300 VTn 250 200 INn 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 fin, Clock Input Frequency (GHz) 50 W 50 W VCC Figure 3. CLOCK Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typ) Figure 4. Input Structure http://onsemi.com 5 NB7L72M VIH Vth VIL IN Vth IN IN IN Figure 5. Differential Input Driven Single−Ended Figure 6. Differential Inputs Driven Differentially VCC Vthmax VIHmax VILmax VIH Vth VIL VIHmin VILmin VID = |VIHD(IN) − VILD(IN)| VIHD VILD Vth Vthmin GND IN IN Figure 7. Vth Diagram VCC VCMmax VIHDmax VILDmax IN VCMR IN VCMmin GND VIHDtyp VID = VIHD − VILD VILDtyp VIHDmin VILDmin IN IN Q Q Figure 8. Differential Inputs Driven Differentially VINPP = VIH(IN) − VIL(IN) VOUTPP = VOH(Q) − VOL(Q) tPHL tPLH Figure 9. VCMR Diagram Figure 10. AC Reference Measurement NB7L72M VCC Receiver VCC (Receiver) 50 W 50 W Q Q 50 W 50 W 16 mA GND Figure 11. Typical CML Output Structure and Termination http://onsemi.com 6 NB7L72M VCC 50 W Z = 50 W DUT Driver Device Q Z = 50 W Q 50 W D Receiver Device D Figure 12. Typical Termination for CML Output Driver and Device Evaluation VCC VCC VCC VCC ZO = 50 W LVPECL Driver VT = VCC − 2 V ZO = 50 W NB7L72M IN 50 W 50 W IN LVDS Driver ZO = 50 W VT = Open ZO = 50 W NB7L72M IN 50 W 50 W IN GND VCC Figure 13. LVPECL Interface GND VCC GND Figure 14. LVDS Interface GND VCC VCC ZO = 50 W CML Driver VT = VCC ZO = 50 W NB7L72M IN 50 W 50 W IN Differential Driver ZO = 50 W VT = VREFAC* ZO = 50 W IN IN NB7L72M 50 W 50 W GND GND GND Figure 15. Standard 50 W Load CML Interface *VREFAC bypassed to ground with a 0.01 mF capacitor Figure 16. Capacitor−Coupled Differential Interface (VT Connected to External VREFAC) GND ORDERING INFORMATION Device NB7L72MMNG NB7L72MMNR2G Package QFN−16 (Pb−free) QFN−16 (Pb−free) Shipping† 123 Units / Rail 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 7 NB7L72M PACKAGE DIMENSIONS 16 PIN QFN MN SUFFIX CASE 485G−01 ISSUE C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG DIM A A1 A3 b D D2 E E2 e K L MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 D A B PIN 1 LOCATION 0.15 C 0.15 C 0.10 C 16 X 0.08 C SIDE VIEW A1 C 16X L NOTE 5 4 16X K 1 16 16X 13 b BOTTOM VIEW 0.10 C A B 0.05 C NOTE 3 GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Phone : 303−675−2175 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Phone : 81−3−5773−3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. ÇÇ ÇÇ TOP VIEW (A3) D2 5 E A SEATING PLANE SOLDERING FOOTPRINT* e 8 EXPOSED PAD 9 0.575 0.022 E2 e 3.25 0.128 0.30 0.012 EXPOSED PAD 12 3.25 0.128 1.50 0.059 0.50 0.02 0.30 0.012 SCALE 10:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 NB7L72M/D