NB7L216MNR2

NB7L216 2.5V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Translator with Internal Termination Description http://onsemi.com MARKING DIAGRAM* The NB7L216 is a differential receiver/driver with high gain output targeted for high frequency applications. The device is functionally equivalent to the NBSG16 but with much higher gain output. This highly versatile device provides 35 dB of gain up to 7 GHz. Inputs incorporate internal 50 W termination resistors and accept Negative ECL (NECL), Positive ECL (PECL), LVTTL, LVCMOS, CML, or LVDS. Outputs are Reduced Swing ECL (RSECL), 400 mV. The VBB pin is an internally generated voltage supply available to this device only. VBB is used as a reference voltage for single−ended NECL or PECL inputs. For all single−ended input conditions, the unused complementary differential input should be connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB output should be left open. Application notes, models and support documentation are available at www.onsemi.com. Features 16 1 QFN−16 MN SUFFIX CASE 485G NB7L 216 ALYWG G A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. VTD 50 W D D 50 W VTD Q Q VOLTAGE (60 mV/div) • • • • • • • • • • • • • • • High Gain of 35 dB from DC to 7 GHz Typical High IIP3: 0 dBm Typical 20 mV Minimum Input Voltage Swing Maximum Input Clock Frequency up to 8.5 GHz Maximum Input Data Rate up to 12 Gb/s Typical 10 V > 4 kV Pb−Free Pkg Level 1 Moisture Sensitivity (Note 2) UL 94 V−0 @ 0.125 in 164 Table 3. MAXIMUM RATINGS (Note 3) Symbol VCC VEE VI VINPP IIN IOUT IBB TA Tstg qJA qJC Tsol Parameter Positive Power Supply Negative Power Supply Positive Input Negative Input Differential Input Voltage |D − D| Static Surge Continuous Surge Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V VI = VCC VI = VEE Condition 2 Rating 3.6 −3.6 3.6 −3.6 2.8 45 80 25 50 ± 0.5 −40 to +85 −65 to +150 0 lfpm 500 lfpm 1S2P (Note 4) QFN−16 QFN−16 QFN−16 42 35 4 265 265 Unit V V V V V mA mA mA mA mA °C °C °C/W °C/W °C/W °C Input Current Through RT (50 W Resistor) Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 4) Thermal Resistance (Junction−to−Case) Wave Solder Pb Pb−Free Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 3. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. 4. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB7L216 Table 4. DC CHARACTERISTICS, CLOCK INPUTS, CML OUTPUTS VCC = 2.375 V to 3.465 V, VEE = 0 V −40 5C Symbol IEE VOH VOL Characteristic Power Supply Current (VTD/VTD open) Output HIGH Voltage (Note 5 and 6) Output LOW Voltage (Note 5 and 6) VCC −1040 VCC −1520 Min Typ 27 VCC −980 VCC −1430 Max 35 VCC −940 VCC −1320 VCC −1000 VCC −1470 Min 25 5C Typ 27 VCC −950 VCC −1370 Max 35 VCC −900 VCC −1270 VCC –950 VCC –1440 Min 85 5C Typ 27 VCC −900 VCC −1340 Max 35 VCC −850 VCC −1240 Unit mA mV mV DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figures 14 and 16) VTH VIH VIL Input Threshold Reference Voltage Range (Note 7 and 8) Single−ended Input HIGH Voltage (Note 8) Single−ended Input LOW Voltage (Note 8) 1100 Vth +10 VEE VCC −10 VCC Vth −10 1100 Vth + 10 VEE VCC −10 VCC Vth −10 1100 Vth +10 VEE VCC −10 VCC Vth −10 mV mV mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figures 15 and 17) VIHD VILD VCMR Differential Input HIGH Voltage (Note 9) Differential Input LOW Voltage (Note 9) Input Common Mode Range (Differential Configuration, Note 9 and 10) Differential Input Voltage (VIHD − VILD) Input Offset Voltage (Note 11) Internally Generated Reference Voltage Supply (Only 3 V – 3.6 V Supply Load with −100 mA) Input HIGH Current D/Db (VTD/VTD Open) Input LOW Current D/Db (VTD/VTD Open) Internal Input Termination Resistor Internal Input Termination Resistor Temperature Coefficient 1105 VEE 1100 VCC VCC −10 VCC −5 2500 0 VCC −1345 +5 VCC −1265 1105 VEE 1100 VCC VCC −10 VCC –5 2500 0 VCC −1345 +5 VCC −1265 1105 VEE 1100 VCC VCC −10 VCC –5 2500 0 VCC −1345 +5 VCC −1265 mV mV mV VID VIO VBB 10 −5 VCC −1425 10 −5 VCC −1425 10 −5 VCC −1425 mV mV mV IIH IIL RTIN RT_Coef 0 −25 45 20 10 50 6.38 100 75 55 0 −25 45 20 10 50 6.38 100 75 55 0 −25 45 20 10 50 6.38 100 75 55 mA mA W mW/°C NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Outputs evaluated with 50 W resistors to VTT = VCC − 2.0 V for proper operation. 6. Input and output parameters vary 1:1 with VCC. 7. VTH is applied to the complementary input when operating in single−ended mode. 8. VIH, VIL and VTH parameters must be complied simultaneously. 9. VIHD, VILD and VCMR parameters must be complied simultaneously. 10. VCMR min varies 1:1 with VEE, VCMR max varies 1:1 with VCC. 11. Typical standard deviation of input offset voltage is 1.76 mV. http://onsemi.com 4 NB7L216 Table 5. AC CHARACTERISTICS VCC = 2.375 V to 3.465 V, VEE = 0 V; (Note 12) −40°C Symbol VOUTPP fDATA |S21| |S11| |S22| |S12| IIP3 tPLH, tPHL tSKEW tJITTER Characteristic Output Voltage Amplitude (@ VINPPmin)fin ≤ 7.0 GHz (See Figure 4) fin ≤ 8.5 GHz Maximum Operating Data Rate Power Gain DC to 7 GHz Input Return Loss @ 7 GHz Output Return Loss @ 7 GHz Reverse Isolation (Differential Configuration) Input Third Order Intercept Propagation Delay to Output Differential @ 1 GHz Duty Cycle Skew (Note 12) Device to Device Skew (Note 17) RMS Random Clock Jitter fin v 8.5 GHz (Note 15) Peak−to−Peak Data Dependent Jitter (Note 16) fDATA = 3.5 Gb/s fDATA = 5.0 Gb/s fDATA = 10 Gb/s fDATA = 12 Gb/s Input Voltage Swing/Sensitivity (Differential Configuration) (Note 14 and Figure 12) Output Rise/Fall Times @ 0.5 GHz (20% − 80%) Q, Q 20 30 60 Min 275 100 10 Typ 380 250 12 35 −10 −5 −25 0 120 2 5 0.1 1 3 4 4 180 10 20 0.5 7 9 9 9 2500 45 20 30 60 Max Min 275 100 10 25°C Typ 380 250 12 35 −10 −5 −25 0 120 2 5 0.1 1 3 4 4 180 10 20 0.5 7 9 9 9 2500 45 20 30 60 Max Min 275 100 10 85°C Typ 380 250 12 35 −10 −5 −25 0 120 2 5 0.1 1 3 4 4 180 10 20 0.5 7 9 9 9 2500 45 mV ps Max Unit mV Gb/s dB dB dB dB dBm ps ps ps VINPP tr tf NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 12. Measured by forcing VINPPmin from a 50% duty cycle clock source. All loading with an external RL = 50 W to VTT =VCC − 2.0 V. Input edge rates 40 ps (20% − 80%). 13. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 1 GHz. 14. VINPP (MAX) cannot exceed VCC − VEE. Input voltage swing is a single−ended measurement operating in differential mode. 15. Additive RMS jitter with 50% duty cycle clock signal. 16. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS 223−1. 17. Device to device skew is measured between outputs under identical transition @ 1 GHz. OUTPUT VOLTAGE AMPLITUDE (mV) OUTPUT VOLTAGE AMPLITUDE (mV) 500 450 400 350 300 250 200 150 100 50 0 0 2 4 6 7 8 9 10 INPUT CLOCK FREQUENCY (GHz) 11 12 85°C 25°C −40°C 500 450 400 350 300 250 200 150 100 50 0 0 2 4 6 7 8 9 10 INPUT CLOCK FREQUENCY (GHz) 11 12 85°C 25°C −40°C Figure 4. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fIN) and Temperature (VINPP = 400 mV, VCC = 3.3 V and VEE = 0 V) Figure 5. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fIN) and Temperature (VINPP = 20 mV, VCC = 3.3 V and VEE = 0 V) http://onsemi.com 5 NB7L216 VOLTAGE (60 mV/div) Device DDJ = 1 ps VOLTAGE (60 mV/div) Device DDJ =1 ps TIME (66 ps/div) TIME (54 ps/div) Figure 6. Typical Output Waveform at 2.488 Gb/s with PRBS 223−1 (VINPP = 400 mV, Input Signal DDJ = 12 ps) Figure 7. Typical Output Waveform at 3.5 Gb/s with PRBS 223−1 (VINPP = 400 mV, Input Signal DDJ = 12 ps) VOLTAGE (60 mV/div) Device DDJ =2 ps VOLTAGE (60 mV/div) Device DDJ = 3 ps TIME (37 ps/div) TIME (21 ps/div) Figure 8. Typical Output Waveform at 5 Gb/s with PRBS 223−1 (VINPP = 400 mV, Input Signal DDJ = 12 ps) Figure 9. Typical Output Waveform at 10 Gb/s with PRBS 223−1 (VINPP = 400 mV, Input Signal DDJ = 12 ps) 40 35 30 GAIN (dB) GAIN (dB) 25 20 15 10 0 −10 −20 S22 S11 −30 −40 5 0 0 2 4 6 8 10 12 14 16 FREQUENCY (GHz) −50 0 2 4 6 8 10 FREQUENCY (GHz) 12 14 16 Figure 10. Small Signal Gain – S21 Magnitude* Figure 11. Input and Output Reflection – S11 and S22 Magnitude* *TA = +25°C, VCC = 3.3 V, VEE=0 V, PIN = −44 dBm,ZS = ZL = 50 W, input and output matching network is not included. http://onsemi.com 6 NB7L216 Table 6. TYPICAL DEVICE S−PARAMETERS Frequency (Hz) 4.97E+08 1.02E+09 1.51E+09 2.00E+09 2.52E+09 3.01E+09 3.50E+09 4.02E+09 4.51E+09 4.99E+09 5.48E+09 6.01E+09 6.49E+09 6.98E+09 7.51E+09 7.99E+09 8.52E+09 9.00E+09 9.49E+09 1.00E+10 1.05E+10 1.10E+10 1.15E+10 1.20E+10 1.25E+10 1.30E+10 1.35E+10 1.40E+10 1.45E+10 1.50E+10 NOTE: S11 dbS11 −45.2 −30.4 −36.2 −27.4 −12.3 −10.6 −19.0 −10.6 −10.7 −9.0 −10.6 −9.3 −9.4 −17.5 −25.6 −13.7 −6.7 −5.2 −3.7 −9.7 −11.0 −8.3 −5.9 −9.0 −15.6 −15.1 −12.0 −11.5 −17.0 −23.4 |S11| 0.005 0.030 0.015 0.042 0.244 0.295 0.112 0.294 0.291 0.354 0.294 0.341 0.340 0.133 0.053 0.206 0.462 0.552 0.652 0.326 0.283 0.384 0.506 0.356 0.166 0.175 0.250 0.265 0.140 0.068 íS11 −88.5 −134.7 −146.5 25.7 −27.7 −83.8 −22.1 −120.3 167.4 87.1 62.7 108.2 59.4 25.5 107.9 146.5 117.9 106.2 71.1 46.2 35.8 7.2 −0.4 −23.8 −46.9 −83.0 −96.5 −105.9 −97.8 −108.9 dbS21 37.2 37.3 37.1 37.4 36.2 36.9 35.4 35.6 36.0 35.1 36.4 35.8 36.2 34.3 33.2 25.2 22.6 19.4 19.0 18.7 14.5 12.9 12.7 12.9 10.5 9.9 8.7 7.3 5.4 4.6 S21 |S21| 72.799 73.145 71.433 74.061 64.810 70.102 58.933 60.437 62.843 56.576 65.812 61.327 64.212 52.039 45.861 18.093 13.434 9.336 8.937 8.595 5.298 4.408 4.339 4.395 3.360 3.121 2.728 2.314 1.856 1.695 íS21 −33.2 −68.4 −105.4 −139.0 −179.5 144.5 99.9 73.8 41.1 14.2 −16.1 −72.8 −119.4 −141.5 164.6 133.6 116.2 102.0 61.1 18.6 −13.3 −9.6 −33.7 −63.4 −97.8 −119.7 −148.9 −167.1 167.6 145.0 dbS12 −72.3 −45.8 −43.3 −37.1 −29.9 −26.1 −28.3 −24.8 −22.5 −25.2 −24.3 −24.5 −21.9 −22.7 −24.4 −21.5 −19.4 −19.0 −19.4 −24.0 −25.9 −29.4 −21.4 −19.4 −21.0 −24.0 −22.0 −18.6 −20.1 −20.2 S12 |S12| 0.001 0.005 0.007 0.014 0.032 0.050 0.038 0.058 0.075 0.055 0.061 0.060 0.080 0.073 0.060 0.084 0.107 0.112 0.107 0.063 0.051 0.034 0.085 0.107 0.089 0.063 0.079 0.118 0.099 0.098 íS12 −139.1 129.8 98.5 91.8 54.4 9.4 25.9 −32.6 −68.3 −107.2 −121.4 −125.7 −152.4 177.5 165.7 152.8 120.7 109.9 62.0 50.6 12.9 21.1 36.3 −9.5 −39.0 −39.9 −39.1 −74.2 −107.0 −128.1 dbS22 −2.5 −2.9 −2.9 −3.5 −4.4 −6.3 −5.0 −7.6 −13.9 −8.7 −8.0 −8.0 −12.5 −7.4 −7.0 −7.6 −12.1 −12.2 −11.5 −10.4 −10.8 −13.4 −21.4 −13.4 −12.4 −11.3 −14.9 −18.4 −15.7 −11.2 S22 |S22| 0.749 0.714 0.717 0.666 0.599 0.485 0.566 0.417 0.201 0.367 0.398 0.397 0.237 0.428 0.445 0.416 0.249 0.246 0.267 0.301 0.288 0.213 0.085 0.214 0.239 0.272 0.181 0.120 0.163 0.274 íS22 157.4 154.3 132.8 107.1 92.1 77.3 67.9 54.2 70.2 81.2 50.4 −0.9 −27.2 −32.2 −37.9 −54.7 −73.7 −62.5 −100.2 −117.0 −172.0 74.0 −148.6 159.5 169.2 171.6 177.8 140.3 98.2 96.1 TA = +25°C, VCC=3.3V, VEE = 0 V, PIN = −44 dBm, ZS = ZL = 50 W, input and output matching network is not included. http://onsemi.com 7 NB7L216 D VINPP = VIH(D) − VIL(D) D Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 12. AC Reference Measurement Q Driver Device Q Zo = 50 W D Receiver Device Zo = 50 W 50 W 50 W D VTT VTT = VCC − 2.0 V Figure 13. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) D Vth D D Vth D Figure 14. Differential Input Driven Single−Ended Figure 15. Differential Inputs Driven Differentially VCC Vthmax VCC VIHmax VILmax VIH Vth VIL VIHmin VILmin NOTE: VCMmax D D VCMmax GND VEE v VIN v VCC; VIH > VIL VIHDmax VILDmax VID = VIHD − VILD VIHDtyp VILDtyp VIHDmin VILDmin Vth VCMR D Vthmin GND Figure 16. Vth Diagram Figure 17. VCMR Diagram http://onsemi.com 8 NB7L216 APPLICATION INFORMATION All NB7L216 inputs can accept PECL, CML, LVTTL, LVCMOS and LVDS signal levels. The limitations for differential input signal (LVDS, PECL, or CML) are minimum input swing of 75 mV and the maximum input swing of 2500 mV. Within these conditions, the input voltage can range from VCC to 1.2 V. Examples interfaces are illustrated below in a 50 W environment (Z = 50 W). For output termination and interface, refer to application note AND8020/D. Table 7. INTERFACING OPTIONS Interfacing Options CML LVDS AC−COUPLED RSECL, PECL, NECL LVTTL, LVCMOS Connections Connect VTD and VTD to VCC (See Figure 18) Connect VTD and VTD Together (See Figure 20) Bias VTD and VTD Inputs within Common Mode Range (VCMR) (See Figure 19) Standard ECL Termination Techniques (See Figure 13) An External Voltage (VTHR) should be Applied to the Unused Complementary Differential Input. Nominal VTHR is 1.5 V for LVTTL and VCC / 2 for LVCMOS Inputs. This Voltage must be within the VTHR Specification. (See Figure 21) VCC VCC 50 W 50 W Q Z = 50 W VCC Z = 50 W VCC D VTD VTD D VEE 50 W 50 W NB7L216 CML Driver Q VEE Figure 18. CML to NB7L216 Interface VCC VCC Z = 50 W C D VBias* VTD VTD 50 W NB7L216 50 W PECL Driver Recommended RT Values VCC RT RT RT 5.0 V 290 W 3.3 V 150 W 2.5 V 80 W VEE VEE Z = 50 W VBias* C D VEE *VBias must be within common mode range limits (VCMR) Figure 19. PECL to NB7L216 Interface http://onsemi.com 9 NB7L216 VCC VCC Z = 50 W D VTD VTD 50 W NB7L216 LVDS Driver Z = 50 W 50 W D VEE VEE Figure 20. LVDS to NB7L216 Interface VCC VCC Z = 50 W D LVTTL/ LVCMOS Driver No Connect* No Connect VREF VTD 50 W NB7L216 VTD D 50 W Recommended VREF Values VREF LVCMOS VCC − VEE 2 VEE *or 60 pF to GND VCC LVTTL 1.5 V Figure 21. LVCMOS/LVTTL to NB7L216 Interface http://onsemi.com 10 NB7L216 ORDERING INFORMATION Device NB7L216MN NB7L216MNG NB7L216MNR2 NB7L216MNR2G Package QFN−16 QFN−16 (Pb−Free) QFN−16 QFN−16 (Pb−Free) Shipping † 123 Units / Rail 123 Units / Rail 3000 / Tape & Reel 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 11 NB7L216 PACKAGE DIMENSIONS 16 PIN QFN CASE 485G−01 ISSUE B D A B PIN 1 LOCATION E NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.20 −−− 0.30 0.50 0.15 C 0.15 C 0.10 C TOP VIEW 16 X 0.08 C SIDE VIEW A1 C 16X L 5 NOTE 5 4 16X K 1 12 16X 0.10 C A B 0.05 C NOTE 3 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative ÇÇÇ ÇÇÇ ÇÇÇ (A3) D2 e 8 9 16 13 A SEATING PLANE DIM A A1 A3 b D D2 E E2 e K L SOLDERING FOOTPRINT* 3.25 0.128 0.30 0.012 EXPOSED PAD 0.575 0.022 EXPOSED PAD E2 e 3.25 0.128 1.50 0.059 b BOTTOM VIEW 0.50 0.02 0.30 0.012 SCALE 10:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 12 NB7L216/D