NCN5121MNTWG

NCN5121 Transceiver for KNX Twisted Pair Networks Introduction NCN5121 is a receiver−transmitter IC suitable for use in KNX twisted pair networks (KNX TP1−256). It supports the connection of actuators, sensors, microcontrollers, switches or other applications in a building network. NCN5121 handles the transmission and reception of data on the bus. It generates from the unregulated bus voltage stabilized voltages for its own power needs as well as to power external devices, for example, a microcontroller. NCN5121 assures safe coupling to and decoupling from the bus. Bus monitoring warns the external microcontroller in case of loss of power so that critical data can be stored in time. • • • • • • • • • • • • • • • 9600 baud KNX Communication Speed Supervision of KNX Bus Voltage and Current Supports Bus Current Consumption up to 24 mA High Efficient DC−DC Converters ♦ 3.3 V Fixed ♦ 1.2 V to 21 V Selectable Control and Monitoring of Power Regulators Linear 20 V Regulator Buffering of Sent Data Frames (Extended Frames Supported) Selectable UART or SPI Interface to Host Controller Selectable UART and SPI baud Rate to Host Controller Optional CRC on UART to the Host Optional Received Frame−end with MARKER Service Optional Direct Analog Signaling to Host Operates with Industry Standard Low Cost 16 MHz Quartz Generates Clock of 8 or 16 MHz for External Devices Auto Acknowledge (optional) Auto Polling (optional) Temperature Monitoring Extended Operating Temperature Range −40°C to +105°C These Devices are Pb−Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2015 August, 2019 − Rev. 2 1 40 QFN40 MN SUFFIX CASE 485AU MARKING DIAGRAM Key Features • • • • www.onsemi.com 1 NCN5121 21420−005 AWLYYWWG A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 57 of this data sheet. Publication Order Number: NCN5121/D NCN5121 BLOCK DIAGRAM CEQ1 VBUS1 VFILT VDDA TRIG VDDD VSSD Bus Coupler SCK/UC2 UART Impedance Control KNX DLL Receiver SPI CCP TXO VSSA Interface Controller CAV CEQ2 SDI/RXD SDO/TXD CSB/UC1 TREQ Mode Transmitter MODE1 MODE2 VBUS2 FANIN VIN NCN5121 Fan−In Control DC/DC Converter 1 VSW1 VDD1M VDD1 VSS1 V20V 20V LDO RC OSC POR XTAL1 XTAL2 VSW2 OSC TW TSD DC/DC Converter 2 UVD VDD2MC VDD2MV VDD2 XSEL ANALOG BUFFER VSS2 Diagnostics XCLKC XCLK ANAOUT SAVEB RESETB Figure 1. Block Diagram NCN5121 31 32 33 34 35 36 37 38 1 30 2 29 3 28 4 27 5 26 NCN5121 6 25 20 19 18 17 VDDD SCK/UC2 SDO/TXD SDI/RXD CSB/UC1 TREQ MODE2 MODE1 TRIG XCLKC VIN VSW1 VSS1 VDD1 VDD1M VDD2MV VDD2MC VDD2 VSS2 VSW2 16 21 15 22 10 14 23 9 13 24 8 12 7 11 VSSA VBUS2 TXO CCP CAV VBUS1 CEQ1 CEQ2 VFILT V20V 39 40 VDDA ANAOUT FANIN RESETB SAVEB XTAL1 XTAL2 XSEL XCLK VSSD PIN OUT Figure 2. Pin Out NCN5121 (Top View) www.onsemi.com 2 NCN5121 PIN DESCRIPTION Table 1. PIN LIST AND DESCRIPTION Name Pin Description Type VSSA 1 Analog Supply Voltage Ground Supply VBUS2 2 Ground for KNX Transmitter Supply Equivalent Schematic TX0 3 KNX Transmitter Output Analog Output Type 1 CCP 4 AC coupling external capacitor connection Analog I/O Type 2 CAV 5 Capacitor connection to average bus DC voltage Analog I/O Type 3 VBUS1 6 KNX power supply input Supply Type 5 CEQ1 7 Capacitor connection 1 for defining equalization pulse Analog I/O Type 4 CEQ2 8 Capacitor connection 2 for defining equalization pulse Analog I/O Type 4 VFILT 9 Filtered bus voltage Supply Type 5 V20V 10 20V supply output Supply Type 5 VDD2MV 11 Voltage monitor of Voltage Regulator 2 Analog Input Type 8 VDD2MC 12 Current monitor input 1 of Voltage Regulator 2 Analog Input Type 9 VDD2 13 Current monitor input 2 of Voltage Regulator 2 Analog Input Type 8 VSS2 14 Voltage Regulator 2 Ground VSW2 15 Switch output of Voltage Regulator 2 Supply VIN 16 Voltage Regulator 1 and 2 Power Supply Input VSW1 17 Switch output of Voltage Regulator 1 VSS1 18 Voltage Regulator 1 Ground Analog Output Type 6 Supply Type 5 Analog Output Type 6 Supply VDD1 19 Current Input 2 and Voltage Monitor Input of Voltage Regulator 1 Analog Input Type 8 VDD1M 20 Current Monitor Input 1 of Voltage Monitor 1 Analog Input Type 9 XCLKC 21 Clock Frequency Configure Digital Input Type 12 TRIG 22 Transmission Trigger Output Digital Output Type 13 MODE1 23 Mode Selection Input 1 Digital Input Type 12 MODE2 24 Mode Selection Input 2 Digital Input Type 12 TREQ 25 Transmit Request Input Digital Input Type 12 CSB/UC1 26 Chip Select Output (SPI) or Configuration Input (UART) or 20 V LDO Disable (Analog Mode) Digital Output or Digital Input Type 13 or 14 SDI/RXD 27 Serial Data Input (SPI) or Receive Input (UART) Digital Input Type 14 SDO/TXD 28 Serial Data Output (SPI) or Transmit Output (UART) SCK/UC2 29 Serial Clock Output (SPI) or Configuration Input (UART) or Voltage Regulator 2 Disable (Analog Mode) VDDD 30 VSSD 31 XCLK 32 Oscillator Clock Output XSEL 33 Clock Selection (Quartz or Digital Clock) XTAL2 34 Clock Generator Output (Quartz) or Input (Digital Clock) XTAL1 35 Digital Output Type 13 Digital Output or Digital Input Type 13 or 14 Digital Supply Voltage Input Supply Type 7 Digital Supply Voltage Ground Supply Digital Output Type 13 Digital Input Type 12 Analog Output or Digital Input Type 10 or 14 Clock Generator Input (Quartz) Analog Input Type 10 SAVEB 36 Save Signal (open drain with pull−up) Digital Output Type 15 RESETB 37 Reset Signal (open drain with pull−up) Digital Output Type 15 FANIN 38 Fan−In Input Digital Input Type 11 ANAOUT 39 Analog Signal Output Analog Output Type 16 VDDA 40 Analog Supply Voltage Input Supply Type 7 NOTE: Type of CSB/UC1 and SCK/UC2 is depending on status MODE1 − MODE2 pin Type of XTAL1 and XTAL2 pin is depending on status XSEL pin. www.onsemi.com 3 NCN5121 EQUIVALENT SCHEMATICS Following figure gives the equivalent schematics of the user relevant inputs and outputs. The diagrams are simplified representations of the circuits used. CCP 60V CAV TXO CEQx 7V 60V 60V Type 1: TXO−pin Type 2: CCP−pin 60V Type 3: CAV−pin Type 4: CEQ1 and CEQ2−pin VIN VBUS1 VFILT V20V VDDD VIN VDDA 60V VBUS1 VFILT V20V VDDD VIN VDDA VSWx 60V 60V 60V 7V 60V Type 5: VBUS1−, VFILT−, V20V and VIN−pin 7V Type 7: VDDD− and VDDA−pin Type 6: VSW1 and VSW2−pin VDD1 VDD2 7V VDD1 VDD2 VDD2MV 7V VDD1M 60V 7V VDD2MC 60V 7V Type 8: VDD1−, VDD2− and VDD2MV−pin VDDD 7V Type 9: VDD1M− and VDD2MC−pin VAUX VDDD VDDD XTAL2 FANIN XTAL1 IN 7V Type 12: MODE1−, MODE2−, TREQ−, XCLKC− and XSEL−pin Type 11: FANIN−pin Type 10: XTAL1− and XTAL2−pin VDDD RDOWN VDDA VDDD VDDD RUP OUT IN Type 13: CSB/UC1−, SDO/TXD−, SCK/UC2−, TRIG− and XCLK−pin NOTE: ANAOUT OUT Type 14: CSB/UC1−, SDI/RXD−, SCK/UC2 and XTAL2−pin Type 15: RESETB− and SAVEB−pin Type of CSB/UC1 and SCK/UC2 is depending on status MODE1 − MODE2 pin Type of XTAL1 and XTAL2 pin is depending on status XSEL pin. Figure 3. In− and Output Equivalent Diagrams www.onsemi.com 4 Type 16: ANAOUT NCN5121 ELECTRICAL SPECIFICATION Table 2. ABSOLUTE MAXIMUM RATINGS (Notes 1 and 2) Symbol Parameter Min Max Unit −0.3 +45 V − 250 mA VTXO KNX Transmitter Output Voltage ITXO KNX Transmitter Output Current (Note 3) VCCP Voltage on CCP−pin −10.5 +14.5 V VCAV Voltage on CAV−pin −0.3 +3.6 V VBUS1 Voltage on VBUS1−pin −0.3 +45 V Voltage on ANAOUT pin −0.3 +3.6 V VANAOUT IBUS1 Current Consumption VBUS1−pin 0 120 mA VCEQ Voltage on pins CEQ1 and CEQ2 −0.3 +45 V VFILT Voltage on VFILT−pin −0.3 +45 V V20V Voltage on V20V−pin −0.3 +25 V VDD2MV Voltage on VDD2MV−pin −0.3 +3.6 V VDD2MC Voltage on VDD2MC−pin −0.3 +45 V VDD2 Voltage on VDD2−pin −0.3 +45 V VSW Voltage on VSW1− and VSW2−pin −0.3 +45 V VIN Voltage on VIN−pin −0.3 +45 V Voltage on VDD1−pin −0.3 +3.6 V Voltage on VDD1M−pin −0.3 +3.6 V VDIG Voltage on pins MODE1, MODE2, TREQ, CSB/UC1, SDI/TXD, SDO/RXD, SCK/ UC2, XCLK, XSEL, SAVEB, RESETB, XCLKC, TRIG, and FANIN −0.3 +3.6 V VDD Voltage on VDDD− and VDDA−pin −0.3 +3.6 V VXTAL Voltage on XTAL1− and XTAL2−pin −0.3 +3.6 V Storage temperature −55 +150 °C Junction Temperature (Note 4) −40 +155 °C Human Body Model electronic discharge immunity (Note 5) −2 +2 kV VDD1 VDD1M TST TJ VHBM Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Convention: currents flowing in the circuit are defined as positive. 2. VBUS2, VSS1, VSS2, VSSA and VSSD form the common ground. They are hard connected to the PCB ground layer. 3. Room temperature, 27 W shunt resistor for transmitter, 250 mA over temperature range. 4. Normal performance within the limitations is guaranteed up to the Thermal Warning level. Between Thermal Warning and Thermal Shutdown temporary loss of function or degradation of performance (which ceases after the disturbance ceases) is possible. 5. According to JEDEC JESD22−A114. www.onsemi.com 5 NCN5121 Recommend Operation Conditions Operating ranges define the limits for functional operation and parametric characteristics of the device. Note that the functionality of the chip outside these operating ranges is not guaranteed. Operating outside the recommended operating ranges for extended periods of time may affect device reliability. Table 3. OPERATING RANGES Symbol VBUS1 Parameter VBUS1 Voltage (Note 6) VDD Digital and Analog Supply Voltage (VDDD− and VDDA−pin) VIN Input Voltage DC−DC Converter 1 and 2 Min Max Unit +20 +33 V +3.13 +3.47 V (Note 7) +33 V VCCP Input Voltage at CCP−pin −10.5 +14.5 V VCAV Input Voltage at CAV−pin 0 +3.3 V VDD1 Input Voltage on VDD1−pin +3.13 +3.47 V Input Voltage on VDD1M−pin +3.13 +3.57 V VDD1M Input Voltage on VDD2−pin +1.2 +21 V VDD2MC VDD2 Input Voltage on VDD2MC−pin +1.2 +21.1 V VDD2MV Input Voltage on VDD2MV−pin +1.2 VDD V Input Voltage on pins MODE1, MODE2, TREQ, CSB/UC1, SDI/RXD, SCK/UC2, XCLKC, and XSEL 0 VDD V Input Voltage on FANIN−pin 0 3.6 V VDIG VFANIN fclk Clock Frequency External Quartz 16 MHz TA Ambient Temperature −40 +105 °C TJ Junction Temperature (Note 8) −40 +125 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 6. Voltage indicates DC value. With equalization pulse bus voltage must be between 11 V and 45 V. 7. Minimum operating voltage on VIN−pin should be at least 1 V larger than the highest value of VDD1 and VDD2. 8. Higher junction temperature can result in reduced lifetime. www.onsemi.com 6 NCN5121 Table 4. DC PARAMETERS The DC parameters are given for a device operating within the Recommended Operating Conditions unless otherwise specified. Convention: currents flowing in the circuit are defined as positive. Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit POWER SUPPLY VBUS1 Bus DC voltage Excluding active and equalization pulse 20 − 33 V Bus Current Consumption VBUS = 30 V, IBUS = 10 mA, DC2, V20V disabled, no crystal or clock − 2.00 2.70 mA Bus Current Consumption VBUS = 20 V, IBUS = 20 mA − 3.20 4.10 VBUSH Undervoltage release level VBUS1 rising, see Figure 4 17.1 18.0 18.9 V VBUSL Undervoltage trigger level VBUS1 falling, see Figure 4 15.9 16.8 17.7 V Undervoltage hysteresis 0.6 − − V VBUS1 IBUS1_Int VBUS_Hyst VDDD VDDD Digital Power Supply 3.13 3.3 3.47 V VDDA VDDA Analog Power Supply 3.13 3.3 3.47 V 2.8 3.3 3.6 V VAUX Auxiliary Supply Internal supply, for info only Bus Coupler Current Slope Limitation FANIN floating, VFILT > VFILTH − 0.40 0.50 A/s FANIN = 0, VFILT > VFILTH − 0.80 1.00 A/s Bus Coupler Startup Current Limitation FANIN floating, VFILT > VFILTH 20.0 25.0 30.0 mA FANIN = 0, VFILT > VFILTH 40.0 50.0 60.0 mA Bus Coupler Current Limitation FANIN floating, VFILT > VFILTH 10.6 11.4 12.0 mA FANIN = 0, VFILT > VFILTH 20.5 22.3 24.0 mA IBUS1 = 10 mA − 1.72 2.32 V IBUS1 = 20 mA − 2.34 2.80 V KNX BUS COUPLER DIcoupler/Dt Icoupler_lim, VBUS1 VBUS1 startup Icoupler_lim Vcoupler_drop VFILTH VBUS1 VBUS1, VFILT VFILT VFILTL Coupler Voltage Drop (Vcoupler_drop = VBUS1 − VFILT) Undervoltage release level VFILT rising, see Figure 5 10.1 10.6 11.2 V Undervoltage trigger level VFILT falling, see Figure 5 8.4 8.9 9.4 V Input Voltage 4.47 − 33 V Output Voltage 3.13 3.3 3.47 V − 40 − mV −100 − −200 mA 90 − % FIXED DC−DC CONVERTER VIN VIN VDD1 VDD1 VDD1_rip Output Voltage Ripple VIN = 25 V, IDD1 = 40 mA, L1 = 220 mH IDD1_lim Overcurrent Threshold R2 = 1 W, see Figure 13 Power Efficiency (DC Converter Only) Vin = 25 V, IDD1 = 35 mA, L1 = 220 mH (1.26 W ESR), see Figure 12 RDS(on)_p1 RDS(on) of power switch See Figure 18 − − 9 W RDS(on)_n1 RDS(on) of flyback switch See Figure 18 − − 4 W − − 3.57 V hVDD1 VDD1M VDD1M Input voltage VDD1M−pin www.onsemi.com 7 NCN5121 Table 4. DC PARAMETERS The DC parameters are given for a device operating within the Recommended Operating Conditions unless otherwise specified. Convention: currents flowing in the circuit are defined as positive. Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit VDD2 +1 − 33 V 1.2 − 21 V ADJUSTABLE DC−DC CONVERTER VIN VIN VDD2 VDD2 Input Voltage Output Voltage VIN ≥ VDD2 VDD2H Undervoltage release level VDD2 rising, see Figure 6 − 0.9 x VDD2 − V VDD2L Undervoltage trigger level VDD2 falling, see Figure 6 − 0.8 x VDD2 − V VDD2_rip Output Voltage Ripple VIN = 25 V, VDD2 = 3.3 V, IDD2 = 40 mA, L2 = 220 mH − 40 − mV IDD2_lim Overcurrent Threshold R3 = 1 W, see Figure 13 −100 − −250 mA Power Efficiency (DC Converter Only) Vin = 25 V, VDD2 = 3.3 V, IDD2 = 35 mA, L2 = 220 mH (1.26 W ESR), see Figure 13 − 90 − % RDS(on)_p2 RDS(on) of power switch See Figure 18 − − 8 W RDS(on)_n2 RDS(on) of flyback switch See Figure 18 − − 4 W hVDD2 VDD2M VDD2MC Input voltage VDD2MC−pin − − 21.1 V RVDD2M VDD2MV Input Resistance VDD2MV−pin 1 − − MW Half−bridge leakage − − 20 mA Ileak,vsw2 V20V REGULATOR V20V V20V Output Voltage I20V < I20V_lim, VFILT ≥ 21 V 18 20 22 V V20V Output Current Limitation Step FANIN floating − 1.25 − mA FANIN = 0 − 2.50 − mA V20V Output Current Limitation (for V20VCLIMIT[2:0] = 100) FANIN floating 6 7.5 9 mA FANIN = 0 12 15 18 mA V20VH V20V Undervoltage release level V20V rising, see Figure 7 14.2 15.0 15.8 V V20VL V20V Undervoltage trigger level V20V falling, see Figure 7 13.2 14.0 14.8 V V20V Undervoltage hysteresis V20V_hyst = V20VH – V20VL − 1.0 − V − − VDDD V 10 20 40 mA V20V DI20V, STEP I20V_lim V20V_hyst XTAL OSCILLATOR VXTAL XTAL1, XTAL2 Voltage on XTAL−pin FAN−IN CONTROL Ipu,fanin FANIN Pull−Up Current FANIN−pin FANIN shorted to GND, Pull−up connected to VAUX www.onsemi.com 8 NCN5121 Table 4. DC PARAMETERS The DC parameters are given for a device operating within the Recommended Operating Conditions unless otherwise specified. Convention: currents flowing in the circuit are defined as positive. Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit 0 − 0.7 V 2.65 − VDDD V 5 10 28 kW DIGITAL INPUTS VIL VIH RDOWN SCK/UC2, Logic Low Threshold SDI/RXD, CSB/UC1, Logic High Threshold TREQ, MODE1, Internal Pull−Down Resistor MODE2, XSEL, XCLKC, XTAL2 SCK/UC2−, SDI/RXD− and CSB/UC1 pin excluded. Only valid in Normal State. DIGITAL OUTPUTS Logic low output level 0 − 0.4 V VOH SCK/UC2, SDO/TXD, CSB/UC1, XCLK, TRIG Logic high output level VDDD − 0.45 − VDDD V IL SCK/UC2, XCLK, TRIG Load Current − − 8 mA − − 4 mA − − 0.4 V 20 40 80 kW VOL SDO/TXD, CSB/UC1 VOL Rup SAVEB, RESETB Logic low level open drain IOL = 4 mA Internal Pull−up Resistor ANALOG OUTPUT ANAOUT Analog output division ratio for VBUS 0.067 0.071 0.075 − PVFILT Analog output division ratio for VFILT 0.071 0.075 0.079 − PV20V Analog output division ratio for V20V 0.086 0.091 0.096 − PVDDA Analog output division ratio for VDDA 0.438 0.462 0.485 − PVDD2 Analog output division ratio for VDD2MV 0.950 1.000 1.050 − PIBUS Analog output conversion ratio for IBUS 14.0 20.9 28.8 V/A − −4 − mV/K PVBUS PTJ VTJOFF VOFF tSW,ANA Analog output conversion ratio for Tjunction Analog output offset for Tjunction at 300K Analog output offset voltage Time between writing Analog Control Register 1 and stable ANAOUT voltage ( t WDPR and < t WDTO WD Timer t t WDRD vt WDPR and wt WDTO t WDTO t WDPR t Comments: − WD Timer is an internal timer − tWDTO = − and are Watchdog Register bits Figure 9. Watchdog Timing Diagram CS ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ CLK DI DO tSDI_SET tSDI _HOLD tCS _SET tCS _HIGH t SDO_VALID tSCK _HIGH tSCK _LOW tSCK tCS_HOLD Figure 10. SPI Bus Timing Diagram CS CLK ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ DI DO LSB 1 Dummy 2 Dummy 7 Dummy ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ Dummy TREQ tTREQ_HOLD tTREQ _SET tTREQ _LOW tTREQ_HIGH Figure 11. TREQ Timing Diagram www.onsemi.com 13 NCN5121 TYPICAL APPLICATION SCHEMATICS RESETb SAVEb uC CLK C8 C9 3.3 3.3 VSSD 31 32 XTAL2 XTAL1 XSEL 33 34 35 SAVEB 36 RESETB 37 ANAOUT FANIN 38 19 C6 VDDD SCK/UC2 SDO/TXD TxD SDI/RXD CSB/UC1 RxD TREQ MODE2 MODE1 TRIG XCLKC 20 VDD1M 3.3 39 21 18 C7 10 VDD1 B C4 22 11 C3 23 9 VSS1 V20V 8 17 VFILT 24 16 CEQ2 25 7 VSW1 C2 6 15 D2 26 NCN5121 VIN CEQ1 27 5 14 VBUS1 4 VSW2 CAV 28 VSS2 C1 3 13 CCP 29 12 A 2 VDD2 TXO 40 VDDA VBUS2 R1 GND 3.3 30 VDD2MV D1 VCC 1 VDD2MC VSSA XCLK X1 C5 3.3 C10 L1 R2 Figure 12. Typical Application Schematic, 8−bit UART Mode (38400 bps), Single Supply, 20 mA Bus Current Limit and 1 mA/ms Bus Current Slopes, 8 MHz Microcontroller Clock Signal www.onsemi.com 14 NCN5121 TYPICAL APPLICATION SCHEMATICS RESETb SAVEb C8 3.3 3.3 X1 31 32 33 34 35 36 37 38 FANIN RESETB SAVEB XTAL1 XTAL2 XSEL XCLK VSSD 39 ANAOUT 4 27 5 26 NCN5121 6 25 23 9 22 10 21 B VDDD SCK/UC2 SDO/TXD SDI/RXD CSB/UC1 TREQ MODE2 MODE1 TRIG XCLKC VCC VCC2 C6 GND SCK SDO SDI SCB TREQ 20 8 19 24 18 7 17 C7 28 16 C4 3 15 C3 29 14 D2 2 13 C1 30 12 A 3.3 1 11 R1 V2 VDD2MV VDD2MC VDD2 VSS2 VSW2 VIN VSW1 VSS1 VDD1 VDD1M D1 40 VDDA C5 VSSA VBUS2 TXO CCP CAV VBUS1 CEQ1 C2 CEQ2 VFILT V20V uC CLK C9 3.3 C10 L2 R5 L1 R2 R4 R3 V2 C11 Figure 13. Typical Application Schematic, SPI (500 kbps), Dual Supply, 10 mA Bus Current Limit and 0.5 mA/ms Bus Current Slopes, 16 MHz Clock for Microcontroller www.onsemi.com 15 NCN5121 TYPICAL APPLICATION SCHEMATICS RESETb SAVEb 3.3 3.3 C5 XCLK VSSD 31 32 XSEL 33 XTAL2 34 SAVEB XTAL1 35 36 RESETB 37 FANIN 38 ANAOUT 39 C6 VDDD SCK/UC2 SDO/TXD TxD SDI/RXD CSB/UC1 RxD TREQ MODE2 MODE1 TRIG XCLKC 20 21 19 10 18 22 VDD1M 3.3 B 23 9 VDD1 C7 8 17 C4 24 11 C3 25 7 VSS1 V20V 6 VSW1 VFILT NCN5121 16 D2 CEQ2 26 15 C2 27 5 VIN CEQ1 4 14 VBUS1 28 VSW2 CAV 3 13 CCP C1 29 VSS2 A 2 VDD2 TXO 12 VBUS2 R1 30 VDD2MV D1 GND 3.3 1 VDD2MC VSSA 40 VDDA VCC 3.3 C10 L1 R2 Figure 14. Typical Application Schematic, Analog Mode, Single Supply, 20 mA Bus Current Limit and 1.0 mA/ms Bus Current Slopes, 8 MHz Clock Signal for Microcontroller www.onsemi.com 16 NCN5121 Table 6. EXTERNAL COMPONENTS LIST AND DESCRIPTION Comp. Function Min Typ Max Unit Remarks Notes C1 AC coupling capacitor 42.3 47 51.7 nF 50 V, Ceramic 9 C2 Equalization capacitor 198 220 242 nF 50 V, Ceramic 9 C3 Capacitor to average bus DC voltage 80 100 120 nF 50 V, Ceramic 9 C4 Storage and filter capacitor VFILT 80 100 4000 mF 35 V 9, 16 C5 VDDA HF rejection capacitor 80 100 − nF 6.3 V, Ceramic C6 VDDD HF rejection capacitor 80 100 − nF 6.3 V, Ceramic C7 Load Capacitor V20V − 1 − mF 35 V, Ceramic, ESR < 2 W 14, 15, 16 Parallel capacitor X−tal 8 10 12 pF 6.3 V, Ceramic 10 C10 Load capacitor VDD1 8 10 mF 6.3 V, Ceramic, ESR < 0.1 W C11 Load capacitor VDD2 8 10 mF Ceramic, ESR < 0.1 W 11 R1 Shunt resistor for transmitting 24.3 27 29.7 W 1W 9 R2 DC1 sensing resistor 0.47 1 10 W 1/16 W R3 DC2 sensing resistor 0.47 1 10 W 1/16 W R4 Voltage divider to specify VDD2 0 − W 0 − 1 MW 1/16 W, see p19 for calculating the exact value − 220 − mH C8, C9 R5 L1, L2 DC1/DC2 inductor D1 Reverse polarity protection diode D2 Voltage suppressor X1 Crystal oscillator SS16 12 1SMA40CA FA-238 13 9. Component must be between minimum and maximum value to fulfill the KNX requirement. 10. Actual capacitor value depends on X1. If a crystal oscillator is chosen, the capacitors need to be chosen in such a way that the frequency equals 16 MHz. Capacitors are not required if external clock signal is supplied. 11. Voltage of capacitor depends on VDD2 value defined by R4 and R5. See p16 for more details on defining VDD2 voltage value. 12. Reverse polarity diode is mandatory to fulfill the KNX requirement. 13. A clock signal of 16 MHz (50 ppm or less) is mandatory to fulfill the KNX requirements. Or a crystal oscillator of 16 MHz, 50 ppm is used (C8 and C9 need to be of the correct value based on the crystal datasheet), or an external 16 MHz clock is used. 14. It’s allowed to short this pin to VFILT-pin 15. High capacitor value might affect the start up time 16. Total charge of C4 and C7 may not be higher than 121 mC to fulfill the KNX requirement. www.onsemi.com 17 NCN5121 ANALOG FUNCTIONAL DESCRIPTION The active pulse is produced by the transmitter and is ideally rectangular. It has a duration of 35 ms and a depth between 6 and 9 V (Vact). Each active pulse is followed by an equalization pulse with a duration of 69 ms. The latter is an abrupt jump of the bus voltage above the DC level followed by an exponential decay down to the DC level. The equalization pulse is characterized by its height Veq and the voltage Vend reached at the end of the equalization pulse. See the KNX Twisted Pair Standard (KNX TP1−256) for more detailed KNX information. Because NCN5121 follows the KNX standard only a brief description of the KNX related blocks is given in this datasheet. Detailed information on the KNX Bus can be found on the KNX website (www.knx.org) and in the KNX standards. KNX Bus Interfacing Each bit period is 104 ms. Logic 1 is simply the DC level of the bus voltage which is between 20 V and 33 V. Logic 0 is encoded as a drop in the bus voltage with respect to the DC level. Logic 0 is known as the active pulse. Veq V end VBUS Vact DC Level Active Pulse t Equalization Pulse 35 ms 69ms 104 ms 104 ms 1 0 Figure 15. KNX Bus Voltage versus Digital Value KNX Bus Transmitter this a large filter capacitor is used on the VFILT−pin. Abrupt load current steps are absorbed by the filter capacitor. Long−term stability requires that the average bus coupler input current is equal to the average (bus coupler) load current. This is shown by the parameter DIcoupler/Dt, which indicates the bus current slope limit. The bus coupler will also limit the current to a maximum of Icoupler_lim. At startup, this current limit is increased to Icoupler_lim,startup to allow for fast charging of the VFILT bulk capacitance. There are 4 conditions that determine the dimensioning of the VFILT capacitor. First, the capacitor value should be between 12.5 mF and 4000 mF to garantuee proper operation of the part. The next requirement on the VFILT capacitor is determined by the startup time of the system. According to the KNX specification, the total startup time must be below 10 s. This time is comprised of the time to charge the VFILT capacitor to 12 V (where the DCDC convertor becomes operatonal) and the startup time of the rest of the system tstartup,system. This gives the following formula: The purpose of the transmitter is to produce an active pulse (see Figure 15) between 6 V and 9 V regardless of the bus impedance (Note 1). In order to do this the transmitter will sink as much current as necessary until the bus voltage drops by the desired amount. KNX Bus Receiver The receiver detects the beginning and the end of the active pulse. The detection threshold for the start of the active pulse is −0.45 V (typ.) below the average bus voltage. The detection threshold for the end of the active pulse is −0.2 V (typ.) below the average bus voltage giving a hysteresis of 0.25 V (typ.). Bus Coupler The role of the bus coupler is to extract the DC voltage from the bus and provide a stable voltage supply for the purpose of powering the NCN5121. This stable voltage supplied by the bus coupler is called VFILT, and will follow the average bus voltage. The bus coupler also makes sure that the current drawn from the bus changes very slowly. For C t ǒ10 s * t startup,systemǓ 1. Maximum bus impedance is specified in the KNX Twisted Pair Standard www.onsemi.com 18 I coupler_Ilim,startup V FILTH NCN5121 and DC2 correctly, the voltage on the VIN−pin should be higher than the highest value of DC1 and DC2. Although both DC−DC converters are capable of delivering 100 mA, the maximum current capability will not always be usable. One always needs to make sure that the KNX bus power consumption stays within the KNX specification. The maximum allowed current for the DC−DC converters and V20V regulator can be estimated as next: The third limit on VFILT capacitor value is the required capacitor value to filter out current steps DIstep of the system without going into reset. Cu DI step 2 ǒ2 @ (VBUS1 * Vcoupler_drop * VFILTL) @ IslopeǓ The last condition on the size of VFILT is the desired warning time twarning between SAVEB and RESETB in case the bus voltage drops away. This is determined by the current consumption of the system Isystem. C u I system V BUS ǒtwarning ) tbusfilterǓ 2 The bus coupler is implemented as a linear voltage regulator. For efficiency purpose, the voltage drop over the bus coupler is kept minimal (see Table 4). KNX Impedance Control The impedance control circuit defines the impedance of the bus device during the active and equalization pulses. The impedance can be divided into a static and a dynamic component, the latter being a function of time. The static impedance defines the load for the active pulse current and the equalization pulse current. The dynamic impedance is produced by a block, called an equalization pulse generator, that reduces the device current consumption (i.e. increases the device impedance) as a function of time during the equalization phase so as to return energy to the bus. w1 (eq. 2) This is the 20 V low drop linear voltage regulator used to supply external devices. As it draws current from VFILT, this current is seen without any power conversion directly at the VBUS1 pin. The V20V regulator starts up by default but can be disabled by a command from the host controller (, see Analog Control Register 0, p54). When the V20V regulator is not used, no load capacitor needs to be connected (see C7 of Figures 12, 13 and 14). Connect V20V−pin with VFILT−pin in this case. V20V regulator will only be enabled when VFILT−bit is set (, see System Status Service, p37). The host controller can also monitor the status of the regulator (, see System Status Service, p37). The 20 V regulator has a current limit that depends on the FANIN resistor value, and the value of bits 0−3 (V20VCLIMIT[0:2]) of the analog control register. In Table 4, the typical value of the current limit at startup is given as I20V_lim (V20VCLIMIT[0:2] initializes at 100). For each bit difference, the current limit is adjusted up or down by DI20 V,STEP. The device contains two DC−DC buck converters, both supplied from VFILT. DC1 provides a fixed voltage of 3.3 V. This voltage is used as an internal low voltage supply (VDDA and VDDD) but can also be used to power external devices (VDD1−pin). DC1 is automatically enabled during the power−up procedure (see Analog State Diagram, p23). DC2 provides a programmable voltage by means of an external resistor divider. It is not used as an internal voltage supply making it not mandatory to use this DC−DC converter (if not needed, tie the VDD2MV pin to VDD1, see also Figure 12). DC2 can be monitored (, see System Status Service, p37), and/or disabled by a command from the host controller (, see Analog Control Register 0, p54). DC2 will only be enabled when VFILT−bit is set (, see System Status Service, p37). The status of DC2 can be monitored (, see System Status Service, p37). The voltage divider can be calculated as follows: 1.2 I DD2Ǔƫ V20V Regulator Fixed and Adjustable DC−DC Converter V VDD2 * 1.2 I DD1Ǔ ) ǒV DD2 IBUS will be limited by the KNX standard and should be lower or equal to Icoupler (see Table 4). Minimum VBUS is 20 V (see KNX standard). VDD1 and VDD2 can be found back in Table 4. IDD1, IDD2 and I20V must be chosen in a correct way to be in line with the KNX specification (Note 2). Although DC2 can operate up to 21 V, it will not be possible to generate this 21 V under all operating conditions. See application note AND9135 for defining the optimum inductor and capacitor of the DC−DC converters. When using low series resistance output capacitors on DC2, it is advised to split the current sense resistor as shown in Figure 18 to reduce ripple current for low load conditions. ǒVBUS1 * Vcoupler_drop * VFILTLǓ R4 + R5 ƪǒVDD1 ǒIBUS * I20VǓ Xtal Oscillator An analog oscillator cell generates the main clock of 16 MHz. This clock is directly provided to the digital block to generate all necessary clock domains. An input pin XSEL is foreseen to enable the use of a quartz crystal (see Figure 16) or an external clock generator (see Figure 17) to generate the main clock. (eq. 1) Both DC−DC converters make use of slope control to improve EMC performance (see Table 5). To operate DC1 2. The formula is for a typical KNX application. It‘s only given as guidance and does not guarantee compliance with the KNX standard. www.onsemi.com 19 NCN5121 XTAL2 34 XTAL1 35 OSC Microcontroller XTAL2 34 OSC XTAL1 35 32 XCLK 33 XSEL XCLKC 21 VDD 33 21 XSEL XCLKC 32 XCLK 8 MHz @ XCLC = VSS 16 MHz @ XCLC = VDD 8 MHz @ XCLC = VSS 16 MHz @ XCLC = VDD Figure 16. XTAL Oscillator VDD Figure 17. External Clock Generator when the transmission is complete or a collision is detected. This can be used during development as verification of transmission. Note that a scheduled transmission is a frame that is sent less than tBUS,IDLE (TODO s) after previous communication on the bus. When a frame is transmitted on a bus which has been idle for a longer time, or an ACK/NACK/BUSY response is sent, the transmission will start immediately after the trigger goes high, and the time between trigger high and frame transmission start will not be consistent. The XCLK−pin can be used to supply a clock signal to the host controller. This clock signal can be switched off by a command from the host controller (, see Analog Control Register 0, p54). After power−up, a 4 MHz (Note 3) clock signal will be present on the XCLK−pin during Stand−By. When Normal State is entered, a 8 or 16 MHz clock signal will be present on the XCLK−pin. See also Figure 20. To output an 8 MHz clock on the XCLK pin, the XCLKC pin must be pulled to ground. When the XCLKC pin is pulled up to VDDD, the XCLK pin will output a 16 MHz clock signal. When Normal State is left and Stand−By State is re−entered due to an issue different than an Xtal issue, the 8 or 16 MHz clock signal will still be present on the XCLK−pin during the Stand−By State. If however Stand−By is entered from Normal State due to an Xtal issue, the 4 MHz clock signal will be present on the XCLK−pin. See also Table 7. RESETB− and SAVEB−pin The RESETB signal can be used to keep the host controller in a reset state. When RESETB is low this indicates that the bus voltage is too low for normal operation and that the fixed DC−DC converter has not started up. It could also indicate a Thermal Shutdown (TSD). The RESETB signal also indicates if communication between host and NCN5121 is possible. The SAVEB signal indicates correct operation. When SAVEB goes low, this indicates a possible issue (loss of bus power or too high temperature) which could trigger the host controller to save critical data or go to a save state. SAVEB goes low immediately when VFILT goes below 14 V (due to sudden large current usage) or after 2 ms when VBUS goes below 20 V. RESETB goes low when VFILT goes below 12 V. RESETB− and SAVEB−pin are open−drain pins with an internal pull−up resistor to VDDD. FANIN−pin The FANIN−pin defines the maximum allowed bus current and bus current slopes. If the FANIN−pin is kept floating, pulled up to VDD, or pulled down with a resistance higher than 250 kW, NCN5121 will limit the KNX bus current slopes to 0.5 mA/ms at all times. NCN5121 will also limit the KNX bus current to 30 mA during start−up. During normal operation, NCN5121 is capable of taking 12 mA (= Icoupler) from the KNX bus for supplying external loads (DC1, DC2 and V20V). If the FANIN−pin is pulled to ground with a resistance smaller than 2 kW the operation is similar as above with the exception that the KNX bus current slopes will be limited to 1 mA/ms at all times, the KNX bus current will be limited to 60 mA during start−up and up to 24 mA (Icoupler) can be taken from the KNX bus during normal operation. Definitions for Start−Up and Normal Operation (as given above) can be found in the KNX Specification. Voltage Supervisors NCN5121 has different voltage supervisors monitoring VBUS, VFILT, VDD2 and V20V. The general function of a voltage supervisor is to detect when a voltage is above or below a certain level. The levels for the different voltages monitored can be found back in Table 4 (see also Figures 4, 5, 6 and 7). The status of the voltage supervisors can be monitored by the host controller (see System Status Service, p37). Depending on the voltage supervisor outputs, the device can enter different states (see Analog State Diagram, p23). Transmit Trigger When bit 3 of analog control register 0 is set, the TRIG−pin will output a signal that goes high 1 bit time before the start of a scheduled transmission, and goes low 3. The 4 MHz clock signal is internally generated and will be less accurate as the crystal generated clock signal of 8 or 16 MHz. www.onsemi.com 20 NCN5121 VIN P1 VSW1 Switch Controller From VFILT L1 1Ω VDD1 = 3.3V N1 10μ F VSS1 VDD1M COMP VDD1 P2 VSW2 Switch Controller L2 0.47Ω 0.47Ω N2 R4 VSS2 VDD2MV VDD2MC COMP VDD2 = 3.3V – 20V 10μF VDD2 R5 NCN5121 Figure 18. Fixed (VDD1) and Adjustable (VDD2) DC−DC Converter www.onsemi.com 21 NCN5121 Table 7. STATUS OF SEVERAL BLOCKS DURING THE DIFFERENT (ANALOG) STATES State Osc XCLK VDD1 VDD2/V20V SPI/UART KNX Reset Off Off Off Off Inactive Inactive Start−Up Off Off Start−up Off Inactive Inactive Stand−By (Note 17) Off 4 MHz On Start−Up Active Inactive (Note 22) Stand−By (Note 18) On (Note 20) On (Note 20) On On (Note 21) Active Inactive (Note 22) Normal On On (Note 19) On On Active Active 17. Only valid when entering Stand−By from Start−Up State. 18. Only valid when entering Stand−By from Normal State. 19. 8 MHz or 16 MHz depending on XCLKC. 20. 4 MHz signal if Stand−By state was entered due to oscillator issue. Otherwise 8 MHz or 16 MHz clock signal. 21. Only operational if Stand−By state was not entered due to VDD2 or V20V issue. 22. Under certain conditions KNX bus is (partly) active. See Digital State Diagram for more details. Temperature Monitor Once this bit is set to ‘1’, the host controller needs to re−write this bit to clear the internal timer before the Watchdog Timeout Interval expires (Watchdog Timeout Interval = , see Watchdog Register, p54). In case the Watchdog is acknowledged too early (before tWDPR) or not within the Watchdog Timeout Interval (tWDTO), the RESETB−pin will be made low (= reset host controller). Table 8 gives the Watchdog timings tWDTO and tWDPR. Details on can be found in the Watchdog Register, p54. The device produces an over−temperature warning (TW) and a thermal shutdown warning (TSD). Whenever the junction temperature rises above the Thermal Warning level (TTW), the SAVEB−pin will go low to signal the issue to the host controller. Because the SAVEB−pin will not only go low on a Thermal Warning (TW), the host controller needs to verify the issue by requesting the status (, see System Status Service, p37). When the junction temperature is above TW, the host controller should undertake actions to reduce the junction temperature and/or store critical data. When the junction temperature reaches Thermal Shutdown (TTSD), the device will go to the Reset State. The Thermal Shutdown will be stored (, see Analog Status Register, p56) and the analog and digital power supply will be stopped (to protect the device). The device will stay in the Reset State as long as the temperature stays above TTSD. If the temperature drops below TTSD, Start−Up State will be entered (see also Figure 19). At the moment VDD1 is back up and the OTP memory is read, Stand−By State will be entered and RESETB will go high. The Xtal oscillator will be started. Once the temperature has dropped below TTW and all voltages are high enough, Normal State will be entered. SAVEB will go high and KNX communication is again possible. The TW−bit will be reset at the moment the junction temperature drops below TTW. The TSD−bit will only be reset when the junction temperature is below TTSD and the bit is read (see Analog Status Register, p56). Figure 8 gives a better view on the temperature monitor. Table 8. WATCHDOG TIMINGS WDT[3:0] tWDTO [ms] tWDPR [ms] 0000 33 2 0001 66 4 0010 98 6 0011 131 8 0100 164 10 0101 197 12 0110 229 14 0111 262 16 1000 295 18 1001 328 20 1010 360 23 1011 393 25 1100 426 27 1101 459 29 1110 492 30 1111 524 31 Watchdog NCN5121 provides a Watchdog function to the host controller. The Watchdog function can be enabled by means of the WDEN−bit (, see Watchdog Register, p54). www.onsemi.com 22 NCN5121 Analog State Diagram oscillator has started, no Thermal Warning (TW) or Thermal Shutdown (TSD) was detected and the VBUS−, VFILT−, VDD2− and V20V−bits are set, the Normal State will be entered and SAVEB−pin will go high. Figure 21 gives a detailed view on the shut−down behavior. If the KNX bus voltage drops below VBUSL for more than tbus_filter, the VBUS−bit will be reset (, see System Status Service, p37) and the Standy−By State is entered. SAVEB will go low to signal this. When VFILT drops below VFILTL, DC2 and the V20V regulator will be switched off. When VFILT drops below 6.5 V (typ), DC1 will be switched off and VDD1 drops below 2.8 V (typ.) the device goes to Reset State (RESETB low). The analog state diagram of NCN5121 is given in Figure 19. The status of the oscillator, XCLK−pin, DC−DC converters, V20V regulator, serial and KNX communication during the different (analog) states is given in Table 7. Figure 20 gives a detailed view on the start−up behavior of NCN5121. After applying the bus voltage, the filter capacitor starts to charge. During this Reset State, the current drawn from the bus is limited to Icoupler (for details see the KNX Standards). Once the voltage on the filter capacitor reaches 10 V (typ.), the fixed DC−DC converter (powering VDDA) will be enabled and the device enters the Start−Up State. When VDD1 gets above 2.8 V (typ.), the OTP memory is read out to trim some analog parameters (OTP memory is not accessible by the user). When done, the Stand−By State is entered and the RESETB−pin is made high. If at this moment VBUS is above VBUSH, the VBUS−bit will be set (, see System Status Service, p37). After aprox. 2 ms the Xtal oscillator will start. When VFILT is above VFILTH DC2 and V20V will be started. When the Xtal Analog Output A multiplexed analog signal is available on the ANAOUT−pin for monitoring signal levels. The signal read out on this pin can be configured through the Analog Output Control bits (, see Analog Control Register 1, p 52). Reset RESETB = ‘0’ SAVEB = ‘0’ V FILT > 12V and Temp < TSD Enable DC1 Disable DC1 VFILT < 6.5V Start−Up RESETB = ‘0’ SAVEB = ‘0’ Disable DC1, DC2 and V20V V DDA OK and OTP read done and clock present Disable DC2 and V20V Enable DC2 and V20V VFILT < V FILTL VFILT > V FILTH Stand−By = ‘1’ or V DDA nOK RESETB = ‘1’ SAVEB = ‘0’ VFILT < 6.5V Disable DC1 = ‘1’ or = ‘0’ or = ‘0’ or = ‘0’ or = ‘0’ or = ‘0’ = ‘0’ and = ‘1’ and = ‘1’ and = ‘1’ and = ‘1’ and = ‘1’ = ‘1’ or VDDA nOK Normal RESETB = ‘1’ SAVEB = ‘1’ Remarks: * , , , , and are internal status bits which can be verified with the System State Service. * is an internal signal indicating a Thermal Shutdown. This internal signal cannot be read out. * Although Reset State could be entered from Normal State on a TSD, Stand*By State will be entered first due to a TW. Figure 19. Analog State Diagram www.onsemi.com 23 NCN5121 VBUS VFILT V BUSH V FILTH 12V IBUS Icoupler_lim,startup VDD1 2.8V VXTAL Xtal Oscillator ±2ms ±2ms VDD2 0.9 x V DD2 V20V V 20VH RESETB SAVEB XCLK Reset Start−Up Remarks: VDD1 directly connected to VDDA. Figure 20. Start−Up Behavior www.onsemi.com 24 Stand−By Normal t NCN5121 VBUS VFILT VBUSH VBUSL VFILTL 6.5V IBUS VDD1 2.8V VXTAL Xtal Oscillator tbus_filter tbus_filter VDD2 0.9 x VDD2 V20V RESETB SAVEB XCLK t Normal Stand-By Normal Remarks: VDD1 directly connected to VDDA. Figure 21. Shut−Down Behavior www.onsemi.com 25 Stand-By Reset NCN5121 Interface Mode The device can communicate with the host controller by means of a UART interface or an SPI interface. The selection of the interface is done by the pins MODE1, MODE2, TREQ, SCK/UC2 and CSB/UC1. Table 9. INTERFACE SELECTION TREQ MODE2 MODE1 SCK/UC2 CSB/UC1 SDI/RXD SDO/TXD 0 0 0 0 0 RXD TXD 0 0 0 0 1 9−bit UART−Mode, 38400 bps 0 0 0 1 0 8−bit UART−Mode, 19200 bps 0 0 0 1 1 8−bit UART−Mode, 38400 bps 1 0 0 DC2EN V20VEN Driver Receiver TREQ 0 1 SCK (out) CSB (out) SDI SDO TREQ 1 0 Description 9−bit UART−Mode, 19200 bps Analog Mode SPI Master, 125 kbps SPI Master, 500 kbps NOTE: X = Don‘t Care UART Interface NCN5121 detects an acceptance window error or pulse duration error on the KNX bus, the parity bit is also encoded to indicate an error in the byte. In 8−bit mode one extra service is available (U_FrameState.ind). The SDI/RXD−pin is the NCN5121 UART receive pin and is used to send data from the host controller to the device. Pin SDO/TXD is the NCN5121 UART transmit pin and is used to transmit data between the device and the host controller. Figure 12 gives an UART application example (9−bit, 19200 bps). Data is transmitted LSB first. The UART interface is selected by pulling pins TREQ, MODE1 and MODE2 to ground. Pin UC2 is used to select the UART Mode (‘0’ = 9−bit, ‘1’ = 8−bit) and pin UC1 is used to select the baudrate (‘0’ = 19200 bps, ‘1’ = 38400 bps). The UART interface allows full duplex, asynchronous communication. The difference between 8−bit mode and 9−bit mode is that in 9−bit an additional parity bit is transmitted. This parity bit is used as an even parity bit (with exception of the internal register read and write services where the parity bit is meaningless and should be ignored). However, when the Start (= 0) Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop (= 1) Figure 22. 8−bit UART Mode Start (= 0) Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Parity Stop (= 1) Figure 23. 9−bit UART Mode Mode, the UC1 and UC2 pins are used to enable or disable the 20 V regulator and DC2 controller. When pulled low, these blocks are enabled. When one of these pins is pulled to VDDD, the respective block is disabled. When using the device in Analog Mode, no clock needs to be provided to the device. One special UART Mode is foreseen called Analog Mode. When this mode is selected (TREQ = ‘1’, MODEx = ‘0’) an immediate connection is made with the KNX transmitter receiver (see Figure 24). Bit level coding/decoding has to be done by the host controller. Keep in mind that the signals on the SDI/RXD− and SDO/TXD−pin are inverted. Figure 14 gives an Analog Mode application example. In Analog www.onsemi.com 26 NCN5121 CEQ1 CAV VBUS1 CEQ2 VFILT VDDA VSSA VDDD VSSD Bus Coupler SCK/UC2 Impedance Control SDI/RXD Receiver CSB/UC1 SDO/TXD CCP TREQ (TREQ = 1) NCN5121 MODE1 TXO VBUS2 FANIN V20V MODE2 Transmitter VIN Fan−In Control DC/DC Converter 1 OSC VDD1M VDD1 VSS1 20V LDO RC Osc POR XTAL1 VSW1 OSC XTAL2 VSW2 TW/ TSD XSEL UVD DC/DC Converter 2 VDD2MC VDD2MV VDD2 Diagnostics XCLKC XCLK ANAOUT SAVEB RESETB Figure 24. Analog UART Mode www.onsemi.com 27 VSS2 NCN5121 SPI Interface The SPI interface allows full duplex synchronous communication between the device and the host controller. The interface operates in Mode 0 (CPOL and CPHA = ‘0’) meaning that the data is clocked out on the falling edge and sampled on the rising edge. The LSB is transmitted first. The SPI interface is selected by MODE1− and MODE2−pin. The baudrate is determined by which MODE−pin is pulled high (MODE1 pulled high = 125 kbps, MODE2 pulled high = 500 kbps). 0 1 2 3 4 5 6 7 SDI LSB 1 2 3 4 5 6 MSB SDO LSB 1 2 3 4 5 6 MSB CSB SCK ÉÉ ÉÉ ÉÉ ÉÉ Figure 25. SPI Transfer During SPI transmission, data is transmitted (shifted out serially) on the SDO/TXD−pin and received (shifted in serially) on the SDI/RXD−pin simultaneously. SCK/UC2 is set as output and is used as the serial clock (SCK) to synchronize shifting and sampling of the data on the SDI− and SDO−pin. The speed of this clock signal is selectable (see Table 9). The slave select line (CSB/UC1−pin) will go low during each transmission allowing to selection the host controller (CSB−pin is high when SPI is in idle state). MOSI SDO/TXD Shift Register Control SDI/RXD MISO SCK/UC2 SCLK CSB/UC1 SS NCN5121 Shift Register Control Host Controller Figure 26. SPI Master In an SPI network only one SPI Master is allowed (in this case NCN5121). To allow the host controller to communicate with the device the TREQ−pin can be used (Transmit Request). When NCN5121 detects a negative edge on TREQ, the device will issue dummy transmission of 8 bits which will result in a transmission of data byte from the host controller to the device. See Figure 11 for details on the timings. See Figure 13 for an SPI application example. CSB SCK SDI 0 1 2 3 4 5 6 7 0 1 2 3 4 D D D D D D D D D D D D D Dummy SDO TREQ Start dummy transmission Figure 27. Transmission Request www.onsemi.com 28 NCN5121 DIGITAL FUNCTIONAL DESCRIPTION The implementation of the Data Link Layer as specified in the KNX standard is divided in two parts. All functions related to communication with the Physical Layer and most of the Data Link Layer services are inside NCN5121, the rest of the functions and the upper communication layers are implemented into the host controller (see Figure 28). The host controller is responsible for handling: • Checksum • Parity • Addressing • Length The NCN5121 is responsible for handling: • Checksum • • • • Parity Acknowledge Repetition Timing Digital State Diagram The digital state diagram is given in Figure 29. The current mode of operation can be retrieved by the host controller at any time (when RESETB−pin is high) by issuing the U_SystemStat.req service and parsing back U_SystemStat.ind service (see System Status Service, p37). Table 10. NCN5121 DIGITAL STATES State Explanation RESET Entered after Power On Reset (POR) or in response to a U_Reset.req service issued by the host controller. In this state NCN5121 gets initialized, all features disabled and services are ignored and not executed. POWER−UP / POWER−UP STOP Entered after Reset State or when VBUS, VFILT or Xtal are not operating correctly (operation of VBUS, VFILT and XTAL can be verified by means of the System Status Service, p37). Communication with KNX bus is not allowed. U_SystemStat.ind can be used to verify this state (code 00). SYNC NCN5121 remains in this state until it detects silence on the KNX bus for at least 40 Tbits. Although the receiver of NCN5121 is on, no frames are transmitted to the host controller. U_SystemStat.ind can be used to verify this state (code 01). STOP This state is useful for setting−up NCN5121 safely or temporarily interrupting reception from the KNX bus. U_SystemStat.ind can be used to verify this state (code 10). NORMAL In this state the device is fully functional. Communication with the KNX bus is allowed. U_SystemStat.ind can be used to verify this state (code 11). www.onsemi.com 29 7 Application Layer 6 Presentation Layer 5 Session Layer 4 Transport Layer 3 Network Layer Host Controller NCN5121 Logic Link Control Data Link Layer NCN5121 2 Media Access Control 1 Physical Layer Figure 28. OSI Model Reference Reset POR or U_Reset.req Initialize device Deactivate all features Send U_StopMode.ind to host U_StopMode .req Power−Up U_ExitStopMode .req Code: 00 KNX Rx = off KNX Tx = off < XTAL > = ‘1’ and = ‘1’ and = ‘1’ = ‘0’ or = ‘0’ or = ‘0’ U_ExitStopMode.req Code: 01 KNX Rx = on KNX Tx = off Code: 00 KNX Rx = off KNX Tx = off = ‘1’ and = ‘1’ and = ‘1’ = ‘0’ or = ‘0’ or = ‘0’ Sync Power−Up Stop = ‘0’ or = ‘0’ or = ‘0’ Stop Code: 10 KNX Rx = off KNX Tx = off U_StopMode.req KNX bus idle for w40 Tbits Send U _Reset .ind to host Send U_StopMode.ind to host U_StopMode.req and no activity for w30 Tbits Normal Code: 11 KNX Rx = on KNX Tx = on Figure 29. Digital State Diagram www.onsemi.com 30 NCN5121 Services Execution of services depends on the digital state (Figure 29). Certain services are rejected if received outside the Normal State. The following table gives a view of all services and there acceptance during the different digital states. Table 11. ACCEPTANCE OF SERVICES State Normal Stop Sync Power−Up Bus Monitor U_Reset.req E E E E E U_State.req E E E E I U_SetBusy.req E E E E I U_QuitBusy.req E E E E I U_Busmon.req E E E E I U_SetAddress.req E E E E I U_SetRepetition.req E E E E I U_L_DataOffset.req E E E E I U_SystemStat.req E E E E I U_StopMode.req E I E E E U_ExitStopMode.req I E I I E U_Ackn.req E R R R I U_Configure.req E E E E I U_IntRegWr.req E E E E E U_IntRegRd.req E E E E E U_L_DataStart.req E R R R I U_L_DataCont.req E R R R I U_L_DataEnd.req E R R R I U_PollingState.req E E E E I Service NOTE: Bus Monitor state is not a separate state. It is applied on top of Normal, Stop, Sync or Power−Up State. Legend: E = service is executed I = service is ignored (not executed and no feedback sent to the host controller) R = service is rejected (not executed, protocol error is sent back to the host controller through U_State.ind) See Internal Register Read Service (p39) for limitations of U_IntRegRd.req www.onsemi.com 31 NCN5121 Table 12. SERVICES FROM HOST CONTROLLER Control Field 7 6 5 4 3 2 1 0 Service Name Hex Remark Extra Following Bytes Total Bytes INTERNAL COMMANDS – DEVICE SPECIFIC 0 0 0 0 0 0 0 1 U_Reset.req 01 1 0 0 0 0 0 0 1 0 U_State.req 02 1 0 0 0 0 0 0 1 1 U_SetBusy.req 03 1 0 0 0 0 0 1 0 0 U_QuitBusy.req 04 1 0 0 0 0 0 1 0 1 U_Busmon.req 05 1 1 1 1 1 0 0 0 1 U_SetAddress.req F1 AddrHigh AddrLow X (don’t care) 4 1 1 1 1 0 0 1 0 U_SetRepetition.req F2 RepCntrs X (don’t care) X (don’t care) 4 0 0 0 0 1 i i i U_L_DataOffset.req 08−0C 0 0 0 0 1 1 0 1 U_SystemState.req 0D 1 0 0 0 0 1 1 1 0 U_StopMode.req 0E 1 0 0 0 0 1 1 1 1 U_ExitStopMode.req 0F 1 0 0 0 1 0 n b a U_Ackn.req 10−17 n = nack b = busy a = addressed 1 0 0 0 1 1 p c m U_Configure.req 18−1F p = auto−polling c = CRC−CCITT m = frame end with MARKER 1 0 0 1 0 1 0 a a U_IntRegWr.req 28−2B Data to be written 0 0 1 1 1 0 a a U_IntRegRd.req 38−3B aa = address of internal register 1 1 1 0 s s s s U_PollingState.req E0−EE s = slot number (0 … 14) PollAddrHigh PollAddrLow PollState 4 iii = MSB byte index (0…4) 1 2 1 KNX TRANSMIT DATA COMMANDS 1 0 0 0 0 0 0 0 U_L_DataStart.req 80 Control Octet (CTRL) 2 1 0 i i i i i i U_L_DataCont.req 81−BF i = index (1…63) Data octet (CTRLE, SA, DA, AT, NPCI, LG, TPDU) 2 0 1 l l l l l l U_L_DataEnd.req 47−7F l = last index + 1 (7 … 63) Check Octet (FCS) 2 With respect to command length, there are two types of services from the host controller: • Single−byte commands: the control byte is the only data sent from the host controller to NCN5121. • Multiple−byte commands: the following data byte(s) need to be handled according to the already received control byte. With respect to command purpose there are two types of services from the host controller: • Internal command: does not initiate any communication on the KNX bus. • KNX transmit data command: initiates KNX communication www.onsemi.com 32 NCN5121 Table 13. SERVICES TO HOST CONTROLLER Extra Following Bytes Control Field 7 6 5 4 3 2 1 0 Service Name Remark Total Bytes DLL (LAYER 2) SERVICES (DEVICE IS TRANSPARENT) 1 0 r 1 p1 p0 0 0 L_Data_Standard.ind 0 0 r 1 p1 p0 0 0 L_Data_Extended.ind 1 1 1 1 0 0 0 0 L_Poll_Data.ind r = not repeated (‘1’) or repeated L_Data frame (‘0’) p1, p0 = priority n n n ACKNOWLEDGE SERVICES (DEVICE IS TRANSPARENT IN BUS MONITOR MODE) x x 0 0 x x 0 0 L_Ackn.ind x = acknowledge frame 1 z 0 0 0 1 0 1 1 L_Data.con z = positive (‘1’) or negative (‘0’) confirmation 1 CONTROL SERVICES – DEVICE SPECIFIC 0 0 0 0 0 0 1 1 U_Reset..ind 1 sc re te pe tw 1 1 1 U_State.ind sc = slave collision re = receive error te = transmit error pe = protocol error tw = temperature warning 1 re ce te 1 res 0 1 1 U_FrameState.ind re = parity or bit error ce = checksum or length error te = timing error res = reserved 1 0 b aa ap c m 0 1 U_Configure.ind b = reserved aa = auto−acknowledge ap = auto−polling c = CRC−CCITT m = frame end with MARKER 1 1 1 0 0 1 0 1 1 U_FrameEnd.ind 1 0 0 1 0 1 0 1 1 U_StopMode.ind 1 0 1 0 0 1 0 1 1 U_SystemStat.ind V20V, VDD2, VBUS, VFILT, XTAL, TW, Mode 2 Each data byte received from the KNX bus is transparently transmitted to the host controller. An exception is the Acknowledge byte which is transmitted to the host controller only in bus monitoring mode. Other useful information can be transmitted to the host controller by request using internal control services. A detailed description of the services is given on the next pages. For all figures, the MSB bit is always given on the left side no matter how the arrow is drawn. MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB KNX Bus MSB 1 LSB 2 LSB 3 2 1 4 5 3 6 5 4 MSB 6 NCN5121 MSB Host Ctrl Figure 30. Bit Order of Services www.onsemi.com 33 NCN5121 Reset Service Reset the device to the initial state. Host Ctrl NCN5121 KNX Bus U_Reset.req 0 0 0 0 0 0 0 0 0 1 1 1 U_Reset.ind 0 0 0 0 Figure 31. Reset Service Remark: U_Reset.Ind will be send when entering Normal State (see Digital State Diagram, p29). State Service Get internal communication state of the device. Host Ctrl NCN5121 KNX Bus U_State.req 0 0 sc re 0 0 0 0 1 0 1 1 U_State.ind te pe tw 1 Figure 32. State Service sc (slave collision): re (receive error): ‘1’ if collision is detected during transmission of polling state ‘1’ if corrupted bytes were sent by the host controller. Corruption involves incorrect parity (9−bit UART only) and stop bit of every byte as well as incorrect control octet, length or checksum of frame for transmission. te (transceiver error): ‘1’ if error detected during frame transmission (sending ‘0’ but receiving ‘1’). pe (protocol error): ‘1’ if an incorrect sequence of commands sent by the host controller is detected. tw (thermal warning): ‘1’ if thermal warning condition is detected. Set Busy Service Activate BUSY mode. During this time and when autoacknowledge is active (see Set Address Service p35), NCN5121 rejects the frames whose destination address corresponds to the stored physical address by sending the BUSY acknowledge. This service has no effect if autoacknowledge is not active. Host Ctrl NCN5121 KNX Bus U_SetBusy.req 0 0 0 0 0 0 1 1 Figure 33. Set Busy Service Remark: BUSY mode is deactivated immediately if the host controller confirms a frame by sending U_Ackn.req service. Quit Busy Service Deactivate the BUSY mode. Restores back to the normal autoacknowledge behavior with ACK sent on the bus in response to addressing frame (only if autoacknowledge is active). This service has no effect if autoacknowledge is not active or BUSY mode was not set. Host Ctrl NCN5121 U_QuitBusy.req 0 0 0 0 0 1 0 0 Figure 34. Quit Busy Service www.onsemi.com 34 KNX Bus NCN5121 Bus Monitor Service Activate bus monitoring state. In this mode all data received from the KNX bus is sent to the host controller without performing any filtering on Data Link Layer. Acknowledge Frames are also transmitted transparently. This state can only be exited by the Reset Service (see p34). Host Ctrl NCN5121 KNX Bus U_Busmon.req 0 0 0 0 0 1 0 1 KNX Message KNX Message x x x x x x x x x x x x x x x x x x x x x 0 0 x KNX Message KNX Message x x x x x x x x x 0 0 0 0 0 0 x x 0 0 0 1 1 1 x x x Acknowledge Acknowledge x x 0 0 x x U_Reset.req 0 0 0 0 U_Reset.ind 0 0 0 0 Figure 35. Bus Monitor Service Remark: x = don‘t care Set Address Service Sets the physical address of the device and activates the auto−acknowledge function. NCN5121 starts accepting all frames whose destination address corresponds to the stored physical address or whose destination address is the group address by sending IACK on the bus. In case of an error detected during such frame reception, NCN5121 sends NACK instead of IACK. When issued several times after each other, the first call will set the physical address and activate the auto−acknowledge. Following calls will only set the physical address because auto−acknowledge is already activated. NCN5121 confirms activation of auto−acknowledge function by sending the U_Configure.ind service to the host controller. Host Ctrl NCN5121 U_SetAddress.req 1 1 1 1 0 0 0 1 Address High Byte x x x x x x x x Address Low Byte x x x x x x 0 b x x x x x x x x Dummy x x U_Configure.ind aa ap c m 0 1 Figure 36. Set Address Service www.onsemi.com 35 KNX Bus NCN5121 b (busy mode): ‘1’ if busy mode is active. Can be enabled with U_SetBusy.req (see Set Busy Service, p34) and disabled with U_QuitBusy.req service (see Quit Busy Service, p34) or U_Ackn.req service (see Receive Frame Service, p47). aa (auto−acknowledge):‘1’ if auto−acknowledge feature is active. Can be enabled with U_SetAddress.req service (see Set Address Service, p35). ap (auto−polling): ‘1’ if auto−polling feature is active. This feature can be enabled with U_Configure.req service (see Configure Service, p38). c (CRC−CCITT): ‘1’ if CRC−CCITT feature is active. This feature can be enabled with U_Configure.req service (see Configure Service, p38). m (frame end with MARKER): ‘1’ when feature is active. This feature can be enabled with U_Configure.req service (see Configure Service, p38). Remarks: • Set Address Service can be issued any time but the new physical address and the autoacknowledge function will only get active after the KNX bus becomes idle. Autoacknowledge can only be deactivated by a Reset Service (p34) • • x = don’t care • Dummy byte can be anything. NCN5121 completely disregards this information. Set Repetition Service Specifies the maximum repetition count for transmitted frames when not acknowledged with IACK. Separate counters can be set for NACK and BUSY frames. Initial value of both counters is 3. If the acknowledge from remote Data Link Layer is BUSY during frame transmission, NCN5121 tries to repeat after at least 150 bit times KNX bus idle. The BUSY counter determines the maximum amount of times the frame is repeated. If the BUSY acknowledge is still received after the last try, an L_Data.con with a negative conformation is sent back to the host controller. For all other cases (NACK acknowledgment received, invalid/corrupted acknowledge received or time−out after 30 bit times) NCN5121 will repeat after 50 bit times of KNX bus idle. The NACK counter determines the maximum retries. L_Data.con with a negative confirmation is send back to the host controller when the maximum retries were reached. In worst case, the same request is transmitted (NACK + BUSY + 1) times before NCN5121 stops retransmission. Host Ctrl NCN5121 KNX Bus U_SetRepetition.req 1 1 1 1 0 0 1 0 Maximum Repetitions 0 b b x x x x x x b 0 n n n x x x x x x Dummy x x Dummy x x Figure 37. Set Repetition Service bbb: BUSY counter (a frame will be retransmitted bbb−times if acknowledge with BUSY). nnn: NACK counter (a frame will be retransmitted nnn−times if acknowledge with NACK). Remark: Bit 3 and 7 of the second byte need to be zero (‘0’)! www.onsemi.com 36 NCN5121 System Status Service Request the internal system state of the device. Host Ctrl NCN5121 KNX Bus U_SystemStat .req 0 0 0 0 1 1 0 1 U_SystemStat .ind 0 1 0 0 1 0 1 1 TW Mode XTAL VFILT VBUS V20V VDD2 2nd byte Figure 38. System State Service V20V: VDD2: VBUS: VFILT: XTAL: TW: Mode: ‘1’ if V20V linear voltage regulator is within normal operating range ‘1’ if DC2 regulator is within normal operating range ‘1’ if KNX bus voltage is within normal operating range ‘1’ if voltage on tank capacitor is within normal operating range State Service ‘1’ if crystal oscillator frequency is within normal operating range ‘1’ if thermal warning condition is present (can also be verified with U_State.ind service (see State Service, p34) Operation mode (see also Digital State Diagram, p29). Bit 1 0 Mode 0 0 Power−Up 0 1 Sync 1 0 Stop 1 1 Normal Note: SAVEB−pin is low if any of bits 3 to 7 is ‘0’ (zero) or bit 2 is ‘1’. Stop Mode Service Go to Stop State. A confirmation is sent to indicate that device has switched to the Stop State. See also Digital State Diagram, p29 Host Ctrl NCN5121 U_StopMode.req 0 0 0 0 1 1 1 0 U_StopMode.ind 0 0 1 0 1 0 1 1 Figure 39. Stop Mode Service www.onsemi.com 37 KNX Bus NCN5121 Exit Stop Mode Service Request transition from Stop to Sync State. An acknowledge service is send later to confirm that device has switched from Sync to Normal State. See also Digital State Diagram, p29. Host Ctrl NCN5121 KNX Bus U_ExitStopMode .req 0 0 0 0 0 0 1 1 1 1 1 1 U_Reset.ind 0 0 0 0 Figure 40. Exit Stop Mode Service Configure Service Activate additional features (which are disabled after reset). U_Configure.ind service is send back to the host controller at the exact moment when the new features get activated. This is done during bus idle or outside the Normal State. It confirms the execution of the request service. Host Ctrl NCN5121 KNX Bus U_Configure.req 0 0 0 b 0 1 1 p c m U_Configure.ind aa ap c m 0 1 Figure 41. Configure Service p (auto polling): when active, NCN5121 automatically fills in corresponding poll slot of polling telegrams. Host controller is responsible to provide appropriate polling information with the U_PollingState.req service (See Slave Polling Frame Service and Master Polling Frame Service, p50 and 51). c (CRC−CCITT): when active, NCN5121 accompanies every received frame with a 2−byte CRC−CCITT value. CRC−CCITT is also known as CRC−16−CCITT. m (frame end with MARKER): End of received frames is normally reported with a silence of 2.6 ms on the Tx line to the host controller. With this feature active, NCN5121 marks end of frame with U_FrameEnd.ind + U_FrameState.ind services (See Send Frame Service and Receive Frame Service, p39 and 47). b: ‘1’ if busy mode is active. Can be enabled with U_SetBusy.req (see Set Busy Service, p34) and disabled with U_QuitBusy.req service (see Quit Busy Service, p34) or U_Ackn.req service (see Receive Frame Service, p47). aa: ‘1’ if auto−acknowledge feature is active. Can be enabled with U_SetAddress.req service (see Set Address Service, p35). ap (auto−polling): ‘1’ if auto−polling feature is active. This feature can be enabled with U_Configure.req service. c (CRC−CCITT): ‘1’ if CRC−CCITT feature is active. See p53 for info on CRC−CCITT. This feature can be enabled with U_Configure.req service. m (frame end with MARKER): ‘1’ when feature is active. This feature can be enabled with U_Configure.req service. Remark: Activation of the additional features is done by setting the corresponding bit to ‘1’. Setting the bit to ‘0’ (zero) has no effect (will not deactivate feature). Features can only be deactivated by a reset. Set all bits (m, c and p) to ‘0‘ (zero) to poll the current configuration status. www.onsemi.com 38 NCN5121 Internal Register Write Service Write a byte to an internal device−specific register (see Internal Device−Specific Registers, p54). The address of the register is specified in the request. The data to be written is transmitted after the request. Host Ctrl NCN5121 KNX Bus U_IntRegWr .req 0 0 1 x x x 0 1 0 a a x x Data Byte x x x Figure 42. Internal Register Write Service aa: address of the internal register Remarks: • x = don’t care (in line with Internal Device−Specific Registers, p54). • Internal Register Write is not synchronized with other services. One should only use this service when all previous services are ended. When using communication over SPI, it is recommended to go to stop mode when performing a register write. When communicating over UART, this is not required. Internal Register Read Service Read a byte from an internal device−specific register (see Internal Device−Specific Registers, p54). The address of the register is specified in the request. The next byte returns the data of the addressed register. Host Ctrl NCN5121 KNX Bus U_IntRegRd.req 0 0 1 x x x 1 1 0 a a x x Data Byte x x x Figure 43. Internal Register Read Service aa: address of the internal register Remarks: • x = don’t care (in line with Internal Device−Specific Registers, p54). • It’s advised to only use this service in Stop, Power−Up Stop or Power−Up State. In the other state erroneous behavior • could occur. Internal Register Read is not synchronized with other services. One should only use this service when all previous services are ended. When using communication over SPI or UART, it is recommended to go to stop mode when performing a register write. Send Frame Service Send data over the KNX bus. The U_L_DataStart.req is used to start transmission of a new frame. The byte following this request is the control byte of the KNX telegram. The different bytes following the control byte are assembled by using U_L_DataCont.req. The byte following U_L_DataCont.req is the data byte of the KNX telegram. U_L_DataCont.req contains the index which specifies the position of the data byte inside the KNX telegram. It‘s allowed to transmit bytes in random order and even overwrite bytes (= write several times into the same index). It‘s up to the host controller to correctly populate all data bytes of the KNX telegram. U_L_DataEnd.req is used to finalize the frame and start the KNX transfer. The byte following U_L_DataEnd.req is the checksum of the KNX telegram. If the checksum received by the device corresponds to the calculated checksum, the device starts the transmission on the KNX bus. If not, the device returns U_State.ind message to the host controller with Receive Error flag set (see State Service p34 for U_State.ind). www.onsemi.com 39 NCN5121 U_L_DataStart/DataCont/DataEnd only provides space for 6 index bits. Because an extended frame can consist out of 263 bytes, an index of 9 bits long is needed. U_DataOffset.req provides the 3 most significant bits of the data byte index. The value is stored internally until a new offset is provided with another call. Each transmitted data octet on the KNX bus will also be transmitted back to the host controller. Each transmission is ended with a L_Data.con service where the MSB indicates if an acknowledgment was received or not. When operating in SPI or UART 8−bit Mode, L_Data.con is preceded with U_FrameState.ind. Depending on the activated features, a CRC−CCITT service and/or a MARKER could be included. Next figures give different examples of send frames. Host Ctrl NCN5121 KNX Bus U_L_DataStart.req 1 0 x x 0 0 0 0 0 0 x x Control Byte x x x x U_L_DataCont.req 1 0 x x i i i i i i x x Data Octet 1 x x x x U_L_DataOffSet .req 0 0 0 0 1 i i i U_L_DataCont.req 1 0 x x i i i i i i x x Data Octet N x x x x U_L_DataEnd .req 0 1 x x l l l l l l x x Checksum x x x x Control Byte L_Data.ind x 0 r 1 p1 p0 0 x x x x x x x x x x x x x x x 0 x x x x x x x x x x x x x x Data Octet 1 Data Octet 1 x x x x x x x Data Octet N Data Octet N x x x x x x x x x x x x Checksum Checksum x x x x x x x x x x x x Immediate Ackn x x x x w2.6ms silence U_FrameState .ind re ce x 0 te 1 res 0 1 1 1 1 L_Data.con 0 0 1 0 Figure 44. Send Frame, SPI or 8−bit UART Mode, Frame End with Silence, No CRC−CCITT www.onsemi.com 40 NCN5121 Host Ctrl NCN5121 KNX Bus U_L_DataStart.req 1 0 x x 0 0 0 0 0 0 x x Control Byte x x x x U_L_DataCont.req 1 0 x x i i i i i i x x Data Octet 1 x x x x U_L_DataOffSet .req 0 0 0 0 1 i i i U_L_DataCont.req 1 0 x x i i i i i i x x Data Octet N x x x x U_L_DataEnd .req 0 1 x x l l l l l l x x Checksum x x x x Control Byte L_Data.ind x 0 r 1 p1 p0 0 x x x x x x x x x x x x x x x 0 x x x x x x x x x x x x x x Data Octet 1 Data Octet 1 x x x x x x x Data Octet N Data Octet N x x x x x x x x x x x x Checksum Checksum x x x x x x x x x x x x Immediate Ackn x x x x w2.6ms silence L_Data.con x 0 0 0 1 0 1 1 Figure 45. Send Frame, 9−bit UART Mode, Frame End with Silence, No CRC−CCITT www.onsemi.com 41 NCN5121 Host Ctrl NCN5121 KNX Bus U_L_DataStart.req 1 0 x x 0 0 0 0 0 0 x x Control Byte x x x x U_L_DataCont.req 1 0 x x i i i i i i x x Data Octet 1 x x x x U_L_DataOffSet .req 0 0 0 0 1 i i i U_L_DataCont.req 1 0 x x i i i i i i x x Data Octet N x x x x U_L_DataEnd.req 0 1 x x l l l l l l x x Checksum x x x x L_Data.ind x 0 r 1 p1 p0 0 x x x x x x x x x x x x x x x 0 Data Octet 1 x Control Byte x x x x x x x x x x x x x x x Data Octet 1 x x x x x Data Octet N Data Octet N x x x x x x x x x x x x Checksum Checksum x x x x x x x x x x x x CRC−CCITT High Byte x x x x x x x x CRC−CCITT Low Byte x x x x x x x x w2.6 ms silence Immediate Ackn x x x x L_Data.con x 0 0 0 1 0 1 1 Figure 46. Send Frame, 9−bit UART Mode, Frame End with Silence, with CRC−CCITT www.onsemi.com 42 NCN5121 Host Ctrl NCN5121 KNX Bus U_L_DataStart.req 1 0 x x 0 0 0 0 0 0 x x Control Byte x x x x U_L_DataCont.req 1 0 x x i i i i i i x x Data Octet 1 x x x x U_L_DataOffSet .req 0 0 0 0 1 i i i U_L_DataCont.req 1 0 x x i i i i i i x x Data Octet N x x x x U_L_DataEnd .req 0 1 x x l l l l l l x x Checksum x x x x Control Byte L_Data.ind x 0 r 1 p1 p0 0 x x x x x x x x x x x x x x x 0 x x x x x x x x x x x x x x Data Octet 1 Data Octet 1 x x x x x x x Data Octet N Data Octet N x x x x x x x x x x x x Checksum Checksum x x x x x x x x x x x x CRC−CCITT High Byte x x x x x x x x CRC−CCITT Low Byte x x x x x x x x Immediate Ackn w 2.6ms silence x x x x U_FrameState .ind re ce x 0 te 1 res 0 1 1 1 1 L_Data.con 0 0 1 0 Figure 47. Send Frame, SPI or 8−bit UART Mode, Frame End with Silence, with CRC−CCITT www.onsemi.com 43 NCN5121 Host Ctrl NCN5121 KNX Bus U_L_DataStart .req 1 0 x x 0 0 0 0 0 0 x x Control Byte x x x x U_L_DataCont .req 1 0 x x i i i i i i x x Data Octet 1 x x x x U_L_DataOffSet .req 0 0 0 0 1 i i i U_L_DataCont .req 1 0 x x i i i i i i x x Data Octet N x x x x U_L_DataEnd.req 0 1 x x l l l l l l x x Checksum x x x x Control Byte L_Data.ind x 0 r 1 p1 p0 0 x x x x x x x x x x x x x x x 0 x x x x x x x x x x x x x x Data Octet 1 Data Octet 1 x x x x x x x Data Octet N Data Octet N x x x x x x x x x x x x Checksum Checksum x x x x x x x x x x x x U_FrameEnd.ind 1 1 0 0 1 0 1 1 Immediate Ackn U_FrameState .ind re ce x 0 te 1 res 0 1 1 1 1 x x x x L_Data.con 0 0 1 0 Figure 48. Send Frame, All Modes, Frame End with MARKER, No CRC−CCITT www.onsemi.com 44 NCN5121 Host Ctrl NCN5121 KNX Bus U_L_DataStart .req 1 0 x x 0 0 0 0 0 0 x x Control Byte x x x x U_L_DataCont .req 1 0 x x i i i i i i x x Data Octet 1 x x x x U_L_DataOffSet .req 0 0 0 0 1 i i i U_L_DataCont .req 1 0 x x i i i i i i x x Data Octet N x x x x U_L_DataEnd.req 0 1 x x l l l l l l x x Checksum x x x x Control Byte L_Data.ind x 0 r 1 p1 p0 0 x x x x x x x x x x x x x x x 0 x x x x x x x x x x x x x x Data Octet 1 Data Octet 1 x x x x x x x Data Octet N Data Octet N x x x x x x x x x x x x Checksum Checksum x x x x x x x x x x x x U_FrameEnd.ind 1 1 0 0 1 0 1 1 Immediate Ackn U_FrameState .ind re ce te 1 res 0 1 x x x x 1 CRC−CCITT High Byte x x x x x x x x CRC−CCITT Low Byte x x x 0 x x x x x x 1 1 L_Data.con 0 0 1 0 Figure 49. Send Frame, All Modes, Frame End with MARKER and with CRC−CCITT www.onsemi.com 45 NCN5121 re (receive error): ce (checksum or length error): te (timing error): res (reserved): ‘1’ if newly received frame contained corrupted bytes (wrong parity, wrong stop bit or incorrect bit timings) ‘1’ if newly received frame contained wrong checksum or length which does not correspond to the number of received bytes ‘1’ if newly received frame contained bytes whose timings do not comply with the KNX standard Reserved for future use (will be ‘0’). Remarks: − If the repeat flag is not set (see Set Repetition Service p36), the device will only perform one attempt to send the KNX telegram. − Sending of the KNX telegram over the KNX bus is only started after all data bytes are received and the telegram is assembled. − When starting transmission of a new frame with U_L_DataStart.req, the device automatically resets the internal offset of the data index to zero. − Data offsets of 5, 6 and 7 are forbidden (U_L_DataOffset.req)! Remarks on Figures 44 to 49: − x = don‘t care (in respect with KNX standard) − See Tables 12 and 13 for more details on all the bits − Code of U_FrameEnd.ind (0xCB) can also be part of the KNX frame content (Data Octet). When NCN5121 transmits the data octet (0xCB) on the KNX bus, 2 bytes (2 times 0xCB) will be transmitted back to the host controller to make it possible for the host controller to distinguish between a data octet (0xCB) and U_FrameEnd.ind. This remark is only valid if frame end with MARKER is enabled. − See p53 for info on CRC−CCITT. www.onsemi.com 46 NCN5121 Receive Frame Service Receive data over the KNX bus. Upon reception from the control byte, the control byte is checked by the device. If correct, the control byte is transmitted back to the host (L_Data_Standard.ind or L_Data_Extended.ind depending if standard or extended frame type is received). After the control byte, all data bytes are transparently transmitted back to the host controller. Handling of this data is a task for the Data Link Layer which should be implemented in the host controller. The host controller can indicate if the device is addressed by setting the NACK, BUSY or ACK flag (U_Ackn.req). When working in SPI or 8−bit UART Mode, each frame is ended with an U_FrameState.ind. Depending on the activated features, a CRC−CCITT or MARKER could be added to the complete frame. Below figures give different examples of receive frames. Host Ctrl NCN5121 KNX Bus Control Byte L_Data .ind x 0 r 1 p1 p0 0 x 0 0 x x x x x x x x x x x x x 0 Data Octet 1 x x x x b a x x x x x x x x x x x x x x Data Octet 1 x x x x U_Ackn .req 0 1 0 n Data Octet N x x x x x x x Data Octet N x x x x x Checksum Checksum x x x x x x x x w2.6 ms silence x x x x Immediate Ackn x x x x U_FrameState .ind re ce te 1 0 0 1 1 Figure 50. Receive Frame, SPI or 8−bit UART Mode, Frame End with Silence, No CRC−CCITT www.onsemi.com 47 NCN5121 Host Ctrl NCN5121 KNX Bus Control Byte L_Data .ind x 0 r 1 p1 p0 0 x 0 0 x x x x x x x x x x x x x 0 x x b a x x x x x x x x x x x x x x Data Octet 1 Data Octet 1 x x x x x x U_Ackn .req 0 1 0 n Data Octet N Data Octet N x x x x x x x x x x x x Checksum Checksum x x x x x x x x x x x x Immediate Ackn w2.6 ms silence x x x x Figure 51. Receive Frame, 9−bit UART Mode, Frame End with Silence, No CRC−CCITT Host Ctrl NCN5121 KNX Bus Control Byte L_Data.ind x 0 r 1 p1 p0 0 x 0 0 x x x x x x x x x x x x x 0 x x b a x x x x x x x x x x x x Data Octet 1 Data Octet 1 x x x x x x U_Ackn.req 0 1 0 n Data Octet N Data Octet N x x x x x x x x x x x x Checksum Checksum x x x x x x x x x x x x CRC−CCITT High Byte x x x x x x x x Immediate Ackn CRC−CCITT Low Byte x x x x x x x x x x x x x x w2.6ms silence Figure 52. Receive Frame, 9−bit UART Mode, Frame End with Silence, with CRC−CCITT www.onsemi.com 48 NCN5121 Host Ctrl NCN5121 KNX Bus Control Byte L_Data.ind x 0 r 1 p1 p0 0 x 0 0 x x x x x x x x x x x x x 0 x x b a x x x x x x x x x x x x Data Octet 1 Data Octet 1 x x x x x x U_Ackn.req 0 1 0 n Data Octet N Data Octet N x x x x x x x x x x x x Checksum Checksum x x x x x x x x x x x x CRC−CCITT High Byte x x x x x x x x Immediate Ackn CRC−CCITT Low Byte x x x x x x x x x x x x x x w2.6ms silence U_FrameState.ind re ce te 1 0 res 1 1 Figure 53. Receive Frame, SPI or 8−bit UART Mode, Frame End with Silence, with CRC−CCITT Host Ctrl NCN5121 KNX Bus Control Byte L_Data.ind x 0 r 1 p1 p0 0 x 0 0 x x x x x x x x x x x x x x 0 x x b a x x x x x x x x x x x Data Octet 1 Data Octet 1 x x x x x x U_Ackn.req 0 1 0 n Data Octet N Data Octet N x x x x x x x x x x x x Checksum Checksum x x x x x x x x x x x x U_FrameEnd.ind 1 1 0 0 1 0 1 1 Immediate Ackn U_FrameState.ind re ce te 1 res 0 1 x x x x x x 1 Figure 54. Receive Frame, All Modes, Frame End with MARKER, No CRC−CCITT www.onsemi.com 49 NCN5121 Host Ctrl NCN5121 KNX Bus Control Byte L_Data.ind x 0 r 1 p1 p0 0 x 0 0 x x x x x x x x x x x x x 0 x x b a x x x x x x x x x x x x x x Data Octet 1 Data Octet 1 x x x x x x U_Ackn .req 0 1 0 n Data Octet N Data Octet N x x x x x x x x x x x x Checksum Checksum x x x x x x x x x x x x U_FrameEnd .ind 1 1 0 0 1 0 1 1 Immediate Ackn U_FrameState .ind re ce te 1 res 0 1 x x x x 1 CRC −CCITT High Byte x x x x x x x x CRC −CCITT Low Byte x x x x x x x x Figure 55. Receive Frame, All Modes, Frame End with MARKER, with CRC−CCITT re (receive error): ce (checksum or length error): te (timing error) : ‘1’ if newly received frame contained corrupted bytes (wrong parity, wrong stop bit or incorrect bit timings) ‘1’ if newly received frame contained wrong checksum or length which does not correspond to the number of received bytes ‘1’ if newly received frame contained bytes whose timings do not comply with the KNX standard Reserved for future use (will be ‘0’). res (reserved) : Remarks on Figures 50 to 55: − x = don‘t care (in respect with KNX standard) − See Tables 12 and 13 for more details on all the bits − Code of U_FrameEnd.ind (0xCB) can also be part of the KNX frame content (Data Octet). To make a distinguish between a data octet and U_FrameEnd.ind, NCN5121 duplicates the data content (if 0xCB). This will result in 2 bytes transmitted to the host controller (two times 0xCB) corresponding to 1 byte received on the KNX bus. Above is only valid if frame end with MARKER is enabled. − See p53 for info on CRC−CCITT. Slave Polling Frame Service Upon reception and consistency check of the polling control byte, the control byte is send back to the host controller (L_Poll_Data.ind). The host controller will send the slot number to the device (U_PollingState.req), followed by the polling address and the polling state. At the same time the source address, polling address, slot count and checksum is received over the KNX bus. If the polling address received from the KNX bus is equal to the polling address received from the host controller, NCN5121 will send the polling data in the slot as define by U_PollingState.req (only if the slotcount is higher as the define slot). U_PollingState.req can be sent at any time (not only during a transmission of a polling telegram). The information is stored internally in NCN5121 and can be reused for further polling telegrams if auto−polling function gets activated. www.onsemi.com 50 NCN5121 Host Ctrl NCN5121 KNX Bus Control Byte L_Poll_Data.ind 1 1 1 1 0 0 0 1 1 0 s s s x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 1 0 0 0 0 x x x x x x Source Address x x x x x x x x x x x x x x x x x x x x x x Poll Address x x x x x Poll Address PollState x x s PollAddrLow x 1 Source Address PollAddrHigh x 1 0 U_PollingState .req 1 1 x x x x x Slot Count x x x x Checksum x x Slot 0 x x Slot N x x Figure 56. Slave Polling Frame Service Remarks: x = don’t care (in respect with KNX standard) ssss = slot number Master Polling Frame Service When NCN5121 receives the polling frame from the host controller, the polling frame will be transmitted over the KNX bus. www.onsemi.com 51 NCN5121 Host Ctrl NCN5121 KNX Bus Control Byte 1 1 x x x x x x x x x x x x 1 1 0 0 0 0 Source Address x x x x x x Source Address x x x x x x x x x x x x x x Poll Address x x x x Poll Address x x x x Slot Count x x x x Checksum x x x x Control Byte L_Poll_Data.ind 1 1 1 1 0 0 0 x x x x x x 1 x x x x x x x x x x x x x x x x x x x 0 1 1 0 0 0 0 Source Address Source Address x 1 x x x x x x x x x x x x x x x x x x x x x x x x U_PollingState .req 1 1 1 0 s s s s Source Address Source Address x x x x x x x x x x x x x x x x x x x x x x Poll Address PollAddrHigh x x x x x x Poll Address x x x x Poll Address PollAddrLow x x x x x x x x x x x x x x x x Poll Address x x x x Slot Count PollState x x x x x x x x x x x x x x x x Slot Count x x x x Checksum Checksum x x x x x x x x x x Slot 0 Slot 0 x x x x x x x x x x Slot N Slot N x x x x x x x x x x Figure 57. Master Polling Frame Service Remarks: x = don‘t care (in respect with KNX standard) ssss = slot number www.onsemi.com 52 NCN5121 CRC−CCITT CRC order − 16 bit CRC polynom (hex) − 1021 Initial value (hex) − FFFF Final XOR value (hex) − 0 No reverse on output CRC Test string „123456789“ is 29B1h CRC−CCITT value over a buffer of bytes can be calculated with following code fragment in C, where pBuf is pointer to the start of frame buffer uLength is the frame length in bytes unsigned short calc_CRC_CCITT(unsigned char* pBuf, unsigned short uLength) { unsigned short u_crc_ccitt; for (u_crc_ccitt = 0xFFFF; uLength−−; p++) { u_crc_ccitt = get_CRC_CCITT(u_crc_ccitt, *p); } return u_crc_ccitt; } unsigned short get_CRC_CCITT(unsigned short u_crc_val, unsigned char btVal) { u_crc_val = ((unsigned char)(u_crc_val >> 8)) | (u_crc_val > 4; u_crc_val ^= u_crc_val