NCP81061MNTWG

NCP81061 VR12 Compatible Synchronous Buck Dual MOSFET Driver http://onsemi.com MARKING DIAGRAM 1 QFN16 CASE 485AW Features • • Typical Applications • Power Management solutions for Desktop and Server Systems 81061 A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (*Note: Microdot may be in either location) DRVH1 Adaptive Anti−Cross−Conduction Circuit Integrated Bootstrap Diode Pre OV Function ZCD Detect Floating Top Driver Accommodates Boost Voltages of up to 35 V Output Disable Control Turns Off Both MOSFETs Under−voltage Lockout Power Saving Operation Under Light Load Conditions Direct Interface to NCP6151 and Other Compatible PWM Controllers Thermally Enhanced Package This is a Pb−Free Device 1 16 PWM1 2 15 SW1 EN1 3 14 GND1 VCC1 4 13 DRVL1 12 DRVH2 FLAG 17 BST2 5 PWM2 6 11 SW2 EN2 7 10 GND2 9 VCC2 8 DRVL2 • • • • • • • • • 81061 ALYWG G BST1 The NCP81061 is a high performance dual MOSFET gate driver optimized to drive the gates of both high−side and low−side power MOSFETs in a synchronous buck converter. It can drive a 3 nF load with a 30 ns propagation delay and a 30 ns transition time. Adaptive anti−cross−conduction and power saving operation circuit can provide a low switching loss and high efficiency solution for notebook and desktop systems. The Bidirectional EN pins can provide a fault signal to the controller when the gate driver detects an OVP or UVLO fault. Also, an under−voltage lockout function guarantees the outputs are low when supply voltage is low. Pin Connections (Top View) ORDERING INFORMATION Device Package Shipping† NCP81061MNTWG QFN16 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2013 May, 2013 − Rev. 0 1 Publication Order Number: NCP81061/D NCP81061 BST1 VCC1 DRVH1 PWM1 Logic SW1 Anti−Cross Conduction VCC1 DRVL1 EN1 ZCD Detection UVLO Pre−OV Fault VCC2 BST2 DRVH2 PWM2 Logic SW2 Anti−Cross Conduction VCC2 DRVL2 EN2 ZCD UVLO Fault Detection Pre−OV Figure 1. Block Diagram http://onsemi.com 2 NCP81061 PIN DESCRIPTIONS Pin No. Symbol Description 1, 5 BST1, BST2 Floating bootstrap supply pin for high side gate driver. Connect the bootstrap capacitor between this pin and the SW pin. 2, 6 PWM1, PWM2 3, 7 EN1, EN2 4, 8 VCC1, VCC2 9, 13 DRVL1, DRVL2 10, 14 GND1, GND2 11, 15 SW1, SW2 12, 16 DRVH1, DRVH2 17 FLAG Control input. The PWM signal has four distinctive states: Low = Low Side FET Enabled, Mid = Diode Emulation Enabled, High = High Side FET Enabled. Logic input. A logic high to enable the part and a logic low to disable the part. Power supply input. Connect a bypass capacitor (0.1 mF) from this pin to ground. Low side gate drive output. Connect to the gate of low side MOSFET. Bias and reference ground. All signals are referenced to this node. Switch node. Connect this pin to the source of the high side MOSFET and drain of the low side MOSFET. High side gate drive output. Connect to the gate of high side MOSFET. Thermal flag. There is no electrical connection to the IC. Connect to ground plane. APPLICATION CIRCUIT ABSOLUTE MAXIMUM RATINGS ELECTRICAL INFORMATION Pin Symbol Pin Name VMAX VMIN VCC1, VCC2 Main Supply Voltage Input 15 V −0.3 V BST1, BST2 Bootstrap Supply Voltage 35 V wrt/ GND 40 V ≤ 50 ns wrt/ GND 15 V wrt/ SW −0.3 V wrt/SW SW1, SW2 Switching Node (Bootstrap Supply Return) 35 V 40 V ≤ 50 ns −5 V −10 V (200ns) DRVH1, DRVH2 High Side Driver Output BST + 0.3 V −0.3 V wrt/SW −2 V ( POR SUPPLY CURRENT ICC + IBST, EN = 5 V, PWM = OSC, Fsw = 100 kHz, ClLOAD = 3 nF 24.4 Standby Current ICC + IBST, EN=GND 1.0 Standby Current ICC + IBST, EN = HIGH, PWM = LOW, No loading on DRVH & DRVL 4.2 mA Standby Current ICC + IBST, EN = HIGH, PWM = HIGH, No loading on DRVH & DRVL 4.4 mA Normal mode mA 3.8 mA BOOTSTRAP DIODE Forward Voltage VVCC = 12 V, forward bias current = 2 mA 0.1 0.4 0.6 V PWM INPUT PWM Input High 3.4 PWM Mid−State 1.3 V PWM Input Low ZCD blanking timer 2.7 V 0.7 V 250 ns HIGH SIDE DRIVER (VCC = 12 V) Output Impedance, Sourcing Current VBST−VSW = 12 V 2.0 3.5 W Output Impedance, Sinking Current VBST−VSW = 12 V 1.0 2.0 W DRVH Rise Time trDRVH VVCC =12 V, 3 nF load, VBST−VSW = 12 V 16 30 ns DRVH Fall Time tfDRVH VVCC =12 V, 3 nF load, VBST−VSW = 12 V 11 25 ns 30 ns 30 ns DRVH Turn−Off Propagation Delay tpdlDRVH CLOAD = 3 nF DRVH Turn−On Propagation Delay tpdhDRVH CLOAD = 3 nF SW pull down resistance SW to PGND 45 kW DRVH to SW, BST−SW = 0 V 45 kW Output Impedance, Sourcing Current VBST−VSW = 5 V 4.5 W Output Impedance, Sinking Current VBST−VSW = 5 V 2.9 W DRVH Rise Time trDRVH VVCC = 5 V, 3 nF load, VBST−VSW = 5 V 30 ns DRVH Fall Time tfDRVH VVCC = 5 V, 3 nF load, VBST−VSW = 5 V 27 ns DRVH Turn−Off Propagation Delay tpdlDRVH CLOAD = 3 nF 20 ns DRVH Turn−On Propagation Delay tpdhDRVH CLOAD = 3 nF 27 ns SW to PGND 45 kW DRVH to SW, BST−SW = 0 V 45 kW DRVH pull down resistance 8.0 HIGH SIDE DRIVER (VCC = 5 V) SW pull down resistance DRVH pull down resistance http://onsemi.com 4 NCP81061 NCP81061 DRIVER ELECTRICAL CHARACTERISTICS Unless otherwise stated −10°C < TA < +125°C; VCC1/VCC2 = 4.5 V ~ 13.2 V Parameter Test Conditions Min Typ Max Unit 2.0 3.5 W LOW SIDE DRIVER (VCC = 12 V) Output Impedance, Sourcing Current Output Impedance, Sinking Current 0.8 1.8 W DRVL Rise Time trDRVL CLOAD = 3 nF 16 35 ns DRVL Fall Time tfDRVL CLOAD = 3 nF 11 15 ns DRVL Turn−Off Propagation Delay tpdlDRVL CLOAD = 3 nF 35 ns DRVL Turn−On Propagation Delay tpdhDRVL CLOAD = 3 nF 30 ns DRVL pull down resistance 8.0 DRVL to PGND, VCC = PGND 45 kW Output Impedance, Sourcing Current 4.5 W Output Impedance, Sinking Current 2.4 W LOW SIDE DRIVER (VCC = 5 V) DRVL Rise Time trDRVL CLOAD = 3 nF 30 ns DRVL Fall Time tfDRVL CLOAD = 3 nF 22 ns DRVL Turn−Off Propagation Delay tpdlDRVL CLOAD = 3 nF 27 ns DRVL Turn−On Propagation Delay tpdhDRVL CLOAD = 3 nF 12 ns DRVL to PGND, VCC = PGND 45 kW DRVL pull down resistance EN INPUT Input Voltage High 2.0 V Input Voltage Low 1.0 Hysteresis V 500 Normal mode bias current −1 Fault mode Enable pin pull down current 4 Propagation Delay Time 20 mV 1 mA 30 mA 40 ns 20 mA SW Node SW node leakage current Zero Cross Detection Threshold Voltage SW to −20 mV, ramp slowly until BG go off. (start in DCM mode) −6 mV DECODER TRUTH TABLE PWM INPUT ZCD DRVL DRVH PWM High ZCD Reset Low High PWM Mid Positive current through the inductor High Low PWM Mid Zero current through the inductor Low Low PWM Low ZCD Reset High Low http://onsemi.com 5 NCP81061 1V 1V Figure 2. Figure 3. Timing Diagram http://onsemi.com 6 NCP81061 APPLICATION INFORMATION Adaptive Non−overlap The NCP81061 gate driver is a dual phase MOSFET driver designed for driving N−channel MOSFETs in a synchronous buck converter topology. The NCP81061 is designed to work with ON Semiconductor’s NCP6151 multi−phase controller. The non−overlap dead time control is used to avoid shoot−through current from damaging the power MOSFETs. When the PWM signal is pulled high, DRVL will start to go low after a propagation delay (tpdlDRVL). The driver will monitor the DRVL voltage until a threshold where an internal timer (tpdhDRVH) will delay turn−on of the high−side MOSFET. When the PWM signal is pulled low, DRVH will start to go low after a propagation delay (tpdlDRVH). The driver will monitor the difference between the DRVH and SW voltages until a threshold where an internal timer (tpdhDRVL) delays turn−on of the low−side MOSFET. Under−voltage Lockout DRVH and DRVL are held low until VCC reaches 4.5 V during start−up. The PWM signals will control the gate status when the VCC threshold is exceeded. If VCC decreases to 200 mV below the threshold, the driver outputs will be forced low until VCC rises above the start−up threshold. Power−On Reset The power−on reset feature is used to protect a gate driver from abnormal status during start−up. When the initial VCC soft−start voltage is higher than 2.75 V, the gate driver will monitor the SW pin. If the SW pin is higher than 2.25 V, bottom gate will be forced high to discharge the output capacitor. The fault mode will be latched and the EN pin will be forced low until the driver is recycled. When the VCC voltage is higher than 4.5 V, and EN is high, the driver will enter normal operation. Layout Guidelines Layout for DC−DC converter is very important. The bootstrap and VCC bypass capacitors should be placed as close the driver IC as possible. Connect GND pin to a local ground plane. The ground plane can provide a good return path for gate drives and reduce the ground noise. The thermal slug should be tied to the ground plane for good heat dissipation. To minimize the ground loop for low side MOSFET, the driver GND pin should be close to the low−side MOSFET source pin. The gate drive trace should be routed to minimize the length, with a minimum width of 20 mils. Bi−directional EN Signal When the driver is in a fault mode such as Power−On Reset and Under−Voltage Lockout, it will de−assert the EN pin by pulling it low. This will pull down the DRON pin of the controller as well. Gate Driver Power Loss Calculation The gate driver power loss consists of the gate drive loss and quiescent power loss. The equation below can be used to calculate the power dissipation of the gate driver. Where QGMF is the total gate charge for each main MOSFET and QGSF is the total gate charge for each synchronous MOSFET. PWM Input and Zero Cross Detect (ZCD) The PWM input, along with EN and ZCD, control the state of DRVH and DRVL. When PWM is set high, DRVH will be set high after the adaptive non−overlap delay. When PWM is set low, DRVL will be set high after the adaptive non−overlap delay. When the PWM is set to the mid state, DRVH will be set low, and after the adaptive non−overlap delay, DRVL will be set high. DRVL remains high during the ZCD blanking time. When the timer is expired, the SW pin will be monitored for zero cross detection. After the detection, the DRVL will be set low. P DRV + ƪ f SW 2xn V CC http://onsemi.com 7 ǒn MF Q GMF ) n SF ƫ Q QFSǓ ) ICC NCP81061 PACKAGE DIMENSIONS QFN16, 2.5x3.5, 0.5P CASE 485AW ISSUE O D PIN ONE REFERENCE A B ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ 2X DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E TOP VIEW MOLD CMPD DETAIL B ALTERNATE CONSTRUCTIONS A DETAIL B (A3) 0.10 C MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.50 BSC 0.85 1.15 3.50 BSC 1.85 2.15 0.50 BSC 0.20 --0.35 0.45 --0.15 DIM A A1 A3 b D D2 E E2 e K L L1 ÇÇÇ ÇÇÇ ÉÉÉ EXPOSED Cu 0.15 C L L1 0.15 C 2X 16X L NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSIONS b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A1 0.08 C NOTE 4 C SIDE VIEW SEATING PLANE SOLDERING FOOTPRINT* 0.15 C A B 3.80 D2 16X L 8 10 DETAIL A 2.10 K 0.50 PITCH 0.15 C A B 2.80 1.10 E2 16X 2 15 e 1 1 b 0.10 C A B 0.05 C 16X 0.60 NOTE 3 16X 0.30 PACKAGE OUTLINE DIMENSIONS: MILLIMETERS e/2 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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