NCN5193
HART Modem
Description
The NCN5193 is a single−chip, CMOS modem for use in highway
addressable remote transducer (HART) field instruments and masters.
The modem and a few external passive components provide all of the
functions needed to satisfy HART physical layer requirements
including modulation, demodulation, receive filtering, carrier detect,
and transmit−signal shaping. In addition, the NCN5193 also has an
integrated DAC for low-BOM current loop slave transmitter
implementation.
The NCN5193 uses phase continuous frequency shift keying (FSK)
at 1200 bits per second. To conserve power the receive circuits are
disabled during transmit operations and vice versa. This provides the
half−duplex operation used in HART communications.
Features
•
•
•
•
•
•
•
•
•
•
•
•
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Single−chip, Half−duplex 1200 Bits per Second FSK Modem
Bell 202 Shift Frequencies of 1200 Hz and 2200 Hz
1.8 V − 3.5 V Power Supply
Transmit−signal Wave Shaping
Receive Band−pass Filter
Low Power: Optimal for Intrinsically Safe Applications
Compatible with 1.8 V or 3.3 V Microcontroller
Internal Oscillator Requires 460.8 kHz, 920 kHz, 1.84 MHz or
3.68 MHz Crystal or Ceramic Resonator
SPI Communication
Integrated 17 bit Sigma-Delta DAC
Meets HART Physical Layer Requirements
Industrial Temperature Range of −40°C to +85°C
Available in 32−pin NQFP Package
These are Pb−Free Devices
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MARKING
DIAGRAM
1
1
32
QFN32
CASE 485EK
NCN
5193
AWLYYWWG
G
NCN5193 = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
Applications
• HART Multiplexers
• HART Modem Interfaces
• 4 − 20 mA Loop Powered Transmitters
© Semiconductor Components Industries, LLC, 2016
July, 2018 − Rev. 6
1
Publication Order Number:
NCN5193/D
NCN5193
BLOCK DIAGRAM
VDD
RxAFI
VDDA
RxAF
RxAP
Demodulator
Logic
RxD
RxAN FSK_IN
Rx Comp
Filter Amplifier
AREF
Carrier Detect
Counter
CD
CDREF
Carrier Comp
Numeric
Controlled
Oscillator
TxD
DEMODULATOR
TxA
Sine
Shaper
RTS
FSK_OUT
MODULATOR
NCN5193
CS
SCLK
DATA
SPI
Registers
DAC
VPOR
KICK
RESET
POR
BIAS
Crystal
Oscillator
VSS
CBIAS
MODE
JUMP
DAC
DACREF
TEST1
TEST2
CLK1
CLK2
XOUT XIN
Figure 1. Block Diagram NCN5193
ELECTRICAL SPECIFICATIONS
Table 1. ABSOLUTE MAXIMUM RATINGS (Note 1)
Parameter
Symbol
Min
Max
Units
TA
Ambient Temperature
−40
+85
°C
TS
Storage Temperature
−55
+150
°C
TJ
Junction Temperature
−40
+85
°C
Supply Voltage
−0.3
4.0
V
DC Input, Output
−0.3
VDD + 0.3
V
VDD
VIN, VOUT
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. CMOS devices are damaged by high−energy electrostatic discharge. Devices must be stored in conductive foam or with all pins shunted.
Precautions should be taken to avoid application of voltages higher than the maximum rating. Stresses above absolute maximum ratings
may result in damage to the device.
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NCN5193
Table 2. DC CHARACTERISTICS (VDD = 1.8 V to 3.5 V, VSS = 0 V, TA = −40°C to +85°C)
Parameter
Symbol
VDD
VDD
DC Supply Voltage
VIL
Input Voltage, Low
1.8 – 3.5 V
VIH
Input Voltage, High
1.8 – 3.5 V
Min
Typ
Max
Units
3.5
V
0.2 * VDD
V
1.8
VOL
Output Voltage, Low (IOL = 0.67 mA)
1.8 – 3.5 V
VOH
Output Voltage, High (IOH = −0.67 mA)
1.8 – 3.5 V
IIL/IIH
Input Leakage Current
0.8 * VDD
V
0.4
V
VDD − 0.4
V
mA
500
mA
IDD
Total Power Supply Current
70
IDDA
Static Analog Supply Current
45
270
mA
IDDQ
Static Digital Current
0
30
mA
IDDD
Dynamic Digital Current
25
200
mA
AREF
Analog Reference
1.2
2.6
V
CDREF
(Note 2)
IBIAS
190
±1
1.235
Carrier Detect Reference (AREF – 0.08 V)
1.15
V
Comparator Bias Current
(RBIAS = 120 kW, AREF = 1.235 V)
2.5
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. The HART specification requires carrier detect (CD) to be active between 80 and 120 mVp−p. Setting CDREF at AREF − 0.08 VDC will set
the carrier detect to a nominal 100 mVp−p.
Table 3. AC CHARACTERISTICS (VDD = 1.8 V to 3.5 V, VSS = 0 V, TA = −40°C to +85°C) (Note 3)
Pin Name
RxAP, RxAN
RxAF
RxAFI
TxA
RxD
CD
Description
Min
Typ
Max
Units
Receive analog input
Leakage current
Frequency – mark (logic 1)
Frequency – space (logic 0)
1190
2180
1200
2200
±150
1210
2220
nA
Hz
Hz
Output of the high−pass filter
Slew rate
Gain bandwidth (GBW)
Voltage range
300
0.15
VDD – 0.15
V/ms
kHz
V
±500
nA
0.04
Carrier detect and receive filter input
Leakage current
Modulator output
Frequency – mark (logic 1)
Frequency – space (logic 0)
Amplitude (IAREF 1.235 V)
Slew Rate − mark (logic 1)
Slew Rate − space (logic 0)
Loading (IAREF = 1.235 V)
1196.9
2194.3
500
1860
3300
Hz
Hz
mV
V/s
V/s
kW
30
Receive digital output
Rise/fall time
20
ns
Carrier detect output
Rise/fall time
20
ns
3. The modulator output frequencies are proportional to the input clock frequency (460.8 kHz/920 kHz/1.84 MHz / 3.68 MHz).
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NCN5193
Table 4. MODEM CHARACTERISTICS (VDD = 1.8 V to 3.5 V, VSS = 0 V, TA = −40°C to +85°C)
Min
Parameter
Typ
Demodulator jitter
Conditions
1. Input frequencies at 1200 Hz ± 10 Hz, 2200 Hz ± 20 Hz
2. Clock frequency of 460.8 kHz ± 0.1%
3. Input (RxAP) asymmetry, 0
Max
Units
12
% of 1 bit
Max
Units
1.0
%
65
%
V
Max
Units
Table 5. CERAMIC RESONATOR AND CRYSTAL − External Clock Specifications
(VDD = 1.8 V to 3.5 V, VSS = 0 V, TA = −40°C to +85°C)
Min
Parameter
Typ
460.8 kHz / 920 kHz / 1.84 MHz / 3.68 MHz Ceramic resonator
or crystal oscillation frequency tolerance
External Clock
Duty cycle
Amplitude
35
50
VOH − VOL
Table 6. DAC CHARACTERISTICS (VDD = 3.0 V to 5.5 V, VSS = 0 V, TA = −40°C to +85°C)
Min
Parameter
Typ
Bandwidth (Note 4)
25
Hz
Resolution
17
Bit
Maximum Output
Return−to−Zero
V
AVDD/2
4. The DAC is a sigma−delta type modulator. Therefore, the bandwidth is determined by the external filter. Decreasing the bandwidth will
increase DAC accuracy.
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NCN5193
TYPICAL APPLICATION
C4
R6
R5
VDDA
1.8 V − 3.5 V
C6
R10
R11
VDD
VDDA
RxAFI
C5
RxAF
R8
RxAN
R9
R3 C3 C2 C1
RESET
VPOR
RxAP
HART IN
KICK
R12
R7
R4 R2
R1
RxD
VDDA
CD
R16
AREF
TxD
RTS
μC
R14
NCN5193
R15
U2
CDREF
CS
TxA
DATA
S
HART &
4 – 20 mA OUT
SCLK
VDDA
CLK1
DAC
CLK2
JUMP
DACREF
XOUT
3.6864 MHz
C7
XT1
TEST2
TEST1
XIN
CBIAS
C8
VSS
MODE
R13
U1
Figure 2. Application Diagram NCN5193
Table 7. TYPICAL BILL OF MATERIALS
Reference Designator
Value (Typical)
Tolerance
Manufacturer
Part Number
U1
−
−
ON Semiconductor
NCN5193
ON Semiconductor
LM285
Raltron
AS−3.6864−18
U2
−
−
R1, R2
1.5M
1%
R3, R5
806k
1%
R4
1.3M
1%
R6
174k
1%
R7
2.2M
1%
R8, R9
422k
1%
R11
240k
1%
R12, R15, R10
200k
1%
R13
120k
1%
R14, R16
14k7
1%
C1
1 nF
5%
C2
470 pF
5%
C3
200 pF
5%
C4
220 pF
5%
C5
20 pF
5%
C6
330 pF
5%
C7, C8
18 pF
10%
XT1
3.6864 MHz
100 ppm
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5
MODE
CD
RxD
25
DACREF
28
26
DAC
29
27
CLK1
VDD
30
CLK2
31
32
NCN5193
SCLK
1
24
DATA
2
23
TxD
JUMP
3
22
RTS
KICK
4
21
TEST2
CS
5
20
TEST1
VSS
6
19
VSS
TxA
7
18
XIN
AREF
8
17
XOUT
12
13
14
15
16
RxAP
RxAF
RxAFI
VPOR
RxAN
11
CBIAS
VDDA
9
10
CDREF
NCN5193
RESET
Figure 3. Pin Out NCN5193 in 32-pin NQFP (top view)
Table 8. PIN OUT SUMMARY 32−PIN NQFP
Pin No.
Signal Name
Type
Pin Description
1
SCLK
Input
SPI Serial Clock
2
DATA
Input
SPI Serial Data
3
JUMP
Input
Sigma−Delta Modulator Alarm condition value
4
KICK
Input
Watchdog kick
5
CS
Input
SPI Serial Chip Select
6
VSS
Ground
Ground
7
TxA
Output
Transmit Data Modulator output
8
AREF
Input
Analog reference voltage
9
CDREF
Input
Carrier detect reference voltage
10
CBIAS
Output
Comparator bias current
11
VPOR
Input
POR measurement point
Receive filter amplifier negative terminal
12
RxAN
Input
13
VDDA
Power
14
RxAP
Input
15
RxAF
Output
16
RxAFI
Input
17
XOUT
Output
18
XIN
Input
19
VSS
Ground
20
TEST1
Input
Test pin. Tie to GND
21
TEST2
Input
Test pin. Tie to VDD
22
RTSB
Input
Request to send
Input transmit data, transmit HART data stream from microcontroller
Analog supply voltage
Receive filter amplifier positive terminal
Analog receive filter output
Analog receive comparator input
Crystal oscillator output
Crystal oscillator input
Ground
23
TxD
Input
24
RESETB
Open Drain
25
RxD
Output
Received demodulated HART data to microcontroller
26
CD
Output
Carrier detect output
27
MODE
Input
Mode pin to select external or internal oscillator
28
DACREF
Input
Sigma−Delta Modulator Reference Voltage
29
DAC
Output
Sigma−Delta Modulator Output
Reset all digital logic when low
30
VDD
Power
Digital supply voltage
31
CLK1
Output
Programmable Clock Output 1
32
CLK2
Output
Programmable Clock Output 2
−
EP
Ground
Exposed pad. Connect to GND
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NCN5193
Table 9. PIN DESCRIPTIONS
Symbol
Pin Name
Description
AREF
Analog reference voltage
Receiver Reference Voltage. See Table 2.
CDREF
Carrier detect reference voltage
Carrier Detect Reference voltage. The value should be 80 mV below AREF to set the
carrier detection to a nominal of 100 mVp−p.
RESETB
Reset digital logic
When at logic low (VSS) this input holds all the digital logic in reset. During normal
operation RESETB should be at VDD.
RTSB
Request to send
Active−low input selects the operation of the modulator. TxA is enabled when this
signal is low. This signal must be held high during power−up.
RxAP
Analog filter amplifier positive
terminal
Positive terminal of the receive filter. For a reference implementation of the receive
filter see Figure 2
RxAN
Analog filter amplifier positive
terminal
Negative terminal of the receive filter. For a reference implementation of the receive
filter see Figure 2
RxAFI
Analog receive comparator input
Positive input of the carrier detect comparator and the receiver filter comparator.
TxD
Digital transmit input
Input to the modulator accepts digital data in NRZ form. When TxD is low, the modulator output frequency is 2200 Hz. When TxD is high, the modulator output frequency
is 1200 Hz.
XIN
Oscillator input
Input to the internal oscillator must be connected to a parallel mode ceramic resonator
when using the internal oscillator or grounded when using an external clock signal.
XOUT
Oscillator output
Output from the internal oscillator must be connected to an external clock signal or to
a parallel mode ceramic resonator when using the internal oscillator.
CLK1
Programmable Clock Output
Output signal derived from oscillator output, frequency division set by internal register.
CLK2
Programmable Clock Output
Output signal derived from oscillator output, frequency division set by internal register.
CBIAS
Comparator bias current
Connection to the external bias resistor. RBIAS should be selected such that AREF /
RBIAS = 10 mA ± 5%
CD
Carrier detect output
Output goes high when a valid input is recognized on RxA. If the received signal is
greater than the threshold specified on CDREF for four cycles of the RxA signal, the
valid input is recognized.
RxAF
Analog receive filter output
The output of the three pole high pass receive data filter
RxD
Digital receive output
Signal outputs the digital receive data. When the received signal (RxA) is 1200 Hz,
RxD outputs logic high. When the received signal (RxA) is 2200 Hz, RxD outputs logic
low. The HART receive data stream is only active if Carrier Detect (CD) is high.
MODE
TxA
Digital input
Analog transmit output
Selects the clock source. Connecting this pin to VDD disables the internal oscillator.
The chip then requires an external clock source. Connecting this pin to VSS enables
the internal oscillator to drive the external crystal or ceramic resonator
Transmit Data Modulator Output. A trapezoidal shaped waveform with a frequency of
1200 Hz or 2200 Hz corresponding to a data value of 1 or 0 respectively applied to
TxD. TxA is active when RTSB is low. TxA equals 0.5 V when RTSB is high.
SCLK
SPI bus clock line
Serial communication clock line
DATA
SPI bus data line
Serial communication data line.
CS
SPI bus chip select
Serial communication chip select line. Pulled high by microcontroller while a frame is
transmitted.
JUMP
DAC Alarm value
When a problem is detected, such as a clock failure or the watchdog going off, the DAC
will jump to VSS or DACREF, depending on whether this pin is connected to VSS or
VDD respectively.
DACREF
DAC Reference
This is the high value of the output and can be connected to any voltage between AREF
and VDD.
DAC
DAC Output
Output of a 17 bit Sigma−Delta Modulator
KICK
Watchdog Kick
Periodically a pulse should be provided to reset the watchdog. This can be configured in
internal registers for an internal 1.8kHz signal, or to an external signal provided to this pin.
VPOR
POR Input
Input to the POR comparator. The voltage on this pin is compared with AREF. An external resistor divider should divide the supply voltage to this pin.
VDD
Digital power
Power for the digital modem circuitry
VDDA
Analog supply voltage
Power for the analog modem circuitry
VSS
Ground
Digital ground
VSSA
Analog ground
Analog ground
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NCN5193
Functional Description
The NCN5193 is a single-chip modem for use in Highway
Addressable Remote Transducer (HART) field instruments
and masters. The modem IC contains a transmit data
modulator with signal shaper, carrier detect circuitry, an
analog receiver, demodulator circuitry and an oscillator, as
shown in the block diagram in Figure 1.
The modulator accepts digital data at its digital input TxD
and generates a trapezoidal shaped FSK modulated signal at
the analog output TxA. A digital “1” or mark is represented
with a frequency of 1200 Hz. A digital “0” or space is
represented with a frequency of 2200 Hz. The used bit rate
is 1200 baud.
The demodulator receives the FSK signal at its analog
input, filters it with a band-pass filter and generates 2 digital
signals: RxD: Received Data and CD: Carrier Detect. At the
digital output RxD the original modulated signal is received.
CD outputs the Carrier Detect signal. It goes logic high if the
received signal is above 100 mVpp during 4 consecutive
carrier periods.
The oscillator provides the modem with a stable time base
using either a simple external resonator or an external clock
source.
The Numeric Controlled Oscillator (NCO) works in a
phase continuous mode preventing abrupt phase shifts when
switching between mark and space frequency. The control
signal “Request To Send” (RTSB) enables the NCO. When
RTSB is logic low the modulator is active and NCN5193 is
in transmit mode. When RTSB is logic high the modulator
is disabled and NCN5193 is in receive mode.
The digital outputs of the NCO are shaped in the Wave
Shaper block to a trapezoidal signal. This circuit controls the
rising and falling edge to be inside the standard HART
waveshape limits. Figure 6 shows the transmit-signal forms
captured at TxA for mark and space frequency. The slew
rates are SRm = 1860 V/s at the mark frequency and SRs =
3300 V/s at the space frequency. For AREF = 1.235 V, TxA
will have a voltage swing from approximately 0.25 to
0.75 VDC.
VTxA
“1” = Mark; fm =1.2 kHz
0.5 V
0.5 V
SRm = 1860 V/s
0
Detailed Description
t (ms)
1
VTxA
2
“0” = Space; fs =2.2 kHz
Modulator
The modulator accepts digital data in NRZ form at the
TxD input and generates the FSK modulated signal at the
TxA output.
0.5 V
0.5 V
t (ms)
SRs = 3300 V/s
0
TxD
Numeric
Controlled
Oscillator
RTS
TxA
Sine
Shaper
1
2
KVDE20110408
Figure 6. Modulator shaped output signal for Mark
and Space frequency at TxA pin.
FSK_OUT
MODULATOR
Demodulator
PC20101117.1
The demodulator accepts a FSK signal at the RxA input
and reconstructs the original modulated signal at the RxD
output. Figure 7 illustrates the demodulation process.
Figure 4. Modulator Block Diagram
A logic “1” or mark is represented by a frequency fm =
1200 Hz. A logic “0”or space is represented by a frequency
fs = 2200 Hz.
“1” = Mark
1.2 kHz
FSK_IN
“0” = Space
2.2 kHz
RxD
LSB
IDLE (mark)
t
MSB
Start
D0
D1
D2
“0”
“1”
“0”
“1”
tBIT
IDLE (mark)
D3
D4
D5
D6
D7
Par
“0”
“0”
“1”
“0”
“1”
“0”
8 data bits
Stop
t BIT
PC20101013.4
Figure 7. Modulation Timing
tBIT = 833 ms
This HART bit stream follows a standard 11-bit UART
frame with Start, Stop, 8 Data – and 1 Parity bit (odd). The
communication speed is 1200 baud.
tBIT = 833 m s
Receive Filter and Comparator
KVDE20110407.5
The received FSK signal first is filtered using a band-pass
filter build around the low noise receiver operational
amplifier. This filter blocks interferences outside the HART
signal band.
Figure 5. Modulation Timing
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NCN5193
C4
R6
R5
C6
RxAFI
C5
R8
RxAF
R9
15 MW
RxAN
Rx Comp
R3 C3 C2 C1
RxAP
HART IN
R7
AREF
Filter Amplifier
DEMODULATOR
R4 R2
R1
1.235V
Figure 8. Demodulator Receive Filter and Signal Comparator
Carrier Detect Circuitry
The filter output is fed into the Rx comparator. The
threshold value equals the analog ground making the
comparator to toggle on every zero crossing of the filtered
FSK signal. The maximum demodulator jitter is 12% of one
bit given the input frequencies are within the HART
specifications, a clock frequency of 460.8 kHz (±1.0 %) and
zero input (RxA) asymmetry.
Low HART input signal levels increases the risk for the
generation of bit errors. Therefore the minimum signal
amplitude is set to 80−120 mVpp. If the received signal is
below this level the demodulator is disabled.
This level detection is done in the Carrier Detector. The
output of the demodulator is qualified with the carrier detect
signal (CD), therefore, only RxA signals large enough to be
detected (100 mVp-p typically) by the carrier detect circuit
produce received serial data at RxD.
FILTERED
HART IN
RxAFI
Demodulator
Logic
15 MΩ
RxD
Rx Comp
AREF
CD
Carrier Detect
Counter
1.235 VDC
CDREF
VAREF – 80 mV
Carrier Comp
DEMODULATOR
Figure 9. Demodulator Carrier and Signal Comparator
is 2200 HZ. The difference between RxD and RxD_ENH is
evident when CD is low: RxD is then also low, while
RxD_ENH is then high. When CD is high, RxD and
RxD_ENH have the same output.
The carrier detect comparator shown in Figure 9 generates
logic low output if the RxAFI voltage is below CDREF. The
comparator output is fed into a carrier detect block. The
carrier detect block drives the carrier detect output pin CD
high if RTSB is high and four consecutive pulses out of the
comparator have arrived. CD stays high as long as RTSB is
high and the next comparator pulse is received in less than
2.5 ms. Once CD goes inactive, it takes four consecutive
pulses out of the comparator to assert CD again. Four
consecutive pulses amount to 3.33 ms when the received
signal is 1200 Hz and to 1.82 ms when the received signal
Miscellaneous Analog Circuitry
Voltage References
The NCN5193 requires two voltage references, AREF
and CDREF. AREF sets the DC operating point of the
internal operational amplifiers and is the reference for the
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NCN5193
resonator. Typically, capacitors in the range of 10 pF to
470 pF are used. Additionally, a resistor may be required
between XOUT and the crystal terminal, depending on
manufacturer recommendation.
Rx comparator. The ON Semiconductor LM285D 1.235 V
reference is recommended.
The level at which CD (Carrier Detect) becomes active is
determined by the DC voltage difference (CDREF - AREF).
Selecting a voltage difference of 80 mV will set the carrier
detect to a nominal 100 mVp-p.
Bias Current Resistor
Crystal
Oscillator
The NCN5193 requires a bias current resistor RBIAS to be
connected between CBIAS and VSS. The bias current
controls the operating parameters of the internal operational
amplifiers and comparators and should be set to 2.5 mA.
XOUT
2.5 mA
BIAS
AREF/4
460.8 kHz
CX
PC20101118 . 5
XIN
CX
OPA
Figure 11. Crystal Oscillator
External Clock Option
PC20101118 .4
It may be desirable to use an external clock as shown in
Figure 12 rather than the internal oscillator. In addition, the
NCN5193 consumes less current when an external clock is
used. Minimum current consumption occurs with the clock
connected to XOUT and XIN connected to VSS.
CBIAS
RBIAS
Figure 10. Bias Circuit
The value of the bias current resistor is determined by the
reference voltage AREF and the following formula:
R BIAS +
4
Crystal
Oscillator
VREF
2.5 mA
The recommended bias current resistor is 120 KW when
AREF is equal to 1.235 V.
XOUT
XIN
PC20101118 .6
460.8 kHz
Oscillator
Figure 12. Oscillator with External Clock
The clock signal used by NCN5193 can either be
460.8 kHz, 921.6 kHz, 1.8432 MHz or 3.6864 MHz. This
can be provided by an external clock or a resonator or crystal
connected to the internal oscillator. This is selected by
connecting pin 27 to VDD (for external oscillator) or VSS
(for internal oscillator). The correct divider value must be
chosen so that the internal system clock is always 460.8 kHz.
This divider value can be set in the Clock Configuration
Register (CCR), bits 1−0. In the CCR, divider values can
also be chosen for the CLK1 and CLK2 outputs. These
values can be freely chosen and do not affect operation of the
HART transceiver.
Reset
The NCN5193 modem includes a Power on Reset block.
An external resistor division of the supply voltage is
required, and should be tied to pin VPOR. This pin is
attached to an internal comparator, and is compared to the
AREF voltage. When this comparator trips, the RESETB
pin will be pulled low and the IC will reset. After VPOR
returns to a valid level, the RESETB pin will be held low for
at least an additional 35 ms (may be longer depending on
clock frequency). The RESETB pin will also be pulled low
when a failure is detected by the watchdog timer. When the
microcontroller fails to provide a periodical kick signal,
either by a pulse on the kick pin or by an update to the
sigma−delta register (configurable in the GCR), the
watchdog will pull down the RESETB pin for 140 ms. A kick
signal should be provided to the IC at least every 53 ms. The
watchdog timer can also guard against system clock failures
if bit 2 of the GCR is set. In this case, the RESETB pin will
also be pulled low when the system clock frequency is
outside of 0.5x − 2x the nominal frequency (460.8 kHz).
Internal Oscillator Option
The oscillator cell will function with a 460.8 kHz,
921.6 kHz, 1.8432 MHz or 3.6864 MHz crystal or ceramic
resonator. A parallel resonant ceramic resonator can be
connected between XIN and XOUT. Figure 11 illustrates the
crystal option for clock generation using a 460.8 kHz (±1%
tolerance) parallel resonant crystal and two tuning
capacitors Cx. The actual values of the capacitors may
depend on the recommendations of the manufacturer of the
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10
NCN5193
CS
POR
AREF
VDD
SCLK
DATA
b7
OPA
VPOR
b6
b5
b4
b3
b2
b1
b0
Figure 14. SPI Frame
KVDE 20110408 .1
Figure 13. Power on Reset Block
Byte 0
7 6 5 4 3 2 1 0
Byte 1
7 6 5 4 3 2 1 0
Byte 2
7 6 5 4 3 2 1 0
0 1 0
W15−W8 for Reg 1, 2, 3
W7−W0 for Reg 1, 2, 3
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
W23−W16 for Reg A
W15−W8 for Reg A
W7−W0 for Reg A
Address
0
Byte 3
Figure 15. Register Write Format
SPI Communication
Once the data is shifted in, CS should go low no sooner than
one clock cycle after the last rising edge of the last byte of
SCLK. To write to a register, first a command byte must be
sent which includes the register address (as shown in Figure
15), followed by 2 bytes (for GCR, CCR, and ACR) or 3
bytes (for SDR) of data. When writing data to the GCR,
CCR, or ACR registers, the first byte must be the bitwise
inverse of the configuration data in the second byte.
The SPI bus on the NCN5193 is made up of three signals;
DATA, SCLK, and CS operating in SPI mode 1 (CPOL = 0,
CPHA = 1, as shown in Figure 14).
CS should first go high at least one clock cycle before the
other signals change. One clock cycle is 2.17 ms at a master
clock frequency of 460.8 kHz.
SCLK can begin to clock in DATA serially to the chip on
the falling edge of SCLK. SCLK should have a maximum
frequency of 460.8 kHz. The format of the data should be
most significant bit first.
DATA is shifted into the chip on the falling edge of SCLK,
and thus for correct operation DATA should change only on
the rising edge of SCLK. The first bit shifted in is the MSB.
Internal Registers
The NCN5193 has four registers to setup its internal
operation. In Tables 10 to 16 an explanation of their usage
is given, together with their reset values.
Table 10. GENERAL CONFIGURATION REGISTER (GCR)
Address
0x01
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
1
0
0
0
0
1
0
1
Data
-
-
-
RXD_IDLE
-
WDT_CLK
WDT_KICK
The general configuration register is used to set the RxD idle state, enable or disable the monitoring of the system clock and
setting the watchdog timer kick source. A write to this register should always be preceded with an inverted value to the shadow
register.
Table 11. GENERAL CONFIGURATION REGISTER PARAMETERS
Parameter
RXD_IDLE
WDT_CLK
WDT_KICK
Value
0
Low
Description
Sets the idle state for the RxD pin (when CD is low)
1
High
0
Enable
1
Disable
00
Disable
Kick signal to watchdog timer is disabled
01
External
Watchdog kick source is a pulse on the KICK pin
10
Sigma-Delta
Disable/Enable monitoring of the clock frequency by the watchdog timer.
Watchdog kick source is an write to the Sigma-Delta Data register (SDR)
11
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11
Info
NCN5193
Table 12. CLOCK CONFIGURATION REGISTER (CCR)
Address
0x02
Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
1
0
1
1
1
Data
CLK2_DIV
CLK1_DIV
SYSCLK_DIV
The clock configuration register is used to set the correct division ratios for both clock outputs and the system clock. A write
to this register should always be preceded with an inverted value to the shadow register.
Table 13. CLOCK CONFIGURATION REGISTER PARAMETERS
Parameter
CLK2_DIV
CLK1_DIV
SYSCLK_DIV
Value
Description
Info
Set the clock division value for clock output 2 (CLK2) with regard to the
oscillator frequency.
000
Divide by 1
001
Divide by 2
010
Divide by 3
011
Divide by 4
100
Divide by 5
101
Divide by 8
110
Divide by 16
111
Divide by 32
000
Divide by 1
001
Divide by 2
010
Divide by 3
011
Divide by 4
100
Divide by 5
101
Divide by 8
110
Divide by 16
111
Divide by 32
00
Divide by 1
01
Divide by 2
10
Divide by 4
11
Divide by 8
Set the clock division value for clock output 1 (CLK1) with regard to the
oscillator frequency.
Set the clock division value for the system clock with regard to the oscillator frequency. These bits must be set so the system clock is 460.8 kHz
Table 14. ANALOG CONFIGURATION REGISTER – ACR
General Configuration Register (GCR)
Address
0x03
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
1
1
1
1
1
1
0
1
Data
MOD_EN
RXAMP_EN
RXCMP_EN
CDCMP_EN
TXAMP_EN
MODDAC_EN
WDOSC_EN
SDDAC_EN
The analog configuration register is used to enable or disable various analog blocks. A write to this register should always
be preceded with an inverted value to the shadow register.
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12
NCN5193
Table 15. ANALOG CONFIGURATION REGISTER PARAMETERS
Parameter
MOD_EN
RXAMP_EN
RXCMP_EN
CDCMP_EN
TXAMP_EN
MODDAC_EN
WDOSC_EN
SDDAC_EN
Value
Description
0
Enable
1
Disable
0
Enable
1
Disable
0
Enable
1
Disable
0
Enable
1
Disable
0
Enable
1
Disable
0
Enable
1
Disable
0
Enable
1
Disable
0
Enable
1
Disable
Info
Disable/Enable the modulator/demodulator
Disable/Enable the receive filter opamp
Disable/Enable the receive comparator
Disable/Enable the carrier detect comparator
Disable/Enable the transmit output amplifier
Disable/Enable the DAC used to provide the waveshaping to the modulator
Disable/Enable the watchdog timer oscillator
Disable/Enable the sigma-delta DAC
Table 16. SIGMA-DELTA DAC REGISTER – SDR
General Configuration Register (GCR)
Address
0x0A
Bit 23:16
Bit 15:8
Bit 7
Bit 6:0
Reset
0x00
0x00
0
0x00
Data
Data 16:9
Data 8:1
Data 0
-
The sigma-delta register is used to update the output value
of the 17-bit sigma delta modulator. The sigma-delta
modulator is disabled at reset and must be enabled in the
ACR first before the value in the SDR will appear at the
sigma-delta output.
how to create a current loop slave transmitter, see
application notes on the ON Semiconductor website. The
DAC output will switch between 0 V and the voltage
provided to DACREF. To achieve maximum accuracy, the
DACREF voltage should be kept stable, so that power
supply variations are not visible in the DAC output. The
Sigma−Delta modulator output can be set through the Sigma
Delta Register (SDR). When a clock failure is detected,
using an internal oscillator, the DAC output will jump to the
level set by the JUMP pin, until the IC is reset or a rising
flank is detected on KICK.
Sigma Delta DAC
The NCN5193 Modem has an integrated Sigma−Delta
Modulator for use in a current loop slave transmitter.
Through this DAC, an analog value can be set and
transmitted across the current loop. For more information on
Ordering Information
The NCN5193 is available in a 32−pin no lead quad flat pack (NQFP). Use the following part numbers when ordering.
Contact your local sales representative for more information: www.onsemi.com.
Table 17. ORDERING INFORMATION
Part Number
NCN5193MNTWG
Temperature Range
Package
−40°C to +85°C (Industrial)
32−pin NQFP
Green/RoHS compliant
Shipping†
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN32 5x5, 0.5P
CASE 485EK
ISSUE A
DATE 29 SEP 2015
1 32
SCALE 2:1
A
D
PIN ONE
LOCATION
0.10 C
ÉÉÉ
ÉÉÉ
ÉÉÉ
0.10 C
L1
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
EXPOSED Cu
A
(A3)
A1
0.05 C
DETAIL A
9
32X
L
ALTERNATE
CONSTRUCTION
MILLIMETERS
MIN
MAX
0.80
0.90
−−−
0.05
0.20 REF
0.18
0.30
5.00 BSC
3.20
3.40
5.00 BSC
3.20
3.40
0.50 BSC
0.35
0.45
−−−
0.15
GENERIC
MARKING DIAGRAM*
1
D2
XXXXXXXX
XXXXXXXX
AWLYYWWG
G
17
8
E2
1
32
MOLD CMPD
DETAIL B
SEATING
PLANE
C
SIDE VIEW
NOTE 4
DIM
A
A1
A3
b
D
D2
E
E2
e
L
L1
ÉÉ
ÉÉ
ÇÇ
TOP VIEW
DETAIL B
0.10 C
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
B
25
e
e/2
32X
b
0.10
M
C A B
0.05
M
C
BOTTOM VIEW
XXXXX = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
NOTE 3
RECOMMENDED
SOLDERING FOOTPRINT*
5.30
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
32X
0.63
3.55
3.55 5.30
PACKAGE
OUTLINE
0.50
PITCH
32X
0.30
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON23299F
QFN32 5x5 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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