NCP1578MNR2G

NCP1578 Synchronous Step-Down Controller with 50 mA Linear Regulator The NCP1578 is a voltage mode synchronous step-down controller for high performance systems intended to be used in battery-powered systems. The NCP1578 includes a high efficiency PWM controller with adjustable output, and a 5 V/50 mA linear regulator. A pin is provided to enable or disable forced PWM mode of operation. An internal power good voltage monitor tracks the SMPS output. NCP1578 also features soft-start sequence, UVLO for linear regulator and switcher, overvoltage protection, overcurrent protection, and thermal shutdown. The IC is packaged in QFN20. http://onsemi.com QFN20 MN SUFFIX CASE 485E Features •Fixed 5.0 V/50 mA Internal Linear Regulator •Adjustable PWM Output Voltage •1.5% Accuracy 0.8 V Reference •4.5 V to 24 V Battery/Adaptor Voltage Range •Selectable Force PWM Mode •Lossless, Programmable High Side MOSFET's RDS(ON) Current Sensing •Soft-start and Power-Up Sequencing •Overvoltage Protection, Undervoltage Protection •Programmable Delay Power Good Output •Thermal Shutdown •Housed in QFN20 •This is a Pb-Free Device MARKING DIAGRAM 20 1 N1578 ALYWG G N1578 = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) VBST TG SWN VCCP BG PIN CONNECTIONS Typical Applications •Network HUB, Switchers and Routers •3-Cell and 4-Cell Li-ion Battery-Powered Devices •Personal Computer Peripherals •Microprocessors Power Supply •Embedded Controller •DSP and Core Processor •Supply for LCD Display PGND PGDLY PGOOD SS COMP LDO5 VBAT AGND NC FB FPWM EN_LDO OCSET FOFF EN_SW ORDERING INFORMATION Device Package Shipping NCP1578MNR2G QFN20 (Pb-Free) 4000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2007 December, 2007 - Rev. 0 1 Publication Order Number: NCP1578/D NCP1578 DETAILED BLOCK DIAGRAM AGND THERMAL SHUTDOWN AGND VREF - 35% + UVP - OC FAULT INREGOUT FB VREF + 15% FB VREF - 15% + - OVP VREF TSD OCSET CONTROL LOGIC VBST + - PGth TG SWN SMPS PWM CONTROLLER VCCP EN_LDO BG PGOOD PROGRAMMABLE DELAY PG_DLY PGND OSC COMP FB AGND ADAPTIVE RAMP VREF FOFF REFERENCE FPWM VCC VBAT SS 5V LDO VCC SOFT START CONTROL UVLO CONTROL EN_SW Figure 1. Detailed Block Diagram http://onsemi.com 2 LDO5 NCP1578 TYPICAL APPLICATION CIRCUITS VIN (6 ~ 24 V) FPWM FPWM VOUT_GND PU BG VCCP SWN TG VBST VOUT PGND 1 EN_LDO PGDLY OCSET PGOOD FOFF PGOOD SS COMP EN_SW NC FB AGND LDO5 VBAT EN_SW Figure 2. Single Supply VBAT Configuration Ext +5V VIN (4.5 ~ 24 V) FPWM FPWM VOUT_GND PGND 1 EN_LDO PGDLY OCSET PGOOD FOFF SS COMP NC FB AGND LDO5 EN_SW VBAT EN_SW PU BG VCCP SWN TG VBST VOUT Figure 3. External 5 V and VIN Configuration http://onsemi.com 3 PGOOD NCP1578 PIN FUNCTION DESCRIPTION Pin No. Symbol 1 FPWM FPWM or Power Saving Control. Logic high enables force PWM. Logic low enables power saving operation. Description 2 EN_LDO LDO enable input. The 5 V LDO is enabled if EN_LDO is high and disabled if it is low. This pin can sustain voltage as high as VBAT. 3 OCSET Input pin for over current threshold setting for high side gate driver. Also it is for the internal ramp gen‐ erator to implement the voltage feed forward rejection to the input voltage variation 4 FOFF Fault OFF. If it pulls to high, it disables the features of OCP, UVLO and OVP. Normally it should be tied to ground. This pin is internally pulled down. 5 EN_SW 6 LDO5 5.0 V linear regulator output. 7 VBAT Battery/adaptor voltage input. 8 AGND Analog ground. 9 NC Not connected 10 FB Feedback input from controller's output voltage. 11 COMP PWM controller's enable input. The switching controller is enabled if EN_SW is high and disabled if EN is low. Error amplifier output pin. 12 SS 13 PGOOD Soft-start (for switcher) capacitor connection to ground. Power good signal open drain output. High impedance (open drain) if power is good (in regulation). Low impedance if power is not good. 14 PGDLY Power good delay capacitor connection to ground. 15 PGND Power ground. 16 BG 17 VCCP Power Input voltage pin. 18 SWN Inductor driven node of the SMPS, the return for high-side gate driver, and also serve as the lower supply rail of the high-side gate driver of the SMPS. 19 TG 20 VBST Positive supply of high-side gate driver of the SMPS. Connect boost capacitor between this pin and switching node SWN of the SMPS. 21 THPAD Copper pad on bottom of IC used for heatsinking. This pin should be connected to the ground plane under the IC. Gate driver output for low-side N-Channel power FET. Gate driver output for high-side N-Channel power FET. http://onsemi.com 4 NCP1578 ABSOLUTE MAXIMUM RATINGS Rating Power Supply Voltage to AGND (VCC internally connects to LDO5) High-side Gate Drive Supply: BST to SWN High-side FET Gate Drive Voltage: TG to SWN Input / Output Pins (except EN_LDO and OCSET) to AGND VBAT Input to AGND Symbol Value Unit VLDO5 -0.3, 6.0 V VBST-VSWN, VTG-VSWN -0.3, 6.0 V VIO -0.3, 6.0 V VVBAT -0.3, 27 V VEN_LDO VOCSET -0.3, 27 V Switch Node SWN VSWN -4 (< 100 ns), -0.3 (dc), 32 V PGND VGND -0.3, 0.3 V Thermal Characteristics QFN20 Plastic Package Thermal Resistance Junction-to-Ambient RθJA 47 _C/W Operating Junction Temperature Range TJ -40 to +150 _C Operating Ambient Temperature Range TA -40 to +85 _C Storage Temperature Range Tstg -55 to +150 _C Moisture Sensitivity Level MSL 1 - EN_LDO Input to AGND OCSET Input to AGND Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device is ESD sensitive. Use standard ESD precautions when handling This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) ≤ 2.0 kV per JEDEC standard: JESD22–A114 for all pins. Machine Model (MM) ≤ 200 V per JEDEC standard: JESD22–A115 for all pins. 2. Latch–up Current Maximum Rating: ≤ 150 mA per JEDEC standard: JESD78. http://onsemi.com 5 NCP1578 ELECTRICAL CHARACTERISTICS (VBAT = 12 V, LDO5 = VCCP = 5 V, TA = -40 to 85°C, for min/max values unless otherwise noted. Typical values are at TA = 25_C.) Symbol Test Conditions Min Typ Max Unit Input Voltage VBAT Single Supply Configuration, See Figure 2 Ext +5 V and VIN Configuration, See Figure 3 6.0 4.5 - 24 V VBAT Operating Supply Current IBAT LDO5 & SMPS are Enabled, See Figure 2 TG and BG are 3 nF Capacitor Load VBAT = 12 V - 2 3 VBAT = LDO5 See Figure 3 TG and BG are 3 nF Capacitor Load VBAT = 5 V - - 3 mA VBAT = 6 V to 24 V, EN_LDO = 0 V, EN_SW = 0 V - 10 30 mA Falling Edge - 4.1 - V - 330 - mV VBAT = LDO5 for 5 V Configuration See Figure 3 4.5 5.0 5.5 V VBAT = 6 V to 24 V, EN_LDO > 1.4 V, ILDO5 = 0 to 50 mA 4.85 5.0 5.15 V 50 - - mA 0.792 0.788 0.8 0.8 0.808 0.812 V Characteristic SUPPLY SECTION VBAT Shutdown Current IBATSD mA UNDERVOLTAGE MONITOR LDO5 UVLO Lower Threshold LDO5 Undervoltage Lockout Hysteresis VLDO5UVVLDO5UVHYS LINEAR REGULATOR LDO5 Input Voltage Range LDO5 Output Voltage LDO5 Maximum Output Current LDO5_IN LDO5 ILDO5_MAX VBAT = 6 V to 24 V, EN_LDO > 1.4 V SMPS CONTROLLERS FB Feedback Voltage, Control Loop in Regulation Operating Frequency Ramp Amplitude Ramp Amplitude to VIN Ratio VFB TA = 25°C TA = -40 to 85°C FSW VRAMP DVRAMP/DVIN 270 300 330 kHz VOCSET = 12 V (Note 3) - 1.02 - V VOCSET = 4.5 V to 24 V (Note 3) - 83 - mV/V - - 0 % Minimum Duty Cycle Dmin Maximum Duty Cycle Dmax VOCSET = 4.5 V to 24 V 90 - - % Voltage Error Amplifier DC Gain Gain (Note 3) - 70 - dB Error Amplifier Unity Gain Bandwidth Ft COMP to GND = 100 pF, 1.0 W in Series (Note 3) - 2 - MHz Voltage Error Amplifier Slew Rate SR (Note 3) - 3.0 - V/ìs OCSET Pin Current Sink IOC OCSET = 4.0 V 34 40 50 mA OCSET Pin Current Sink Temperature Coefficient TCIOC TG Gate Driver Pull-High Resistance RH_TG VBST - VSWN = 5 V, VTG - VSWN = 4 V - 1.5 4.0 W TG Gate Driver Pull-Low Resistance RL_TG VBST - VSWN = 5 V, VTG - VSWN = 1 V - 1.5 4.0 W BG Gate Driver Pull-High Resistance RH_BG VCCP = 5 V, VBG = 4 V - 1.5 4.0 W BG Gate Driver Pull-Low Resistance RL_BG VCCP = 5 V, VBG = 1 V - 0.9 3.0 W EN_SW = 5.0 V; Vss = 0 V 2.8 4.0 5.2 mA EN_SW = 5.0 V, VPG_DLY = 0 V 1.4 2.0 2.6 mA - 1.25 - V Soft-start Current PGDLY Delay Current PGDLY Threshold Iss IPG_DLY 3200 VthPG_DLY 3. Guaranteed by design, not tested in production. http://onsemi.com 6 ppm/°C NCP1578 ELECTRICAL CHARACTERISTICS (VBAT = 12 V, LDO5 = VCCP = 5 V, TA = -40 to 85°C, for min/max values unless otherwise noted. Typical values are at TA = 25_C.) Characteristic Symbol Test Conditions Min Typ Max Unit 110 - 120 % 65 - % -20 - -10 % - 70 - W - - 1.0 mA FAULT DETECTION Overvoltage Trip Threshold OVPth With Respect to FB Voltage Undervoltage Trip Threshold UVPth With Respect to FB Voltage PGOOD Lower Threshold VPG- With Respect to FB Voltage PGOOD Pin ON Resistance PGOOD_R PGOOD Pin Leakage Current PGOOD_LK I_PGOOD = 5.0 mA Thermal Shutdown Trip Point TSD (Note 3) - 150 - °C Thermal Shutdown Hysteresis TSDHYS (Note 3) - 25 - °C EN_LDO Threshold High VENLDO_H LDO ON 1.4 - - V EN_LDO Threshold Low VENLDO_L LDO OFF - - 0.5 V EN_LDO Input Current IINLDO_EN1 EN_LDO = 5.0 V - - 1 mA IINLDO_EN2 EN_LDO = 24.0 V - - 10 mA V LOGIC INPUT LEAKAGE EN_SW Threshold High VENSW_H SMPS ON 1.4 - - EN_SW Threshold Low VENSW_L SMPS OFF - - 0.6 V EN_SW Input Current IINSW_EN EN_SW = 5.0 V - - 1.0 mA FPWM Threshold High FPWM_H Set as Force PWM Mode 1.4 - - V FPWM Threshold Low FPWM_L Set as Power Saving Mode - - 0.6 V FPWM Input Current IIN_FPWM FPWM = 5.0 V - - 1.0 mA FOFF Threshold High FOFF_H Disable OCP, UVLO & OVP 1.4 - - V FOFF Threshold Low FOFF_L OCP, UVLO & OVP are in function - - 0.6 V FOFF Input Current IIN_FOFF FOFF = 5.0 V (Internal Pull Down by 1 MW) - 5.0 - mA 3. Guaranteed by design, not tested in production. http://onsemi.com 7 NCP1578 TYPICAL OPERATING CHARACTERISTICS 5.06 Vin = 24 V LDO5 OUTPUT VOLTAGE (V) VBAT, SHUTDOWN CURRENT (mA) 20 15 10 5 5.04 5.02 5.00 Vin = 6 V, 0 mA Vin = 6 V, 50 mA 4.98 -15 10 35 60 TA, AMBIENT TEMPERATURE (°C) 4.96 -40 85 Figure 4. VBAT Shutdown Current vs. Ambient Temperature -15 10 35 60 TA, AMBIENT TEMPERATURE (°C) 85 Figure 5. LDO5 Output Voltage vs. Ambient Temperature 320 SWITCHING FREQUENCY (kHz) 0.90 VFB, FEEDBACK VOLTAGE (V) Vin = 24 V, 50 mA Vin = 6.0 V 0 -40 0.85 0.80 0.75 0.70 -40 -15 10 35 60 310 300 290 280 -40 85 -15 10 35 60 TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C) Figure 6. VFB Feed Back Voltage vs. Ambient Temperature Figure 7. Switching Frequency vs. Ambient Temperature 85 4.5 ISS, SOFT-START CURRENT (mA) 44 43.5 IOC CURRENT (mA) Vin = 24 V, 0 mA 43 42.5 42 41.5 41 -40 -15 10 35 60 4.4 4.3 4.2 4.1 4.0 -40 85 -15 10 35 60 TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C) Figure 8. IOC Current vs Ambient Temperature Figure 9. Soft-Start Current vs. Ambient Temperature http://onsemi.com 8 85 NCP1578 TYPICAL OPERATING CHARACTERISTICS 1.25 PGOOD, DELAY THRESHOLD (V) PGOOD, DELAY CURRENT (mA) 2.5 2.3 2.1 1.9 1.7 1.5 -40 -15 10 35 60 1.22 1.21 -15 10 35 60 85 TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C) Figure 10. PGOOD Delay Current vs. Ambient Temperature Figure 11. PGOOD Delay Threshold vs. Ambient Temperature 66 UNDERVOLTAGE THRESHOLD (%) OVERCURRENT THRESHOLD (%) 1.23 1.20 -40 85 116 115.8 115.6 115.4 115.2 115 -40 -15 10 35 60 65.5 65 64.5 64 -40 85 -15 10 35 60 TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C) Figure 12. Overcurrent Threshold vs. Ambient Temperature Figure 13. Undervoltage Threshold vs. Ambient Temperature EN_LDO LEAKAGE @ 24 V (mA) -14.8 -15 -15.3 -15.5 -40 85 5.0 -14.5 PGOOD LOWER THRESHOLD (%) 1.24 -15 10 35 60 85 4.5 4.0 3.5 3.0 -40 -15 10 35 60 TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C) Figure 14. PGOOD Lower Threshold vs. Ambient Temperature Figure 15. EN_LDO Leakage Current vs. Ambient Temperature http://onsemi.com 9 85 NCP1578 TYPICAL OPERATING CHARACTERISTICS 3.350 Vo, OUTPUT VOLTAGE (V) Vo, OUTPUT VOLTAGE (V) 3.350 3.325 Io = 0 A 3.300 Io = 5 A 3.275 3.250 5 10 15 20 3.325 Vo = 24 V 3.300 Vo = 6 V 3.275 3.250 0.5 25 1.5 2.5 3.5 Io, OUTPUT CURRENT (A) Figure 16. Vo Output Voltage vs. Input Voltage Figure 17. Vo Output Voltage vs. Output Current 100 100 Vin = 6 V Vin = 6 V 90 90 Vin = 12 V EFFICIENCY (%) EFFICIENCY (%) 4.5 Vin, INPUT VOLTAGE (V) Vin = 24 V 80 70 Vo = 3.3 V FSW = 300 kHz TA = 25°C 60 50 0.1 Vin = 12 V Vin = 24 V 80 VBAT = +5.0 V Vo = 3.3 V FSW = 300 kHz TA = 25°C 70 60 With Power Saving Without Power Saving 1 10 50 0.1 With Power Saving Without Power Saving 1 Io, OUTPUT CURRENT (A) Io, OUTPUT CURRENT (A) Figure 18. Vo Efficiency vs. Output Current (Single Supply) Figure 19. Vo Efficiency vs. Output Current (Separate Supply) Figure 20. Power Up Sequence Figure 21. Power Down Sequence http://onsemi.com 10 10 NCP1578 TYPICAL OPERATING CHARACTERISTICS Figure 22. Switcher Operation - CCM Mode Figure 23. Switcher Operation - DCM Mode Figure 24. Switcher Operation - Pulse SkippingMode (PSM) Figure 25. Switcher Operation - PSM Zoom-In Figure 26. Load Transient - Load Step Up Figure 27. Load Transient - Load Release http://onsemi.com 11 NCP1578 TYPICAL OPERATING CHARACTERISTICS Figure 28. Vout OCP by Short Circuit to Ground Figure 29. Vout OCP by Steady Iout Increases Figure 30. Undervoltage Protection Figure 31. Overvoltage Protection http://onsemi.com 12 NCP1578 DETAILED OPERATING DESCRIPTION General For enhanced efficiency, an active synchronous switch is used to eliminate the conduction loss contributed by the forward voltage of a Schottky diode rectifier. Adaptive nonoverlap timing control of the complementary gate drive output signals is provided to reduce large shoot-through current that degrades efficiency. When the forced PWM is disabled, the low-side MOSFET is allowed to turn off after the detection of negative inductor current. The NCP1578 synchronous step-down power controller contains a PWM controller and a 5 V/50 mA linear regulator for wide battery/adaptor voltage range applications The NCP1578 includes power good voltage monitor, soft-start, over current protection, undervoltage protection, overvoltage protection, LDO5 UVLO and thermal shutdown. The NCP1578 allows for improved efficiency at light loads by allowing the synchronous MOSFET to turn off automatically making this device a ideal for battery operated systems. The IC is packaged in QFN20. Overcurrent Protection of SMPS Controllers An external resistor connected between the input voltage and OCSET sets the current limit for the high-side switch. An internal 40 mA current sink (IOC) at OCSET pin establishes a voltage drop across this resistor and develops a voltage at input and is compared to the voltage at SWN pin when the high-side gate drive is high after a fixed period of blanking time (X150 ns) to avoid false current limit triggering. When the voltage at SWN is lower than that at the input for 16 consecutive internal clock cycles, an over current condition occurs. Those 16 consecutive cycles will be operating as cycle by cycle condition in the way such that for each cycle, TG is OFF once the inductor current hits the preset threshold value. The SMPS output will be latched off after those 16 cycles to protect against a short-to-ground condition on SWN or OUT. The IC will be reset once LDO5 or EN_SW is cycled. Control Logic The LDO5 is enabled when EN_LDO is high. The PWM controller is enabled when EN_SW is high. The internal Vref is activated whenever the output of LDO5 rises above the UVLO threshold of 65% of VFB volts, power-on reset occurs which resets all the protection faults. The device's control logic is powered by LDO5 internally. Once Vref reaches its regulation voltage, an internal signal will wake up the supply undervoltage monitor which will assert a “GOOD” condition if LDO5 voltage is within certain preset levels. Linear Regulator The 5 V linear regulator can supply total 50 mA current for both internal and external loads. It can be enabled or disabled independently by the control pin EN_LDO. When EN_LDO = 1, the UVLO voltage is set as 4.5 V with hystersis 330 mV typical. It is recommended to bypass LDO5 output with 1 mF (min) ceramic capacitors. Output Voltages Sensing The SMPS output voltage is sensed across the FB and AGND pins. FB should be connected through a feedback resistor divider to the output voltage point of regulation. The AGND should be connected directly through a sense trace to the remote ground sense point which is usually the ground of local bypass capacitor for load. Switching Controller The controller directly drives two external N-Channel power FETs. An external resistor divider sets the nominal output voltage. The control architecture is voltage mode fixed frequency with input voltage feedforward PWM. The part is compensated externally. The switching frequency is fixed at 300 kHz ± 10%. The SMPS output voltage is divided down via resistor network and fed back to the inverting input of an internal error amplifier through FB pin to close the loop at Vout. This amplifier compares the feedback voltage with an internal Vref to generate an error signal for the PWM comparator. This error signal is further compared with a fixed frequency RAMP waveform derived from the internal oscillator to generate a pulse-width-modulated signal. This PWM signal drives the external N-Channel Power FETs via the TG and BG pins. External inductor and capacitor filter the output waveform. The SMPS output voltage ramps up at a pre-defined soft-start rate when the EN_SW pin goes HIGH from LOW after Vref is ready. Input voltage feedforward is implemented to the RAMP signal generation to reject the effect of wide input voltage variation. With input voltage feedforward, the amplitude of the RAMP is proportional to the input voltage. Supply Voltage Under-Voltage Monitor The IC continuously monitors LDO5 output pin. The IC will shutdown if the voltage is below 4.5 V. Thermal Shutdown The IC will shutdown if the die temperature exceeds 150_C. The IC restarts operation only after the junction temperature drops below 125_C. Power Good The PGOOD is an open-drain output of a comparator which continuously monitors SMPS output voltage. The Power Good time delay can be programmable by connecting an external capacitor. The PGOOD is true (high impedance) when the FB pin is within $15% of the preset nominal regulation voltage. The PGOOD is false (pulled low) when FB rises above 15% or falls below 15% the nominal regulation point. PGOOD pin also pulls low when protection fault occurs (OVP, UVP, OTP, and UVLO), or http://onsemi.com 13 NCP1578 Cycling EN_SW or LDO5 can reset the undervoltage fault latch and restart the controller. SMPS is disabled by EN_SW. Note that the PGOOD pin is valid providing LDO5 is high enough to maintain the internal logic state. Soft-Start The switcher VOUT soft-start feature is incorporated in the device to prevent surge current from power supply and output voltage overshot during power up. When EN_SW, LDO5 rises above their respective upper threshold voltages, the external soft start capacitor Css is charged by a constant current source Iss. When the soft-start voltage reaches the Vref voltage, the soft start process is finished. The soft-start time Tss can be programmed by the soft-start capacitor according to the following equation: Tss [ (0.8 x Css) / Iss. Overvoltage Protection When SMPS output voltage is above 115% (typ) the preset nominal regulation voltage for 16 consecutive internal clock cycles, the SMPS output will be latch off and it can be restarted by toggling EN_SW or LDO5. Undervoltage Protection When SMPS output falls below 65% (typ) of the nominal regulation voltage for 16 consecutive internal clock cycles, the undervoltage fault is set, the SMPS is latched off. OPERATION TABLE 1 (Single Supply VBAT Configuration) Operating Condition Input Condition Output Condition FPWM EN_LDO EN_SW SMPS LDO5 PGOOD X Low X Off Off H-Z X High Low Off On Low High High High On (FPWM) On H-Z Low High High On (DCM or Pulse Skipping) On H-Z OPERATION TABLE 2 (External +5 V and VIN Configuration (Note 4)) Input Condition FPWM EN_LDO (Note 5) Operating Condition Output Condition SMPS PGOOD EN_SW X Low Low Off Low High Low High On (FPWM) H-Z Low Low High On (DCM or pulse skipping) H-Z 4. External +5 V is connecting to VBAT and LDO5 pin. 5. For this configuration, it is recommended to pull EN_LDO to GND at any time. http://onsemi.com 14 NCP1578 TIMING DIAGRAMS VBAT EN_LDO LDO5 EN_SW Vout Drop Rate Depends on Output Loading SMPS VOUT PGDLY PGOOD VBAT > 6 V for LDO5 Ready LDO5 Soft-Start PGOOD is Undermined SMPS Soft-Start SMPS In PGOOD Delay PGOOD Goes Low EN_SW Should Be Regulation and Goes High when LDO5 Goes UVLO when LDO5 is too Low Ready when LDO5 is Threshold to Maintain Logic Level High Enough to LDO5 in Regulation Maintain Logic Level Figure 32. Single VBAT Configuration (SMPS Disabled by EN_LDO) VBAT EN_LDO LDO5 EN_SW Vout Drop Rate Depends on Output Loading SMPS VOUT PGDLY PGOOD VBAT > 6 V for LDO5 Ready SMPS Soft-Start SMPS In LDO5 Soft-Start EN_SW Should Be Regulation Ready when LDO5 is LDO5 in Regulation High Enough to Maintain Logic Level PGOOD Delay and Goes High PGOOD Goes Low whenever EN_SW Goes Low Figure 33. Single VBAT Configuration (SMPS Disabled by EN_SW) http://onsemi.com 15 NCP1578 TIMING DIAGRAMS (Continuous) VBAT VIN LDO5 EN_SW Vout Drop Rate Depends on Output Loading SMPS VOUT PGDLY PGOOD LDO5 > 4.5 V to Enable IC EN_SW Goes High SMPS In Regulation PGOOD Delay and Goes High PGOOD Goes Low Whenever EN_SW Goes Low Figure 34. External 5 V (Connect to VBAT and LDO5) and Vin Configuration http://onsemi.com 16 NCP1578 GENERAL APPLICATION INFORMATION Introduction of the error amplifier is used to provide pulse-width modulated (PWM) wave. Figure 35 depicts the general control blocks of voltage mode control loop for a synchronous-rectified buck converter. The voltage output Vout is regulated to a reference level which is basically governed by the following formula ǒ Ǔ R1 R2 V out + 1 ) V FB Loop Compensation Since NCP1578 is a voltage mode PWM controller with LC output filter, type III compensation network is recommended to provide the good closed loop bandwidth and phase boot with stability under any circumstances. The purpose of compensation is to obtain a stable close loop system with the highest possible bandwidth. In another word, we need to obtain a ”fast and stable” system. (eq. 1) In order to provide proper regulation, the error amplifier is compared with the internal reference voltage and the output VIN NCP1578 Modulator CIN Q1 TG VOUT SWN PWM Logic Q2 Gate Driver & L DCR BG Ramp Generator ESR COUT Output Filter PGND COMP Vref C2 Error Amp R3 A C3 C1 R4 R1 Compensation Network FB R2 Figure 35. Buck Converter with Modulator, Output Filter and Compensation Network Equations Involved in Compensation Network F P2 + The following equations are provided as general guidelines for defining the positions of poles and zeros of the compensation network. 1 2p ǸL F ESR + 2p  (LCDoublePole) C out 1 ESR  (ESRZero) C out F P1 + F Z2 + 2p 1 R3  (1stZero) C2 1 ǒC1 C2 2p R3 2p 1 (R1 ) R4) C1)C2  (1stPole) Ǔ  (2ndPole) C3 (eq. 7) 1. Select a value of R1 between 2 kW and 5 kW 2. Target for close loop bandwidth should be less than 50% of switching frequency 3. Place 1st zero at 50% of filter double pole. 4. Place 1st pole at ESR zero 5. Place 2nd zero at filter double pole 6. Place 2nd pole at half the switching frequency. Figure 36 shows an asymptotic plot of the converter gain against frequency. It gives the general trend of how system and its individual components behave. Actually, the Modulator and Filter Gain has a high peak due to the high Q factor of the output filter. The Open Loop Error Amplifier Gain bounds the Compensation Gain. The Converter Gain is constructed on the graph by summing up the Modulator and Filter Gain (in dB) and the Compensation Gain (in dB). The Compensation Gain uses the external impedance network (R1, R4, C3, C1, C2, R3 at Figure 35) to provide a (eq. 2) (eq. 3) Compensation Network Break Frequency F Z1 + 1 R4 Guidelines for selecting compensation component Output Filter Break Frequency F LC + 2p (eq. 4) (eq. 5)  (2ndZero) (eq. 6) C3 http://onsemi.com 17 NCP1578 stable and high bandwidth overall loop. Worst case component variation should be considered when selecting the components of impedance network such that the control loop phase margin should be greater than 45°. Open Loop Error Amp Gain FZ1 = 0.5 FLC FZ2 = FLC FP2 = 0.5 FS GAIN (dB) FP1 = FESR Converter Gain 0dB FLC Compensation Gain FESR Modulator & Filter Gain FREQUENCY Figure 36. Bode Plot of the Converter Gain Input Capacitor Selection capacitors should be used for switching regulator applications. For steady state ripple, both ESR and capacitance of the output capacitor contribute output ripple voltage. Normally, ESR is the dominant factor for output ripple voltage. The output ripple voltage DVo can be estimated by the following equation: It is used to minimize the input voltage ripple from the power supply source. The input capacitors should be placed as close as possible to the drain of the high-side MOSFET and source of the low-side MOSFET. The PCB trace style should be in form of short and wide ones. The voltage rating and the RMS current rating are the important parameters for the bulk input capacitor. In typical application, the bulk capacitor should be selected such that the voltage and current ratings must above the maximum input voltage and largest RMS current required by system. As a safety guideline, the capacitor voltage rating should be at least 1.5 times greater than the maximum input voltage. And the RMS current rating requirement is approximately half of the DC load current. The required input capacitor RMS ripple current rating may be estimated by the following equation:I Cin(RMS) w I out Ǹ V out V in(min) * ǒ V out Ǔ DV o + DI L ESR ) DI L 8 C out FS (eq. 9) and DI L + (V in * V o) L FS Vo (eq. 10) V in DVo = DIL X ESR if Cout is large enough. Where: DIL = Inductor ripple current ESR = Effective Series Resistance of the output capacitor L = Inductance Cout = Output capacitance FS = Switching frequency Vin = Input Voltage Vo = Regulated output voltage From the above equations, it can be seen that the output ripple voltage can be reduced by either using the inductor with larger inductance or the output capacitor with smaller ESR value. In general rule of thumb, the inductor ripple current is typically 30% of the maximum load current and the ripple voltage is typically 2% of the output voltage. The output capacitor also plays an important role in response of load step up or release transients. The voltage 2 (eq. 8) V in(min) Ceramic capacitor is the good choice of the input capacitor for notebook application due to its low ESR and good ripple current rating and high voltage rating. Aluminum electrolytic capacitors are also good choice. They are relatively low cost but they should be used in parallel connection to lower the ESR which is intrinsically high compared with ceramic capacitors. Output Capacitor Selection The output capacitor's ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. So, only specialized low-ESR http://onsemi.com 18 NCP1578 undershoot DV- due to load step up DI can be estimated by the following equation: ȡI * ȣ ȧF ȧ Ȣ Ȥ It is because the switching on time of lower side MOSFET is longer than that of high side MOSFET especially at the high Vin and low Vo case. For practical application, high side MOSFET and low side MOSFET with RDSON about 7.0 mW and 5.0 mW respectively can achieve good efficiency. In order to have better immunity to low side MOSFET false switching on due to high dV/dt switching slew rate of the high side MOSFET, the low side MOSFET should be selected such that the ratio QGD/QGS should be low enough. Vo DV * + DI ESR ) V DI C out in (eq. 11) S and the voltage overshoot DV+ due to load release can be estimated by the following equation: Ǹ L DV ) + ǒI DI Ǔ 2 L o) 2 ) C out C out V 2o Overcurrent Protection Component Selection (eq. 12) * V OUT The overcurrent protection will trip when a peak inductor current hit the ILIM which is determined by the equation:- Where: IO = Load current step Other parameters for selection of output capacitor are the voltage rating and ripple current rating. In general, the voltage rating should be at least 1.25 times the output voltage and the RMS ripple current rating should be greater then the inductor ripple current. IsubsLIM + Basically, a physical inductor can be simply modeled as two components: an ideal inductance L and an ideal resistor DCR. The value of L determines the output ripple voltage, inductor ripple current and performance of load transients. And DCR contributes the system loss. Hence, the higher the DCR, the lower the efficiency of the system will be. In general, the typical inductor ripple current is 30% of the maximum load current. So based on this criteria, by simple rearrangement of Equation 10, the required inductance can be estimated as follow:- ǒV in * V oǓ 0.3 I O(max) Vo V in I OC (eq. 14) R DS(on)_HS Where: ROC = Resistor across OCSET pin and Vin IOC = Constant current flowing into the OCSET pin RDS(on)_HS = On resistance of the high side MOSFET Since IOC is varying with device to device and high side MOSFET's RDS(on) varies with temperature, so in order to prevent from mis-triggering the over current protection in normal operating condition, ROC should be determined based on the following corner conditions:1. The minimum IOC value from the electrical table. 2. The maximum high side MOSFET's RDS(on) used at the highest junction temperature. 3. Estimate ILIM such that ILIM > Io_max + DIL/2 where Io_max = Maximum output current rating, DIL = Inductor ripple current. In addition, a decoupling capacitor Coc should be added in parallel with ROC for noise filtering purpose. Output Inductor Selection Lw R OC (eq. 13) FS PCB Layout Guidelines Where: IO(max) = Maximum load current In addition, The DC current rating of the inductor should be about 1.2 times of the peak inductor current at maximum output load current and in order to achieve the good system efficiency, DCR should be minimized. In general, inductor with about 2 mW to 3 mW per mH should be used. In some cases, larger inductor value can be selected to achieve higher efficiency as long as it still meets the required voltage overshoot at load release and inductor DC current rating. The following items should be considered when preparing PCB layout: 1. All high current traces should be kept as short and wide as possible to reduce power loss. For example the input voltage terminal to the drain of high-side MOSFET, trace from inductor to the output terminal, etc. Power handling and heat sinking capability of power traces can be improved by multiple trace routing at different layer and join them together with multiple vias. 2. Power components which include the input capacitor, MOSFETs, inductor and output capacitor must be placed close together to minimize the current loop. 3. The thermal pad of the QFN20 package should be connected to the ground planes for providing good heat dissipation. It is recommended to use PCB with 1 oz or 2 oz copper foil. The thermal pad can MOSFET Selection For selection of MOSFET, gate drive voltage (VGS), ON-Resistance (RDSON), gate input capacitance (CGS) and gate charges (QG, QGD and QGS) are the key parameters to be considered. For ON-resistance, in consideration of efficiency and power dissipation, it should be the lower the better. In general, for the buck converter, the RDSON of low side MOSFET is usually lower than that of high side MOSFET. http://onsemi.com 19 NCP1578 6. The feedback resistor divider should be placed as close as possible to FB pin. The output voltage sensing signal should be come up from the separated noise free signal trace. 7. To minimize the effect of parasitic impedance, traces between gate drivers to MOSFET's gates should be as shortest as possible. be connected to either PGND or AGND but not on the both. 4. The ground terminals of input and output capacitors, and the low-side MOSFET's source pin should be connected to PGND ground plane through (if necessary) multiple vias. 5. Noise sensitive traces such as traces of FB, COMP and OCSET should be placed in order to prevent from interference of high voltage switching signal traces like SWN, VBST, TG and BG. VBAT Cin1 10uF Cin2 0.1uF M1 NTMS7N03R2 D1 MBRM120L L1 2.2uH Dbst MBR0530T1 Cbst 0.1uF 3.3V, 5A Co2 Co1 180uF 180uF M2 Cvccp 1uF VO Co3 1uF 20 FPWM EN_SW VCCP SWN BG 16 1 15 2 14 PGND Cpgdly 18nF PGDLY U1 OCSET FOFF EN_SW 3 13 NCP1578NMR2 4 12 5 11 6 7 8 9 PGOOD SS Ccmp1 COMP 680pF Ccmp2 Rcmp 10 2.7k Rfb1 2.7nF Cfb Cvbat 100 Rldo 10 10nF Cldo 1uF Rfb3 Rfb2a 1uF 1.8k 5.6k Figure 37. Typical Application Schematic Diagram http://onsemi.com 20 PGOOD Css 82nF FB 10nF 17 NC Coc 18 AGND Roc 4.7k EN_LDO 19 VBAT Ren_ldo 100k LDO5 FPWM TG VBST NTMS7N03R2 AGND PGND NCP1578 BILL OF MATERIAL (BOM) FOR THE TYPICAL APPLICATION SCHEMATIC Item Qty Designator Part Description Vendor 1 1 U1 NCP1578 Buck Controller ON Semicondutor 2 2 M1, M2 NTMS7N03R2 MOSFET N-Ch 7A, 30V, 23mW @ 4.5V ON Semicondutor 3 1 D1 MBRM120L Schottky Diode 1A, 20V, POWERMITE ON Semicondutor 4 1 Dbst MBR0530T1 Schottky Diode 0.5A, VF=0.375V @ 0.1A, SOD-123 ON Semicondutor 5 1 L1 FDA1055-2R2M 2.2uH, 4.8mW max TOKO 6 2 Co1, Co2 SP-CAP, 180uF, 6.3V, ESR=10mW SIZE-D Panasonic 7 1 Cin1 Ceramic Capacitor 10uF/25V, 2512 8 4 Co3, Cvbat, Cldo, Cvccp Ceramic Capacitor 1uF/10V, 0805 9 2 Cin2, Cbst Ceramic Capacitor 0.1uF/25V, 0603 10 1 Cpgdly Ceramic Capacitor 18nF/50V, 0603 11 1 Css Ceramic Capacitor 82nF/50V, 0603 12 1 Ccmp1 Ceramic Capacitor 680pF/50V, 0603 13 1 Ccmp2 Ceramic Capacitor 2.7nF/50V, 0603 14 2 Cfb, Coc Ceramic Capacitor 10nF/50V, 0603 15 1 Rcmp Resistor 2.7kW, 0603 16 1 Rfb1 Resistor 100W, 0603 17 1 Rfb2a Resistor 5.6kW, 0603 18 1 Rfb3 Resistor 1.8kW, 0603 19 1 Rldo Resistor 10W, 0603 20 1 Ren_ldo Resistor 100kW, 0603 21 1 Roc Resistor 4.7kW, 0603 http://onsemi.com 21 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN20, 4x4, 0.5P CASE 485E ISSUE C DATE 13 FEB 2018 SCALE 2:1 A B D PIN ONE REFERENCE 2X 0.15 C ÉÉ ÉÉ EXPOSED COPPER ÉÉ ÉÉ ÇÇ A3 A1 E ÉÉÉ ÉÉÉ ÇÇÇ A3 MOLD COMPOUND PLATING A1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DETAIL B ALTERNATE CONSTRUCTIONS DIM A A1 A3 b D D2 E E2 e K L L1 2X 0.15 C L L TOP VIEW (A3) DETAIL B L1 A 0.10 C DETAIL A OPTIONAL CONSTRUCTIONS 0.08 C A1 SIDE VIEW C SEATING PLANE GENERIC MARKING DIAGRAM* 20 0.10 C A B D2 DETAIL A 20X 1 L 6 0.10 C A B 11 E2 20 20X e b 0.10 C A B 0.05 C NOTE 3 BOTTOM VIEW *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking. SOLDERING FOOTPRINT* 4.30 XXXXXX XXXXXX ALLYWG G XXXXXX= Specific Device Code A = Assembly Location LL = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) 1 K MILLIMETERS MIN MAX 0.80 1.00 --0.05 0.20 REF 0.20 0.30 4.00 BSC 2.60 2.90 4.00 BSC 2.60 2.90 0.50 BSC 0.20 REF 0.35 0.45 0.00 0.15 20X 0.58 2.88 1 2.88 4.30 PKG OUTLINE 20X 0.35 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON03163D QFN20, 4X4, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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