NCP5104, NCV5104
Single Input High Voltage
High and Low-Side MOSFET
or IGBT Drivers
The NCP5104 is a High Voltage Power gate Driver providing two
outputs for direct drive of 2 N−channel power MOSFETs or IGBTs
arranged in a half−bridge configuration. It uses the bootstrap
technique to insure a proper drive of the High−side power switch.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High Voltage Range: up to 600 V
dV/dt Immunity ±50 V/nsec
Gate Drive Supply Range from 10 V to 20 V
High and Low Drive Outputs
Output Source / Sink Current Capability 250 mA / 500 mA
3.3 V and 5 V Input Logic Compatible
Up to VCC Swing on Input Pins
Extended Allowable Negative Bridge Pin Voltage Swing to −10 V
for Signal Propagation
Matched Propagation Delays between Both Channels
1 Input with Internal Fixed Dead Time (520 ns)
Under VCC LockOut (UVLO) for Both Channels
Pin to Pin Compatible with Industry Standards
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• Half−Bridge Power Converters
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MARKING
DIAGRAMS
1
SOIC−8
D SUFFIX
CASE 751
8
P5104
ALYW
G
1
NCP5104
AWL
YYWWG
1
PDIP−8
P SUFFIX
CASE 626
NCP5104
A
L or WL
Y or YY
W or WW
G or G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PINOUT INFORMATION
VCC
IN
SD
GND
1
2
3
4
VBOOT
DRV_HI
BRIDGE
DRV_LO
8
7
6
5
8 Pin Package
ORDERING INFORMATION
Device
Package
Shipping†
NCP5104PG
PDIP−8
(Pb−Free)
50 Units / Rail
NCP5104DR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCV5104DR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 7
1
Publication Order Number:
NCP5104/D
NCP5104, NCV5104
Vbulk
+
C1
D4
GND
Q1
Vcc
T1
C3
U1
8
VBOOT
Vcc
2
7
IN
DRV_HI
3
6
SD
Bridge
4
5
GND DRV_LO
1
GND
NCP1395
L1
Out+
+
C4
C3
Lf
Out−
D2
C6
Q2
NCP5104
GND
D1
GND
GND
R1
D3
GND
U2
Figure 1. Typical Application Resonant Converter (LLC type)
Vbulk
+
C1
C5
D4
GND
Q1
Vcc
C3
GND
T1
1
SG3526
MC34025
TL594
NCP1561
2
3
4
U1
8
VBOOT
Vcc
7
IN
DRV_HI
6
Bridge
SD
5
GND DRV_LO
L1
C4
Out+
+
C3
Out−
D2
C6
NCP5104
GND
D1
Q2
GND
GND
R1
D3
GND
U2
Figure 2. Typical Application Half Bridge Converter
VCC
VCC
VBOOT
UV
DETECT
IN
DEAD TIME
GENERATION
PULSE
TRIGGER
S Q
R Q
LEVEL
SHIFTER
GND
UV
DETECT
DRV_HI
BRIDGE
VCC
GND
SD
DRV_LO
DELAY
GND
GND
GND
Figure 3. Detailed Block Diagram
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2
NCP5104, NCV5104
PIN DESCRIPTION
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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Pin Name
Description
VCC
Low Side and Main Power Supply
IN
Logic Input
SD
Logic Input for Shutdown
GND
Ground
DRV_LO
Low Side Gate Drive Output
VBOOT
Bootstrap Power Supply
DRV_HI
High Side Gate Drive Output
BRIDGE
Bootstrap Return or High Side Floating Supply Return
MAXIMUM RATINGS
Rating
VCC
VCC_transient
Symbol
Main power supply voltage
Main transient power supply voltage:
IVCC_max = 5 mA during 10 ms
Value
Unit
−0.3 to 20
V
23
V
VBOOT
VHV: High Voltage BOOT Pin
−1 to 620
V
VBRIDGE
VHV: High Voltage BRIDGE pin
−1 to 600
V
VBRIDGE
Allowable Negative Bridge Pin Voltage for IN_LO Signal Propagation to DRV_LO
(see characterization curves for detailed results)
−10
V
VBOOT−VBRIDGE
VHV: Floating supply voltage
−0.3 to 20
V
VDRV_HI
VHV: High side output voltage
VBRIDGE − 0.3 to
VBOOT + 0.3
V
VDRV_LO
Low side output voltage
−0.3 to VCC + 0.3
V
50
V/ns
−1.0 to VCC + 0.3
V
2
200
kV
V
dVBRIDGE/dt
VIN, VSD
Allowable output slew rate
Inputs IN & SD
ESD Capability:
− HBM model (all pins except pins 6−7−8 in 8)
− Machine model (all pins except pins 6−7−8)
Latch up capability per JEDEC JESD78
RqJA
TST
TJ_max
°C/W
Power dissipation and Thermal characteristics
PDIP−8: Thermal Resistance, Junction−to−Air
SO−8: Thermal Resistance, Junction−to−Air
100
178
Storage Temperature Range
Maximum Operating Junction Temperature
−55 to +150
°C
+150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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3
NCP5104, NCV5104
ELECTRICAL CHARACTERISTIC (VCC = Vboot = 15 V, VGND = Vbridge, −40°C < TJ < 125°C, Outputs loaded with 1 nF)
TJ −40°C to 125°C
Symbol
Min
Typ
Max
Units
Output high short circuit pulsed current VDRV = 0 V, PW v 10 ms (Note 1)
IDRVsource
−
250
−
mA
Output low short circuit pulsed current VDRV = Vcc, PW v 10 ms (Note 1)
IDRVsink
−
500
−
mA
Output resistor (Typical value @ 25°C) Source
ROH
−
30
60
W
Output resistor (Typical value @ 25°C) Sink
ROL
−
10
20
W
High level output voltage, VBIAS−VDRV_XX @ IDRV_XX = 20 mA
VDRV_H
−
0.7
1.6
V
Low level output voltage VDRV_XX @ IDRV_XX = 20 mA
VDRV_L
−
0.2
0.6
V
Turn−on propagation delay (Vbridge = 0 V) (Note 2)
tON
−
620
800
ns
Turn−off propagation delay (Vbridge = 0 V or 50 V) (Note 3)
tOFF
−
100
170
ns
Shutdown propagation delay, when Shutdown is enabled
tsd_en
−
100
170
ns
Shutdown propagation delay, when Shutdown is disabled
tsd_dis
−
620
800
ns
Output voltage rise time (from 10% to 90% @ VCC = 15 V) with 1 nF load
tr
−
85
160
ns
Output voltage fall time (from 90% to 10% @ VCC = 15 V) with 1 nF load
tf
−
35
75
ns
Propagation delay matching between the High side and the Low side
@ 25°C (Note 4)
Dt
−
10
45
ns
Internal fixed dead time (Note 5)
DT
400
520
650
ns
Low level input voltage threshold
VIN
−
−
0.8
V
Input pull−down resistor (VIN < 0.5 V)
RIN
−
200
−
kW
High level input voltage threshold
VIN
2.3
−
−
V
Logic “1” input bias current @ VIN = 5 V @ 25°C
IIN+
−
5
25
mA
Logic “0” input bias current @ VIN = 0 V @ 25°C
IIN−
−
−
2.0
mA
Vcc_stup
8.0
8.9
9.8
V
Vcc_shtdwn
7.3
8.2
9.0
V
Vcc_hyst
0.3
0.7
−
V
Vboot_stup
8.0
8.9
9.8
V
Vboot UV Shut−down voltage threshold
Vboot_shtdwn
7.3
8.2
9.0
V
Hysteresis on Vboot
Vboot_shtdwn
0.3
0.7
−
V
IHV_LEAK
−
5
40
mA
Consumption in active mode (Vcc = Vboot, fsw = 100 kHz and 1 nF load on
both driver outputs)
ICC1
−
4
5
mA
Consumption in inhibition mode (Vcc = Vboot)
ICC2
−
250
400
mA
Vcc current consumption in inhibition mode
ICC3
−
200
−
mA
Vboot current consumption in inhibition mode
ICC4
−
50
−
mA
Rating
OUTPUT SECTION
DYNAMIC OUTPUT SECTION
INPUT SECTION
SUPPLY SECTION
Vcc UV Start−up voltage threshold
Vcc UV Shut−down voltage threshold
Hysteresis on Vcc
Vboot Start−up voltage threshold reference to bridge pin
(Vboot_stup = Vboot − Vbridge)
Leakage current on high voltage pins to GND
(VBOOT = VBRIDGE = DRV_HI = 600 V)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Parameter guaranteed by design.
2. TON = TOFF + DT
3. Turn−off propagation delay @ Vbridge = 600 V is guaranteed by design.
4. See characterization curve for Dt parameters variation on the full range temperature.
5. Timing diagram definition see: Figure 4, Figure 5 and Figure 6.
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4
NCP5104, NCV5104
IN
SD
DRV_HI
DRV_LO
Figure 4. Input/Output Timing Diagram
Note: DRV_HI output is in phase with the input
IN
50%
50%
tr
ton
90%
Dead time
DRV_HI
90%
10%
toff
tf
toff
10%
tf
Dead time
tr
90%
90%
ton
DRV_LO
10%
Ton = Toff + DT
Figure 5. Timing Definitions
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5
10%
NCP5104, NCV5104
IN
50%
50%
toff_HI
DeadTime1
90%
DRV_HI
10%
toff_LO
DeadTime2
90%
DRV_LO
Matching Delay1=toff_HI−toff_LO
Matching Delay 2=(toff_LO+DT1)−(toff_HI+DT2)
10%
Figure 6. Matching Propagation Delay Definition
50%
50%
SD
tsd_en
DRV_HI
tsd_dis
90%
10%
DRV_LO
Figure 7. Shutdown Waveform Definition
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6
NCP5104, NCV5104
CHARACTERIZATION CURVES
900
TON, PROPAGATION DELAY (ns)
TON, PROPAGATION DELAY (ns)
800
750
700
TON Low Side
650
600
550
TON High Side
500
450
12
14
16
VCC, VOLTAGE (V)
18
800
750
TON Low Side
700
650
600
550
TON High Side
500
450
400
−40
400
10
850
20
Figure 8. Turn ON Propagation Delay vs.
Supply Voltage (VCC = VBOOT)
20
40
60
80
TEMPERATURE (°C)
100
120
160
140
TOFF, PROPAGATION DELAY (ns)
TOFF, PROPAGATION DELAY (ns)
0
Figure 9. Turn ON Propagation Delay vs.
Temperature
160
TOFF High Side
120
100
80
TOFF Low Side
60
40
20
10
12
14
16
VCC, VOLTAGE (V)
18
140
TOFF High Side
120
TOFF Low Side
100
80
60
40
20
0
−40
0
20
Figure 10. Turn OFF Propagation Delay vs.
Supply Voltage (VCC = VBOOT)
−20
0
20
40
60
80
TEMPERATURE (°C)
100
120
Figure 11. Turn OFF Propagation Delay vs.
Temperature
160
TOFF, PROPAGATION DELAY (ns)
800
TON, PROPAGATION DELAY (ns)
−20
700
600
500
400
300
200
100
0
140
120
100
80
60
40
20
0
0
10
20
30
40
50
0
10
20
30
40
VBRIDGE VOLTAGE (V)
VBRIDGE VOLTAGE (V)
Figure 12. High Side Turn ON Propagation
Delay vs. VBRIDGE Voltage (VCC = VBOOT)
Figure 13. High Side Turn OFF Propagation
Delay vs. VBRIDGE Voltage (VCC = VBOOT)
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7
50
NCP5104, NCV5104
CHARACTERIZATION CURVES
160
160
TON, RISETIME (ns)
140
TON, RISETIME (ns)
120
100
80
tr High Side
60
40
120
100
0
10
80
60
40
12
14
16
VCC, VOLTAGE (V)
18
0
−40
20
Figure 14. Turn ON Risetime vs. Supply
Voltage (VCC = VBOOT)
−20
0
20
40
60
80
TEMPERATURE (°C)
100
120
Figure 15. Turn ON Risetime vs. Temperature
60
80
70
tf High Side
50
60
TOFF, FALLTIME (ns)
TOFF, FALLTIME (ns)
tr Low Side
20
20
50
tf Low Side
40
tf High Side
30
20
40
tf Low Side
30
20
10
10
0
−40
0
10
12
14
16
VCC, VOLTAGE (V)
18
20
Figure 16. Turn OFF Falltime vs. Supply
Voltage (VCC = VBOOT)
−20
0
20
40
60
80
TEMPERATURE (°C)
100
120
Figure 17. Turn OFF Falltime vs. Temperature
20
600
15
10
550
5
DEAD TIME (ns)
PROPAGATION DELAY MATCHING (ns)
tr High Side
140
tr Low Side
Delay Matching 1
0
−5
−10
500
450
Delay Matching 2
−15
−20
−40
−20
0
20
40
60
80
100
400
−40
120
−20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. Propagation Delay Matching
Between High Side and Low Side Driver vs.
Temperature
Figure 19. Dead Time vs. Temperature
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8
120
NCP5104, NCV5104
1.4
1.6
1.2
1.4
LOW LEVEL INPUT VOLTAGE
THRESHOLD (V)
LOW LEVEL INPUT VOLTAGE THRESHOLD (V)
CHARACTERIZATION CURVES
1.0
0.8
0.6
0.4
0.2
0
10
12
14
16
18
1.2
1.0
0.8
0.6
0.4
0.2
0
−40
20
Figure 20. Low Level Input Voltage Threshold
vs. Supply Voltage (VCC = VBOOT)
0
100
120
2.5
HIGH LEVEL INPUT VOLTAGE
THRESHOLD (V)
HIGH LEVEL INPUT VOLTAGE
THRESHOLD (V)
20
40
60
80
TEMPERATURE (°C)
Figure 21. Low Level Input Voltage Threshold
vs. Temperature
2.5
2.0
1.5
1.0
0.5
0
10
12
14
16
VCC, VOLTAGE (V)
18
2.0
1.5
1.0
0.5
0
−40
20
Figure 22. High Level Input Voltage Threshold
vs. Supply Voltage (VCC = VBOOT)
−20
0
20
40
60
80
TEMPERATURE (°C)
100
120
Figure 23. High Level Input Voltage Threshold
vs. Temperature
10
LOGIC “0” INPUT CURRENT (mA)
4.0
LOGIC “0” INPUT CURRENT (mA)
−20
VCC, VOLTAGE (V)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10
12
14
16
VCC, VOLTAGE (V)
18
8.0
6.0
4.0
2.0
0
−40 −20
20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 25. Logic “0” Input Current vs.
Temperature
Figure 24. Logic “0” Input Current vs. Supply
Voltage (VCC = VBOOT)
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9
120
NCP5104, NCV5104
CHARACTERIZATION CURVES
10
LOGIC “1” INPUT CURRENT (mA)
LOGIC “1” INPUT CURRENT (mA)
8
7
6
5
4
3
2
1
0
10
12
14
16
VCC, VOLTAGE (V)
18
8.0
6.0
4.0
2.0
0
−40
20
20
40
60
80
100
120
Figure 27. Logic “1” Input Current vs.
Temperature
1.0
LOW LEVEL OUTPUT VOLTAGE (V)
1.0
LOW LEVEL OUTPUT VOLTAGE
THRESHOLD (V)
0
TEMPERATURE (°C)
Figure 26. Logic “1” Input Current vs. Supply
Voltage (VCC = VBOOT)
0.8
0.6
0.4
0.2
0
10
12
14
16
VCC, VOLTAGE (V)
18
20
0.8
0.6
0.4
0.2
0
−40
Figure 28. Low Level Output Voltage vs.
Supply Voltage (VCC = VBOOT)
−20
0
20
40
60
80
TEMPERATURE (°C)
100
120
Figure 29. Low Level Output Voltage vs.
Temperature
1.0
HIGH LEVEL OUTPUT VOLTAGE (V)
1.6
HIGH LEVEL OUTPUT VOLTAGE
THRESHOLD (V)
−20
1.2
0.8
0.4
0
10
12
14
16
VCC, VOLTAGE (V)
18
20
0.8
0.6
0.4
0.2
0
−40
−20
0
20
40
60
80
TEMPERATURE (°C)
100
Figure 31. High Level Output Voltage vs.
Temperature
Figure 30. High Level Output Voltage vs.
Supply Voltage (VCC = VBOOT)
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10
120
NCP5104, NCV5104
CHARACTERIZATION CURVES
400
OUTPUT SOURCE CURRENT (mA)
OUTPUT SOURCE CURRENT (mA)
400
Isrc High Side
350
300
Isrc Low Side
250
200
150
100
50
300
250
200
12
14
16
VCC, VOLTAGE (V)
18
Isrc Low Side
150
100
50
0
10
Isrc High Side
350
0
−40 −20
20
40
60
80
100
120
Figure 33. Output Source Current vs.
Temperature
600
600
Isink High Side
OUTPUT SINK CURRENT (mA)
Isink High Side
500
Isink Low Side
400
300
200
100
500
10
12
14
16
18
Isink Low Side
400
300
200
100
0
0
−40 −20
20
0
VCC, VOLTAGE (V)
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 34. Output Sink Current vs. Supply
Voltage (VCC = VBOOT)
Figure 35. Output Sink Current vs.
Temperature
0.20
20
LEAKAGE CURRENT ON HIGH
VOLTAGE PINS (600 V) to GND (mA)
HIGH SIDE LEAKAGE CURRENT ON
HV PINS TO GND (mA)
20
TEMPERATURE (°C)
Figure 32. Output Source Current vs. Supply
Voltage (VCC = VBOOT)
OUTPUT SINK CURRENT (mA)
0
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
0
100
200
300
400
500
600
15
10
5.0
0
−40
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
HV PINS VOLTAGE (V)
Figure 36. Leakage Current on High Voltage
Pins (600 V) to Ground vs. VBRIDGE Voltage
(VBRIDGE = VBOOT = VDRV_HI)
Figure 37. Leakage Current on High Voltage
Pins (600 V) to Ground vs. Temperature
(VBRIDGE = VBOOT = VDRv_HI = 600 V)
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11
NCP5104, NCV5104
CHARACTERIZATION CURVES
100
VBOOT CURRENT SUPPLY (mA)
VBOOT SUPPLY CURRENT (mA)
100
80
60
40
20
0
0
4.0
8.0
12
16
80
60
40
20
0
−40
20
−20
0
60
80
100
120
Figure 39. VBOOT Supply Current vs.
Temperature
400
VCC CURRENT SUPPLY (mA)
240
VCC SUPPLY CURRENT (mA)
40
TEMPERATURE (°C)
VBOOT, VOLTAGE (V)
Figure 38. VBOOT Supply Current vs. Bootstrap
Supply Voltage (VCC = VBOOT)
200
160
120
80
40
0
4.0
8.0
12
16
350
300
250
200
150
100
50
0
−40
0
20
−20
0
VCC, VOLTAGE (V)
40
60
80
100
120
Figure 41. VCC Supply Current vs. Temperature
10
UVLO SHUTDOWN VOLTAGE (V)
9.0
9.8
9.6
9.4
9.2
VCC UVLO Startup
9.0
8.8
VBOOT UVLO Startup
8.6
8.4
8.2
8.0
−40
20
TEMPERATURE (°C)
Figure 40. VCC Supply Current vs. VCC Supply
Voltage (VCC = VBOOT)
UVLO STARTUP VOLTAGE (V)
20
−20
0
20
40
60
80
100
120
8.8
8.6
VCC UVLO Shutdown
8.4
8.2
8.0
VBOOT UVLO Shutdown
7.8
7.6
7.4
7.2
7.0
−40
TEMPERATURE (°C)
−20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 42. UVLO Startup Voltage vs.
Temperature
Figure 43. UVLO Shutdown Voltage vs.
Temperature
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12
120
NCP5104, NCV5104
CHARACTERIZATION CURVES
40
ICC+ IBOOT CURRENT SUPPLY (mA)
ICC+ IBOOT CURRENT SUPPLY (mA)
25
CLOAD = 1 nF/Q = 15 nC
20
15
10
5.0
RGATE = 0 R to 22 R
0
RGATE = 10 R
30
25
RGATE = 22 R
20
15
10
5.0
0
0
100
200
300
400
500
0
600
100
SWITCHING FREQUENCY (kHz)
Figure 44. ICC1 Consumption vs. Switching
Frequency with 15 nC Load on Each Driver @
VCC = 15 V
200
300
400
500
SWITCHING FREQUENCY (kHz)
600
Figure 45. ICC1 Consumption vs. Switching
Frequency with 33 nC Load on Each Driver @
VCC = 15 V
80
CLOAD = 3.3 nF/Q = 50 nC
ICC+ IBOOT CURRENT SUPPLY (mA)
60
RGATE = 0 R
50
RGATE = 10 R
40
RGATE = 22 R
30
20
10
0
CLOAD = 6.6 nF/Q = 100 nC
70
RGATE = 0 R
60
50
RGATE = 10 R
40
RGATE = 22 R
30
20
10
0
0
100
200
300
400
500
600
0
100
SWITCHING FREQUENCY (kHz)
Figure 46. ICC1 Consumption vs. Switching
Frequency with 50 nC Load on Each Driver @
VCC = 15 V
200
300
400
500
SWITCHING FREQUENCY (kHz)
−5
−40°C
−10
25°C
−15
125°C
−20
−25
−30
−35
0
100
200
600
Figure 47. ICC1 Consumption vs. Switching
Frequency with 100 nC Load on Each Driver @
VCC = 15 V
0
NEGATIVE PULSE VOLTAGE (V)
ICC+ IBOOT CURRENT SUPPLY (mA)
RGATE = 0 R
CLOAD = 2.2 nF/Q = 33 nC
35
300
400
500
600
NEGATIVE PULSE DURATION (ns)
Figure 48. NCP5104, Negative Voltage Safe Operating Area on the Bridge Pin
www.onsemi.com
13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
E1
1
4
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. AUXILIARY
8. VCC
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42420B
PDIP−8
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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