LDO Regulator, 150 mA,
38V, 1 mA IQ, with PG
NCV8730
The NCV8730 device is based on unique combination of features −
very low quiescent current, fast transient response and high input and
output voltage ranges. The NCV8730 is CMOS LDO regulator
designed for up to 38 V input voltage and 150 mA output current.
Quiescent current of only 1 mA makes this device ideal solution for
battery− powered, always−on systems. Several fixed output voltage
versions are available as well as the adjustable version.
The device (version B) implements power good circuit (PG) which
indicates that output voltage is in regulation. This signal could be used
for power sequencing or as a microcontroller reset.
Internal short circuit and over temperature protections saves the
device against overload conditions.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Operating Input Voltage Range: 2.7 V to 38 V
Output Voltage: 1.2 V to 24 V
Capable of Sourcing 200 mA Peak Output Current
Low Shutdown Current: 100 nA typ.
Very Low Quiescent Current: 1 mA typ.
Low Dropout: 290 mV typ. at 150 mA, 3.3 V Version
Output Voltage Accuracy ±1%
Power Good Circuit (Version B)
Stable with Small 1 mF Ceramic Capacitors
Built−in Soft Start Circuit to Suppress Inrush Current
Over−Current and Thermal Shutdown Protections
Available in Small TSOP−5 and WDFNW6 (2x2) Packages
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
Typical Applications
•
•
•
•
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MARKING DIAGRAMS
5
TSOP−5
CASE 483
SN SUFFIX
5
1
XXXAYWG
G
1
XXX = Specific Device Code
A
= Assembly Location
Y
= Year
W = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
WDFNW6 (2x2)
CASE 511DW
MTW SUFFIX
1
XX M
XX = Specific Device Code
M = Date Code
PIN ASSIGNMENTS
TSOP−5
IN
1
GND
2
EN
3
5
OUT
4
NC/ADJ/PG
CASE 483
WDFNW6 (2x2)
Body Control Modules
LED Lighting
On Board Charger
General Purpose Automotive
6 IN
OUT 1
NC/ADJ 2
GND 3
EP
5 NC/PG
4 EN
CASE511DW
(Top Views)
ORDERING INFORMATION
See detailed ordering and shipping information on page 27 of
this data sheet.
© Semiconductor Components Industries, LLC, 2019
September, 2020 − Rev. 2
1
Publication Order Number:
NCV8730/D
NCV8730
TYPICAL APPLICATION SCHEMATICS
VIN=6−38V
IN
C IN
1mF
ON
OUT
NCV8730A 5.0V
TSOP−5 / WDFN−6
EN
OFF
GND
VIN=6−38V
VOUT=5.0V
COUT
1mF
C IN
1mF
IN
C IN
1mF
NCV8730B 5.0V
TSOP−5 / WDFN−6
NC
EN
OFF
GND
VOUT=5V
OUT
NCV8730A ADJ
TSOP−5 / WDFN−6
EN
ADJ
GND
R1
2M4
PG
R PG
100k
COUT
1mF
R2
750k
Figure 2. Adjustable Output Voltage Application (No PG)
VIN=6−38V
VOUT=5.0V
C OUT
1mF
C FF
1nF
1.2V
OFF
OUT
ON
ON
NC
Figure 1. Fixed Output Voltage Application (No PG)
VIN=6−38V
IN
IN
C IN
1mF
ON
NCV8730B ADJ
Only WDFN−6
1.2V
ADJ
EN
PG
VOUT=5V
OUT
GND
PG
OFF
R1
2M4
C FF
1nF
R2
750k
COUT
1mF
R PG
100k
PG
Figure 3. Fixed Output Voltage Application with PG
Figure 4. Adjustable Output Voltage Application with PG
ǒ
V OUT + V ADJ @ 1 )
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2
Ǔ
R1
) I ADJ @ R 1
R2
NCV8730
SIMPLIFIED BLOCK DIAGRAM
IN
OUT
Current limit
UVLO Comparator
UVLO
I EN−PU = 300nA
1.95 V
V CCEN
V−REFERENCE
AND SOFT−START
V REF
1.2V
EA
RADJ1
V FB =1.2V
EN
ADJ
Enable
RADJ2
EN Comparator
GND
THERMAL
SHUTDOWN
0.9 V
PG
PG Comparator
DEGLITCH
DELAY TMR
93% of V REF
NC
Note: Blue objects are valid for ADJ version
Green objects are valid for FIX version
Brown objects are valid for B version (with PG)
Figure 5. Internal Block Diagram
PIN DESCRIPTION
Pin No. TSOP−5 Pin No. WDFN−6
Pin Name
Description
1
6
IN
Power supply input pin.
2
3
GND
Ground pin.
5
1
OUT
LDO output pin.
3
4
EN
Enable input pin (high − enabled, low − disabled). If this pin is connected to IN pin
or if it is left unconnected (pull−up resistor is not required) the device is enabled.
4 (Note 1)
2
ADJ
Adjust input pin, could be connected to the resistor divider to the OUT pin.
4 (Note 1)
5
PG
Power good output pin. Could be left unconnected or could be connected to GND
if not needed. High level for power ok, low level for fail.
4 (Note 1)
2, 5
NC
Not internally connected. This pin can be tied to the ground plane to improve
thermal dissipation.
NA
EP
EPAD
Connect the exposed pad to GND.
1. Pin function depends on device version.
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3
NCV8730
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VIN
−0.3 to 40
V
VOUT Voltage
VOUT
−0.3 to [(VIN + 0.3) or 40 V; whichever is lower]
V
EN Voltage
VEN
−0.3 to (VIN + 0.3)
V
ADJ Voltage
VFB/ADJ
−0.3 to 5.5
V
PG Voltage
VPG
−0.3 to (VIN + 0.3)
V
Output Current
IOUT
Internally limited
mA
PG Current
IPG
3
mA
TJ(MAX)
150
°C
TSTG
−55 to 150
°C
ESD Capability, Human Body Model (Note 3)
ESDHBM
2000
V
ESD Capability, Charged Device Model (Note 3)
ESDCDM
1000
V
VIN Voltage (Note 2)
Maximum Junction Temperature
Storage Temperature
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per ANSI/ESDA/JEDEC JS−001, EIA/JESD22−A114 (AEC−Q100−002)
ESD Charged Device Model tested per ANSI/ESDA/JEDEC JS−002, EIA/JESD22−C101 (AEC Q100−011D)
THERMAL CHARACTERISTICS (Note 4)
Characteristic
Symbol
WDFNW6 2x2
TSOP−5
Unit
RthJA
61
142
°C/W
Thermal Resistance, Junction−to−Case (top)
RthJCt
200
80
°C/W
Thermal Resistance, Junction−to−Case (bottom)
RthJCb
14
N/A
°C/W
Thermal Resistance, Junction−to−Board (top)
RthJBt
46
110
°C/W
Thermal Characterization Parameter, Junction−to−Case (top)
PsiJCt
3
21
°C/W
Thermal Characterization Parameter, Junction−to−Board [FEM]
PsiJB
46
113
°C/W
Thermal Resistance, Junction−to−Air
4. Measured according to JEDEC board specification (board 1S2P, Cu
of the board can be found in JESD51−7.
layer thickness 1 oz, Cu area 650 mm2,
no airflow). Detailed description
ELECTRICAL CHARACTERISTICS (VIN = VOUT−NOM + 1 V and VIN ≥ 2.7 V, VEN = 1.2 V, IOUT = 1 mA, CIN = COUT = 1.0 mF
(effective capacitance – Note 5), TJ = −40°C to 125°C, ADJ tied to OUT, unless otherwise specified) (Note 6)
Parameter
Test Conditions
Recommended Input Voltage
Output Voltage Accuracy
TJ = 25°C
Symbol
Min
Typ
Max
Unit
VIN
2.7
−
38
V
VOUT
−1
−
1
%
−1
−
2
TJ = −40°C to +125°C
ADJ Reference Voltage
ADJ version only
VADJ
−
1.2
−
V
ADJ Input Current
VADJ = 1.2 V
IADJ
−0.1
0.01
0.1
mA
Line Regulation
VIN = VOUT−NOM + 1 V to 38 V and VIN ≥ 2.7 V
DVO(DVI)
−
−
0.2
%VOUT
Load Regulation
IOUT = 0.1 mA to 150 mA
DVO(DIO)
−
−
0.4
%VOUT
Quiescent Current (version A)
VIN = VOUT−NOM + 1 V to 38 V, IOUT = 0 mA
IQ
−
1.3
2.5
mA
Quiescent Current (version B)
VIN = VOUT−NOM + 1 V to 38 V, IOUT = 0 mA
−
1.8
3.0
Ground Current
IOUT = 150 mA
IGND
−
325
450
mA
Shutdown Current (Note 10)
VEN = 0 V, IOUT = 0 mA, VIN = 38 V
ISHDN
−
0.35
1.5
mA
Output Current Limit
VOUT = VOUT−NOM − 100 mV
IOLIM
200
280
450
mA
Short Circuit Current
VOUT = 0 V
IOSC
200
280
450
mA
Dropout Voltage (Note 7)
IOUT = 150 mA
VDO
−
290
480
mV
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NCV8730
ELECTRICAL CHARACTERISTICS (VIN = VOUT−NOM + 1 V and VIN ≥ 2.7 V, VEN = 1.2 V, IOUT = 1 mA, CIN = COUT = 1.0 mF
(effective capacitance – Note 5), TJ = −40°C to 125°C, ADJ tied to OUT, unless otherwise specified) (Note 6) (continued)
Parameter
Power Supply Ripple Rejection
Test Conditions
VIN = VOUT−NOM + 2 V
IOUT = 10 mA
Symbol
Min
Typ
Max
Unit
PSRR
−
80
−
dB
10 kHz
−
70
−
100 kHz
−
42
−
1 MHz
−
48
−
VN
−
240
−
mVRMS
10 Hz
Output Noise
f = 10 Hz to 100 kHz
VOUT−NOM = 5 V
EN Threshold
VEN rising
VEN−TH
0.7
0.9
1.05
V
EN Hysteresis
VEN falling
VEN−HY
0.01
0.1
0.2
V
EN Internal Pull−up Current
VEN = 1 V, VIN = 5.5 V
IEN−PU
0.01
0.3
1.0
mA
EN Input Leakage Current
VEN = 30 V, VIN = 30 V
IEN−LK
−1.0
0.05
1.0
mA
Start−up time (Note 8)
VOUT−NOM ≤ 3.3 V
tSTART
100
250
500
ms
300
600
1000
VOUT−NOM > 3.3 V
Internal UVLO Threshold
Ramp VIN up until output is turned on
VIUL−TH
1.6
1.95
2.6
V
Internal UVLO Hysteresis
Ramp VIN down until output is turned off
VIUL−HY
0.05
0.2
0.3
V
PG Threshold (Note 9)
VOUT falling
VPG−TH
90
93
96
%
PG Hysteresis (Note 9)
VOUT rising
VPG−HY
0.1
2.5
4.0
%
PG Deglitch Time (Note 9)
tPG−DG
75
160
270
ms
PG Delay Time (Note 9)
tPG−DLY
120
320
600
ms
PG Output Low Level Voltage (Note 9) IPG = 1 mA
VPG−OL
−
0.2
0.4
V
PG Output Leakage Current (Note 9)
VPG = 30 V
IPG−LK
−
0.01
1.0
mA
Thermal Shutdown Temperature
Temperature rising from TJ = +25°C
TSD
−
165
−
°C
Thermal Shutdown Hysteresis
Temperature falling from TSD
TSDH
−
20
−
°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Effective capacitance, including the effect of DC bias, tolerance and temperature. See the Application Information section for more
information.
6. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at TA = 25°C.
Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.
7. Dropout measured when the output voltage falls 100 mV below the nominal output voltage. Limits are valid for all voltage versions.
8. Startup time is the time from EN assertion to point when output voltage is equal to 95% of VOUT−NOM.
9. Applicable only to version B (device option with power good output). PG threshold and PG hysteresis are expressed in percentage of nominal
output voltage.
10. Shutdown current includes EN Internal Pull−up Current.
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NCV8730
TYPICAL CHARACTERISTICS
VIN = VOUT−NOM + 1 V and VIN ≥ 2.7 V, VEN = 1.2 V, IOUT = 1 mA, COUT = 1.0 mF, ADJ tied to OUT, TJ = 25°C, unless otherwise specified
VIN = (VOUT-NOM+ 1 V) to 38 V, VIN ≥ 2.7 V
IOUT = 1 to 150 mA
(V)
1.5%
High limit
2.3
1.0%
OUT
OUTPUT VOLTAGE, V
2.5
High limit
QUIESCENT CURRENT, IQ (mA)
2.0%
VOUT-NOM= 15 V
0.5%
VOUT-NOM= 5 V
0.0%
VOUT-NOM= 1.2 V
-0.5%
Low limit
-1.0%
-1.5%
1.9
1.7
1.5
Version-A
(non PG)
1.3
1.1
VIN = 38 V
IOUT= 0 mA
0.9
-2.0%
-40
-20
0
20
40
60
80
100
JUNCTION TEMPERATURE, TJ ( °C)
0.7
-40
120
Figure 6. Output Voltage vs. Temperature
-20
0
20
40
60
80
JUNCTION TEMPERATURE, TJ ( °C)
100
120
Figure 7. Quiescent Current vs. Temperature
1.6
1.10
ENABLE THRESHOLD VOLTAGE, VEN -TH (V)
High limit
1.4
SHUTDOWN CURRENT, I SHDN ( μA)
Version-B
(with PG)
2.1
Note:
Shutdown current is measured at IN pin
and includes EN pin pull-up current.
1.2
1.0
0.8
0.6
0.4
VIN = 38 V
VEN = 0 V
0.2
0.0
-40
-20
0
20
40
60
80
100
1.05
High limit
1.00
0.95
0.90
0.85
0.80
0.75
Low limit
0.70
0.65
0.60
-40
120
-20
JUNCTION TEMPERATURE, T J ( °C)
0
20
40
60
80
100
120
JUNCTION TEMPERATURE, TJ (°C)
Figure 8. Shutdown Current vs. Temperature
Figure 9. Enable Threshold Voltage vs.
Temperature
0.10
1.4
1.2
ADJ INPUT CURRENT, I ADJ (μA)
ENABLE PULL - UP CURRENT, I EN-PU ( μA)
1.6
High limit
1.0
0.8
0.6
0.4
0.2
High limit
0.08
0.06
0.04
0.02
VEN = 1 V
0.0
-40
-20
0
20
40
60
80
100
0.00
-40
120
TEMPERATURE (°C)
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 10. Enable Internal Pull−Up Current vs.
Temperature
Figure 11. ADJ Input Current vs. Temperature
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NCV8730
TYPICAL CHARACTERISTICS
VIN = VOUT−NOM + 1 V and VIN ≥ 2.7 V, VEN = 1.2 V, IOUT = 1 mA, COUT = 1.0 mF, ADJ tied to OUT, TJ = 25°C, unless otherwise specified
500
High limit
450
DROPOUT VOLTAGE, V DROP (mV)
400
350
VOUT = VOUT-NOM - 100 mV
IOUT = 150 mA
All output voltage versions
300
250
200
150
100
50
0
-40
-20
0
20
40
60
80
100
JUNCTION TEMPERATURE, TJ ( °C)
Figure 12. Dropout Voltage vs. Temperature
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120
NCV8730
TYPICAL CHARACTERISTICS
VIN = VOUT−NOM + 1 V and VIN ≥ 2.7 V, VEN = 1.2 V, IOUT = 1 mA, COUT = 1.0 mF, ADJ tied to OUT, TJ = 25°C, unless otherwise specified
4.3V
VIN
VIN
8.3V
150mA
150mA
1mA
IOUT
1mA
VOUT
3.3V
IOUT
+55mV
+58mV
3.3V
-115mV
-120mV
C1: VIN
C2: VOUT (ac)
C4: IOUT
VOUT
1.0V/div
50mV/div
100mA/div
20.0ms/div
C1: VIN
C2: VOUT (ac)
C4: IOUT
Figure 13. Load Transient − NCV8730−3.3 V,
COUT = 1 mF
20.0ms/div
Figure 14. Load Transient − NCV8730−3.3 V,
COUT = 1 mF
VIN
38.0V
2.0V/div
50mV/div
100mA/div
VIN
4.3V
150mA
150mA
1mA
IOUT
1mA
VOUT
3.3V
IOUT
+58mV
+37mV
3.3V
VOUT
-60mV
-120mV
C1: VIN
C2: VOUT (ac)
C4: IOUT
10.0V/div
50mV/div
100mA/div
20.0ms/div
C1: VIN
C2: VOUT (ac)
C4: IOUT
1.0V/div
50mV/div
100mA/div
50.0ms/div
Figure 16. Load Transient − NCV8730−3.3 V,
COUT = 10 mF
Figure 15. Load Transient − NCV8730−3.3 V,
COUT = 1 mF
VIN
4.3V
150mA
VIN
6.0V
150mA
IOUT
1mA
1mA
+55mV
+30mV
3.3V
IOUT
VOUT
VOUT
5.0V
-50mV
-115mV
C1: VIN
C2: VOUT (ac)
C4: IOUT
1.0V/div
50mV/div
100mA/div
50.0ms/div
C1: VIN
C2: VOUT (ac)
C4: IOUT
Figure 17. Load Transient − NCV8730−3.3 V,
COUT = 22 mF
5.0V/div
50mV/div
100mA/div
20.0ms/div
Figure 18. Load Transient − NCV8730−5.0 V,
COUT = 1 mF
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NCV8730
TYPICAL CHARACTERISTICS
VIN = VOUT−NOM + 1 V and VIN ≥ 2.7 V, VEN = 1.2 V, IOUT = 1 mA, COUT = 1.0 mF, ADJ tied to OUT, TJ = 25°C, unless otherwise specified
VIN
38.0V
VIN
6.0V
150mA
150mA
1mA
IOUT
1mA
VOUT
5.0V
IOUT
+48mV
5.0V
+36mV
VOUT
-60mV
-112mV
C1: VIN
C2: VOUT (ac)
C4: IOUT
10.0V/div
50mV/div
100mA/div
20.0ms/div
C1: VIN
C2: VOUT (ac)
C4: IOUT
Figure 19. Load Transient − NCV8730−5.0 V,
COUT = 1 mF
VIN
15.5V
150mA
150mA
1mA
IOUT
1mA
VOUT
15.0V
IOUT
+34mV
5.0V
-53mV
C1: VIN
C2: VOUT (ac)
C4: IOUT
50.0ms/div
Figure 20. Load Transient − NCV8730−5.0 V,
COUT = 10 mF
VIN
6.0V
5.0V/div
50mV/div
100mA/div
+55mV
VOUT
-120mV
5.0V/div
50mV/div
100mA/div
50.0ms/div
C1: VIN
C2: VOUT (ac)
C4: IOUT
Figure 21. Load Transient − NCV8730−5.0 V,
COUT = 22 mF
10.0V/div
100mV/div
100mA/div
20.0ms/div
Figure 22. Load Transient − NCV8730−15.0 V,
COUT = 1 mF
VIN
38.0V
VIN
15.5V
150mA
150mA
1mA
1mA
VOUT
15.0V
IOUT
+40mV
+50mV
15.0V
IOUT
VOUT
-110mV
-105mV
C1: VIN
C2: VOUT (ac)
C4: IOUT
10.0V/div
100mV/div
100mA/div
20.0ms/div
C1: VIN
C2: VOUT (ac)
C4: IOUT
Figure 23. Load Transient − NCV8730−15.0 V,
COUT = 1 mF
10.0V/div
50mV/div
100mA/div
50.0ms/div
Figure 24. Load Transient − NCV8730−15.0 V,
COUT = 10 mF
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NCV8730
TYPICAL CHARACTERISTICS
VIN = VOUT−NOM + 1 V and VIN ≥ 2.7 V, VEN = 1.2 V, IOUT = 1 mA, COUT = 1.0 mF, ADJ tied to OUT, TJ = 25°C, unless otherwise specified
VIN
15.5V
VIN
15.5V
150mA
150mA
IOUT
1mA
VOUT
15.0V
1mA
IOUT
+45mV
+16mV
15.0V
-98mV
C1: VIN
C2: VOUT (ac)
C4: IOUT
VOUT
-44mV
10.0V/div
50mV/div
100mA/div
50.0ms/div
C1: VIN
C2: VOUT (ac)
C4: IOUT
10.0V/div
20mV/div
100mA/div
100.0ms/div
Figure 25. Load Transient − NCV8730−15.0 V,
COUT = 22 mF
Figure 26. Load Transient − NCV8730−15.0 V,
COUT = 50 mF
Figure 27. PSRR − NCV8730−3.3 V, COUT = 1 mF,
IOUT = 10 mA
Figure 28. PSRR − NCV8730−3.3 V, COUT = 1 mF,
IOUT = 100 mA
Figure 29. PSRR − NCV8730−3.3 V, VIN = 4.3 V,
IOUT = 100 mA
Figure 30. PSRR − NCV8730−3.3 V, VIN = 8.3 V,
IOUT = 100 mA
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NCV8730
TYPICAL CHARACTERISTICS
VIN = VOUT−NOM + 1 V and VIN ≥ 2.7 V, VEN = 1.2 V, IOUT = 1 mA, COUT = 1.0 mF, ADJ tied to OUT, TJ = 25°C, unless otherwise specified
Figure 31. Noise – FIX − 5.0 V, IOUT = 1 mA,
COUT = 1 mF, Different VIN
Figure 32. Noise – FIX − 5.0 V, COUT = 1 mF,
Different IOUT
Figure 33. Noise – FIX − 5.0 V,
COUT = 1 mF + 10 mF, Different IOUT
Figure 34. Noise – FIX − 5.0 V,
COUT = 1 mF + 50 mF, Different IOUT
Figure 35. Noise – FIX − 5.0 V, IOUT = 10 mA,
Different COUT
Figure 36. Noise – FIX − 5.0 V, IOUT = 150 mA,
Different COUT
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NCV8730
TYPICAL CHARACTERISTICS
VIN = VOUT−NOM + 1 V and VIN ≥ 2.7 V, VEN = 1.2 V, IOUT = 1 mA, COUT = 1.0 mF, ADJ tied to OUT, TJ = 25°C, unless otherwise specified
Figure 37. Noise – ADJ−set−5.0 V with
Different CFF and FIX − 5.0 V
Figure 38. Noise – FIX, IOUT = 10 mA,
COUT = 1 mF, Different VOUT
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NCV8730
APPLICATIONS INFORMATION
Input Capacitor Selection (CIN)
divider for adjustment. When it is connected to the OUT pin
the output voltage of the circuit is simply the same as the
nominal output voltage of the LDO. At this case, without
ADJ resistor divider, the LDO should be loaded by at least
200 nA (by the application or added pre−load resistor).
When connected to the resistor divider the output voltage
could be computed as the ADJ reference voltage (1.2 V)
multiplied by the resistors divider ratio, see following
equation.
Input capacitor connected as close as possible is necessary
to ensure device stability. The X7R or X5R capacitor should
be used for reliable performance over temperature range. The
value of the input capacitor should be 1 mF or greater (max.
value is not limited). This capacitor will provide a low
impedance path for unwanted AC signals or noise modulated
onto the input voltage. There is no requirement for the ESR
of the input capacitor but it is recommended to use ceramic
capacitor for its low ESR and ESL. A good input capacitor
will limit the influence of input trace inductance and source
resistance during load current changes. When a large load
transients (like 1 mA to 150 mA) happens in the application
the input power source of the LDO needs to provide enough
power and the input voltage must not go below the level
defined by this equation: VIN = VOUT−NOM + VDO
otherwise the output voltage drop will be significantly
higher (because LDO will enter the dropout state). In some
cases when power supply powering the LDO has a poor load
transient response or when there is a long connection
between LDO and its power source then capacitance of input
capacitor needs to be high enough to cover the LDO’s input
voltage drop caused by load transient and maintains its value
above the VIN = VOUT−NOM + VDO level (then CIN could be
in range of hundreds of mF).
ǒ
V OUT + V ADJ @ 1 )
Ǔ
R1
) I ADJ @ R 1
R2
(eq. 1)
Where:
VOUT is output voltage of the circuit with resistor divider.
VADJ is the LDO’s ADJ reference voltage.
IADJ is the LDO’s ADJ pin input current.
R1 and R2 are resistors of output resistor divider.
At the classical “old style” regulators like LM317 etc. the
resistors where small (100 W − 10 kW) to make regulator
stable at light loads (divider was also a pre−load function).
On NCV8730, which is very low quiescent current LDO
regulator (1 mA), we need to care about current consumption
of surrounding circuitry so we need to set the current through
resistor divider flowing from VOUT through R1 and R2 to
GND, as low as possible.
On the other hand, the parasitic leakage current flowing
into ADJ pin (IADJ) causes VOUT voltage error (given by
IADJ ⋅ R1). The IADJ is temperature dependent so it is
changing and we cannot compensate it in application, we
just can minimize the influence by setting of R1 value low,
what is in opposite to maximizing its value because of
current consumption.
So when selecting the R1 and R2 values we need to find a
compromise between desired VOUT error (temperature
dependent) and total circuit quiescent current.
If we want to simplify this task, we can say the IR2 should
be 100−times higher than IADJ at expected TJ temperature
range. If we chose the ratio “IR2 to IADJ” higher (for example
more than 100 as stated before), the ΔVOUT error caused by
IADJ change over temperature would be lower and opposite,
if the ratio “IR2 to IADJ” is smaller, the error would be bigger.
In limited TJ temperature range −40°C to +85°C the IADJ
is about 10−times smaller than in the full temperature range
−40°C to +125°C (see typical characteristics graph of IADJ
over temperatures), so we can use bigger R1, R2 values, as
could be seen at next examples.
Example 1:
Desired VOUT voltage is 5.0 V. Computed maximal TJ in
application (based on max. power dissipation and cooling)
is 85°C. Than IADJ at 85°C is about: IADJ85 = 10 nA.
Output Capacitor Selection (COUT)
The LDO requires the output capacitor connected as close
as possible to the output and ground pins. The LDO is
designed to remain stable with output capacitor’s effective
capacitance in range from 1 mF to 100 mF and ESR from
1 mW to 200 mW. The ceramic X7R or X5R type is
recommended due to its low capacitance variations over the
specified temperature range and low ESR. When selecting
the output capacitor the changes with temperature and DC
bias voltage needs to be taken into account. Especially for
small package size capacitors such as 0402 or smaller the
effective capacitance drops rapidly with the applied DC bias
voltage (refer the capacitor’s datasheet for details). Larger
capacitance and lower ESR improves the load transient
response and PSRR.
Output Voltage
NCV8730 is available in two version from output voltage
point of view. One is fixed output voltage version (FIX
version) and the other one is adjustable output voltage
version (ADJ version).
The ADJ version has ADJ pin, which could be connected
to the OUT pin directly, just to compensate voltage drop
across the internal bond wiring and PCB traces or could be
connected to the middle point of the output voltage resistor
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13
NCV8730
VOUT =5V
OUT
ADJ version
GND
R1
3.76 MW
ADJ version
COUT
1mF
IR1
1.01uA
IADJ
10nA
VOUT
5V
ADJ
GND
IR2
1uA
VR2 =VADJ
1.2V
R1
376 kW
COUT
1mF
IR1
10.1uA
IADJ
100nA
VOUT
5V
ADJ
IR2
10uA
VR2 =VADJ
1.2V
R2
1.2 MW
Figure 39. ADJ Output Voltage Schematic − Example 1
R2
120 kW
Figure 40. ADJ Output Voltage Schematic − Example 2
We chose:
We chose:
I R2 + 100 @ I ADJ85 + 100 @ 10E−9 + 1 mA
I R2 + 100 @ I ADJ125 + 100 @ 100E−9 + 10 mA
Then:
Then:
V
R 2 + R2 + 1.2 + 1.2 MW
I R2
1E−6
R1 +
VOUT =5V
OUT
V
* V R2
V R1
5 * 1.2
+ OUT
+
I R1
I ADJ85 ) I R2
10E−9 ) 1E−6
+
R2 +
V R2
+ 1.2 + 120 kW
I R2
10E−6
R1 +
V
* V R2
V R1
5 * 1.2
+ OUT
+
I R1
I ADJ125 ) I R2
100E−9 ) 10E−6
3.8 + 3.762 MW
1.01E−6
+
Verification:
For low temperature (TJ = 25°C) the IADJ25 = 1 nA:
ǒ
V OUT + V ADJ @ 1 )
Verification:
For low temperature (TJ = 25°C) the IADJ25 = 1 nA:
Ǔ
ǒ
R1
) I ADJ @ R 1
R2
ǒ
V OUT + V ADJ @ 1 )
Ǔ
Ǔ
R ADJ1
) I ADJ @ R ADJ1
R ADJ2
ǒ
V OUT + 1.2 @ 1 ) 3.762E6 ) 1E−9 @ 3.762E6
1.2E6
Ǔ
V OUT + 1.2 @ 1 ) 376.2E3 ) 1E−9 @ 376.2E3
120E3
+ 4.966 V
+ 4.962 V
For maximal temperature (TJ = 85°C) the IADJ85 = 10 nA:
ǒ
3.8 + 376.2 kW
10.1E−6
For maximal temperature (TJ = 125°C) the IADJ125 = 100 nA:
Ǔ
ǒ
V OUT + 1.2 @ 1 ) 3.762E6 ) 10E−9 @ 3.762E6
1.2E6
Ǔ
V OUT + 1.2 @ 1 ) 376.2E3 ) 100E−9 @ 376.2E3
120E3
+ 5.000 V
+ 5.000 V
Output voltage error for temperatures 85°C to 25°C is:
Output voltage error for temperatures 125°C to 25°C is:
V
* V OUT25
DV OUT + OUT85
@ 100
V OUT85
DV OUT +
V OUT125 * V OUT25
@ 100
V OUT125
+ 5.000 * 4.966 @ 100 + 0.68%
5.000
+ 5.000 * 4.962 @ 100 + 0.76%
5.000
Total circuit quiescent current at TJ = 25°C is:
Total circuit quiescent current at TJ = 25°C is:
I Q(TOT) + I Q(LDO) ) I R1 + 1.3E−6 ) 1.01E−6 + 2.31 mA
I Q(TOT) + I Q(LDO) ) I R1 + 1.3E−6 ) 10.1E−6 + 11.4 mA!!!
We can see that current consumption of external resistor
divider is almost the same as quiescent current of LDO.
Example 2:
Desired VOUT voltage is 5.0 V. Computed maximal TJ in
application (based on max. power dissipation and cooling)
is in this case higher, 125°C, to show the difference. Than
maximal IADJ at 125°C is IADJ125 = 100 nA (based on
Electrical characteristics table).
We can see that error of VOUT voltage is almost the same as
in example 1 (because we have used the same “IR2 to IADJ”
ratio = 100x) but the application quiescent current is almost
10−times higher (because of 10−times higher divider
current).
CFF Capacitor
Even the NCV8730 is very low quiescent current device,
both the load transients over/under shoots and settling times
are excellent. See the Typical characteristics graphs.
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14
NCV8730
At adjustable application, the external resistor divider
with input ADJ pin capacity and ADJ pin PCB trace capacity
to GND makes a low pass filter what negatively affects the
dynamic behavior of the LDO. On the next picture is shown
how this unwanted side effect could be compensated by
adding of feed−forward capacitor CFF across R1 resistor.
VOUT=5V
OUT
R1
2M4
ADJ version
GND
ADJ
CFF
1nF
COUT
1mF
1.2V
R2
750k
Figure 44. PSRR – Different CFF
Figure 41. ADJ Output Voltage Schematic − CFF
Capacitor
The value of the CFF depends on R1 and R2 resistor values.
When R1, R2 values are in hundreds of kiloohms, proposed
CFF value is 1 nF, as shown on picture above, for the best
dynamic performance. Generally, the value could be in
range from 0 to 10 nF.
On next three pictures is shown the CFF capacitor
influence to dynamic parameters.
I OUT =1−to−150mA – 100mA/div VIN =4.3V – 1V/div
C FF =0pF
VOUT =3.3V – 50mV/div
Figure 45.
Startup
C FF = 100p
CFF =1nF
In the NCV8730 device there are two main internal
signals which triggers the startup process, the under−voltage
lockout (UVLO) signal and enable signal. The first one
comes from UVLO comparator, which monitors if the IN
pin voltages is high enough, while the second one comes
from EN pin comparator. Both comparators have embedded
hysteresis to be insensitive to input noise.
Not only the comparator but also the pull−up current
source is connected to EN pin. Current source is sourcing
IEN-PU = 300 nA current flowing out of the chip what
ensures the level on the pin is high enough when it is left
floating. The comparator compares the EN pin voltage with
internal reference level 0.9 V (typ.). Hysteresis is 100 mV
(typ.).
The UVLO comparator threshold voltage is 1.95 V (typ.)
and hysteresis is 200 mV (typ.).
ASNADJ set to 3.3 V
C FF =10pF
Time – 10ms/div
Figure 42. Load Transient – Different CFF
ASNADJ set to 3.3 V
VIN = 0´ 38V − 5V/div
CFF =0pF
VOUT =3.3V – 1V/div
CFF = 100pF
C FF =1nF
Time – 2ms/div
Figure 43. Startup Timing – Different CFF
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15
NCV8730
IN
OUT
V IN
UVLO
IEN −PU = 300 nA
1.95 V
V C CEN
V−REFERENCE
AND SOFT−START
V R EF
1.2V
EA
C IN
1 mF
RADJ1
GND
DEGLITCH
DELAY TMR
VIUL−TH
VIUL−TH – VIUL−HY
VIN−TOP
VEN = VIN
PG
PG Comparator
93% of VR EF
EN
VIN
GND
THERMAL
SHUTDOWN
0.9 V
C OUT
1 mF
VIN−TOP
RADJ2
EN Comparator
V OUT
Figure 49. Circuit – EN Pin Connected to IN Pin
ADJ
Enable
300 nA
OUT
LDO
V EN
V FB =1.2V
EN
IN
Current limit
UVLO Comparator
VEN−TH
VEN−TH – VEN−HY
VOUT−NOM
NC
95% of VOUT−NOM
VOUT
Time
tSTART
Figure 46. Internal Block Diagram – EN Pin
Figure 50. Startup Timing – EN Pin Connected to IN
Pin
Startup by IN Pin Voltage
When the LDO is started by IN pin voltage rise, it is turned
ON when the voltage is higher than UVLO threshold level.
This is the case of both following application circuits, the
first one with EN pin floating and the second one with EN
pin connected to IN pin.
When the EN pin is floating (left unconnected) its voltage,
after the LDO is powered, rises to VCCEN level
(2.5 V – 4.5 V, VIN dependent) as the internal current source
pulls the pin voltage up. VCCEN voltage level on EN pin is
higher than EN comparator threshold so the LDO is turned
ON.
IN
V IN
C IN
1 mF
OUT
EN
Startup by EN Pin Voltage
When VIN voltage in the application is settled above the
VIUL-TH level and control voltage to the EN pin is applied,
the level higher than VEN−TH enables the LDO and the level
lower than (VEN-TH – VEN-HY) disables it.
Startup time is measured from point where VEN voltage
reaches VEN−TH value to point when VOUT voltage reaches
95% of its nominal value.
V OUT
C OUT
1mF
LDO
V EN
Startup time in both cases above is measured from the
point where IN pin voltage reaches VIUL−TH value to point
when OUT pin voltage reaches 95% of its nominal value.
The reason why the LDO is started by the UVLO signal
and not by the enable signal is the fact that the UVLO signal
turns to valid state later then the enable. (EN pin voltage
reaches the VEN-TH level prior the IN pin voltage reaches the
VIUL-TH level).
GND
Figure 47. Circuit – Floating EN Pin
VIN−TOP
VIN
V IN
IN
C IN
1mF
VIUL−TH
VIUL−TH – V IUL−HY
VCCEN
VOUT−NOM
VEN−TH
VEN−TH – V EN−HY
V OUT
COUT
1mF
LDO
V EN
VEN
OUT
EN
GND
Figure 51. Circuit – LDO Controlled by VEN
95% of VOUT−NOM
VOUT
Time
t START
V IN
V IUL−TH
V IUL−TH – V IUL−HY
V EN
V EN−TH
V EN−TH – V EN−HY
Figure 48. Startup Timing – Floating EN Pin
It is also possible to connect EN pin directly to IN pin in
the whole input voltage range. The startup sequence is very
similar to previous case, the only difference is that the EN
pin voltage is not clamped to VCCEN level but it is the same
as VIN voltage.
VOUT−NOM
95% of VOUT−NOM
V OUT
Time
t START
Figure 52. Timing – VEN−Startup
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16
NCV8730
Startup by IN Pin Voltage − Delayed
signal makes it high because the transistor is connected as
signal invertor.
In this application we need to care about transistor’s
leakage current which must be negligible compared to the
internal pull−up current IEN−PU = 300 nA otherwise
additional pull−up resistor REN will be needed. The
maximum value of the EN resistor REN-MAX is computed
from maximal external transistor leakage current (over
desired temperature range) IT-LK-MAX and minimal input
voltage VIN−MIN:
The startup time triggered by IN pin voltage rise could be
delayed by adding of EN pin capacitor (CEN). The startup
sequence is following − after the VIN voltage is applied, the
charging of CEN capacitor by internal pull−up current
(IEN-PU) is started. When the CEN capacitor voltage (VCEN)
reaches EN comparator’s threshold voltage (VEN−TH) the
LDO is enabled. Charging of CEN continues up to the VCCEN
level (2.5 V – 4.5 V, VIN dependent) with no following effect.
The steepness of the LDO’s output voltage rise (soft−start
time) is not affected by using of CEN capacitor. The
additional delay time (tCEN−DELAY) could be computed by:
t CEN−DELAY + C EN @
V EN−TH
0.9 V
+ C EN @
I EN−PU
300 nA
R EN−MAX +
(eq. 3)
I SD(TOT) + I SD(LDO) ) I REN
Value of the CEN capacitor could be in range from 0 to
several microfarads. Capacitor’s leakage current must be
negligible to internal pull−up current IEN−PU, otherwise the
charging will be affected and adding of REN resistor from IN
to EN pin will be needed.
V IN
IN
C IN
1mF
C EN
EN
I EN−PU
I Q(TOT)
R EN
IN
CIN
1 mF
Figure 53. Circuit – CEN−Delayed VIN−Startup
REN
Opt.
I REN
V EN
I EN−PU
V IN
VCTRL
VCCEN
VEN−TH
(eq. 6)
I Q(LDO)
VIN
VEN
ǒVIN * VT−DSǓ
I Q(TOT) + I Q(LDO) ) I T−LK
GND
(without CEN )
(eq. 5)
Where VT−DS is the drain to source voltage of the transistor
(given by RDSON and IREN).
The overall application quiescent current when REN is
used is influenced only by the transistor’s leakage current
IT−LK.
COUT
1 mF
LDO
V EN
I REN +
VOUT
OUT
(eq. 4)
For safe, select the EN resistor value REN lower enough
to computed REN-MAX.
When REN is used the overall application shutdown
current is increased because the current through REN resistor
(IREN) is added to input shutdown current of the LDO
(ISD(LDO)). The total application shutdown current
(ISD(TOT)) is:
(eq. 2)
The total startup time (tSTART-CEN) with connected CEN
capacitor is a sum of normal startup time (tSTART) and
additional delay time caused by CEN capacitor
(tCEN-DELAY):
t START−CEN + t START ) t CEN−DELAY
V IN−MIN
I T−LK−MAX
OUT
VOUT
COUT
1mF
LDO
EN
GND
IT
Figure 55. Circuit – EN Pin Controlled by Transistor
(with CEN )
VOUT−NOM
VOUT
(with CEN )
(without CEN )
95% of VOUT−NOM
VCTRL
Time
t CEN−DELAY
t START
t START−CEN
VEN−TH
VEN−TH – V EN−HY
V EN
Figure 54. Timing – CEN−Delayed VIN−Startup
V OUT−NOM
95% of VOUT−NOM
VOUT
Startup by Transistor at EN Pin
Time
If the LDO needs to be controlled by transistor or
generally by open collector / open drain circuit as shown at
the next picture, the control behavior is inverted. High
control signal makes the EN pin voltage low and low control
t START
Figure 56. Startup Timing – EN Pin Controlled by
Transistor
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17
NCV8730
Startup by Transistor at EN Pin − Delayed
UVLO threshold value, the external resistor divider from IN
pin to EN pin, is needed.
Note that the specification of EN pin threshold voltage
(0.7 V to 1.05 V over full operating temperature range) is
not as precise as threshold voltage on dedicated UVLO
devices. The reason is the EN circuit has to have ultra−low
current consumption (NCV8730 ISHDN is 350 nA typ. even
while IEN−PU is 300 nA typ. so EN comparator is powered
by less than 50 nA typ.). We need to count with that when
thinking about the IN pin UVLO design. Below is the
application example to show what precision we can get.
The startup time triggered by EN pin voltage rise, could
be delayed the same way as IN pin triggered startup, by
adding of CEN capacitor. The startup sequence is following
– when the external NMOS control voltage (VCTRL) is high
the CEN capacitor connected to the EN pin is shorted to GND
and LDO is disabled. After the VCTRL is turned low the
charging of CEN capacitor by the internal pull−up current
source (IEN-PU) starts. When the CEN capacitor voltage
(VCEN, which is the VEN in fact) reaches EN comparator’s
threshold voltage (VENTH) the LDO is enabled. Charging of
CEN then continues up to the VCCEN level (2.5 V – 4.5 V,
VIN dependent) with no following effect. The steepness of
the LDO’s output voltage rise (soft−start time) is not affected
by using of CEN capacitor. The additional delay time
(tCEN-DELAY) could be computed by eq. 2 and the total
delayed startup time with CEN capacitor (tSTART-CEN) by eq.
3. What has been said about the CEN capacitor selection at
previous paragraphs is applicable here as well.
Also in this application we need to care about transistor’s
leakage current which must be negligible compared to the
internal pull−up current IEN−PU = 300 nA otherwise
additional pull−up resistor REN will be needed. Same rules
and computations as stated in previous paragraph about REN
are applicable here. Note that REN would influence the speed
of CEN capacitor charging.
IQ(TOT)
VIN
CIN
1mF
I Q(LDO)
IN
I REN
REN
Opt.
V EN
I EN−PU
CIN
1 mF
CEN
100pF
Optional
COUT
1 mF
(with CEN)
VOUT−NOM
VOUT
(without CEN)
(with CEN)
I REN2
R EN1 +
V IN−UVLO−TH * V EN−TH
I REN1
R EN2 +
V EN−TH
I REN1 ) I EN−PU
(eq. 7)
From that, we can get:
ǒ
GND
VCCEN
GND
The two main equations for IN pin threshold computation
are:
V IN−UVLO−TH + V EN−TH @ 1 )
Ǔ
(eq. 8)
R EN1
* R EN1 @ I EN−PU
R EN2
We can see that IN pin UVLO threshold is EN pin
threshold multiplied by the resistor divider ratio as expected
but it is unwillingly affected by IEN-PU pull−up current. As
the IEN-PU current could vary up to the 1 mA max., we need
to choose the IREN1 current several times higher to make the
IEN-PU influence negligible. The good practice could be to
choose IREN1 at least 10−times higher than IEN-PU (the
bigger the better for the accuracy).
An optional component in this application is CEN capacitor.
Its main function is filtering out the spurious signals coming
from IN power supply and the minor function is to delay the
startup as described in section before. The value of CEN for
filtering purpose could be in range from 10 pF to 10 nF. The
time constant of this filter is given by:
VCTRL
(without CEN)
EN
VOUT
COUT
1mF
LDO
I EN−PU
REN2
OUT
Figure 59. Circuit – IN Voltage UVLO by EN Pin
Figure 57. Circuit – EN Pin with CEN Controlled by
Transistor
VEN
REN1
I REN1
V EN
C EN
VCTRL
I Q(LDO)
IN
VOUT
OUT
LDO
EN
I Q(TOT)
VIN
VEN−TH
95% of VOUT−NOM
Time
tCEN−DELAY
tSTART
tSTART −CEN
t FILTER + C EN @
Figure 58. Startup Timing – EN Pin with CEN
Controlled by Transistor
R EN1 @ R EN2
R EN1 ) R EN2
(eq. 9)
The side effect of the UVLO divider is increased overall
power consumption. At no load state, the quiescent current
IQ(TOT) of the application is:
Enable Input as Inaccurate IN Pin UVLO
I Q(TOT) + I Q(LDO) ) I REN1
The EN input pin on NCV8730 device is specified by
threshold voltage and hysteresis both with minimum and
maximum value, what allows using EN comparator as
adjustable input voltage UVLO function. To set the VIN
(eq. 10)
So if we select the IREN1 value at least 10−times higher
than IEN-PU-MAX (1 mA), then the UVLO divider current is
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18
NCV8730
Output Current Limit
almost 10-times higher than typical LDO’s quiescent
current (1.3 mA).
IN voltage UVLO application example:
Desired VOUT voltage is 5 V, the LDO’s input voltage in
normal state is 12 V. We want to turn−off the LDO’s output
voltage when input voltage is below 10 V (max.).
First, choose the IREN1 current as 10−times the maximum
IEN-PU current:
I REN1 + 10 @ I EN−PU + 10 @ 1 mA + 10 mA
Output current is internally limited to 280 mA typ. The
LDO will source this current when the output voltage drops
down from the nominal output voltage (test condition is 90%
of VOUT−NOM). If the output voltage is shorted to ground,
the device continues with current limitation at the same
current level. The current limit and short circuit protection
will work properly over the whole temperature and input
voltage ranges. There is no limitation for the short circuit
duration.
Minimal output current limit value is 200 mA what could
be used to cover current demand peaks, higher than the
LDO’s nominal output current (150 mA).
(eq. 11)
Then, to obtain REN1 and REN2 values for maximal
VIN-UVLO-TH = 10 V, we need to put maximum value of
VEN-TH (1.05 V) and minimum value of IEN-PU (0 mA) into
the equations for REN1 and REN2:
Inrush Current
(eq. 12)
At every application, the startup sequence needs a special
care because during power−up the bypass capacitors
connected to the power rail are charged from zero to input
voltage level, what generates a current spike, so called
inrush current. The size of such current spike depends on the
voltage transient slope (the faster the bigger spike), on the
total impedance of the loop from the power source to bypass
capacitor (traces impedance, power source internal
impedance and capacitor impedance; the lower the bigger
spike) and on the capacitor value (the higher the bigger
spike).
This inrush current during startup could cause power
source’s overcurrent event, damage of PCB traces, power
line fuses blowing or spurious signal generation in
surrounding application parts.
For a simplified case when total impedance between input
power source and bypass capacitor is zero, we can use
following equation to compute the inrush current, based just
on voltage transient slope (dV/dt) and the capacitor value:
−V
V
10 V−1.05 V
R EN1 + IN−UVLO−TH EN−TH +
+ 895 kW
I REN1
10 mA
R EN2 +
V EN−TH
1.05
+
+ 105 kW
I REN1 ) I EN−PU
10 mA ) 0 mA
The resulting VIN-UVLO-TH limits will be:
ǒ
V IN−UVLO−TH−MIN + V EN−TH−MIN @ 1 )
ǒ
V IN−UVLO−TH−MIN + 0.7 @ 1 )
(eq. 13)
R EN1
* R EN1 @ I EN−PU−MAX
R EN2
Ǔ
Ǔ
895 kW
* 895 kW @ 1 mA
105 kW
V IN−UVLO−TH−MIN + 5.77 V
ǒ
V IN−UVLO−TH−MAX + V EN−TH−MAX @ 1 )
ǒ
V IN−UVLO−TH−MAX + 1.05 @ 1 )
Ǔ
R EN1
* R EN1 @ I EN−PU−MIN
R EN2
Ǔ
895 kW
−895 kW @ 0 mA
105 kW
V IN−UVLO−TH−MAX + 10.0 V
I Q(TOT) + I Q(LDO) ) I REN1 + 1.3 mA ) 10 mA + 11.3 mA
i INRUSH + C @ dV
dt
When higher IREN1 is selected the VIN-UVLO-TH-MIN
would be slightly near the target value, the
VIN-UVLO-TH-MAX would stay the same but the IQ(TOT)
would be significantly higher:
I REN1 + 100 @ I EN−PU + 100 @ 1 mA + 100 mA
Example – when the voltage changes from 0 V to 24 V in
10 ms and bypass capacitor is 10 mF, the inrush current is:
i INRUSH + 10 mF @
(eq. 14)
We would get:
R EN1 + 89.5 kW
(eq. 16)
24 V * 0 V
+ 24A
10 ms
(eq. 17)
Of course, this is the worst case when impedances in the
circuit are zero, but it shows why we need to care about
startup and what defines the inrush current value. We can see
the inrush current is lower when capacitance and voltage
change are smaller or transition time is longer.
In most cases, the capacitor value and the input voltage
change are defined by the application so then the only thing
we can do is to slow down the input voltage transition time.
We can do it directly by changing input voltage rise time by
soft−start circuit (related to Equation 16) or indirectly by
adding a current limit block, which in combination with the
capacitor will do the same (slower the input voltage rise), see
the following equation:
(eq. 15)
R EN2 + 10.5 kW
V IN−UVLO−TH−MIN + 6.58 V
I Q(TOT) + I Q(LDO) ) I REN1 + 1.3 mA ) 100 mA + 101.3 mA
We can see the IN pin UVLO threshold precision
computed above (5.77 V or 6.58 V min. / 10.0 V max.) is not
too high because the EN pin threshold and EN pin internal
pull−up current specifications are not so tight as on
dedicated UVLO devices but at some applications this
precision could fit the needs.
t START + C @ dV
I LIMIT
www.onsemi.com
19
(eq. 18)
NCV8730
We see that voltage transition time (tSTART) is given by
bypass capacitor value (C), by the voltage change (dV) and
by current limit value (ILIMIT) of added current limit block.
Now back to LDO application. Here we can see two
different inrush current spikes. The first one is caused by the
LDO’s input capacitor (CIN) charging from zero to the input
voltage level. It happens when the previous power block (for
example DC/DC) starts providing the input voltage to the
LDO circuit. The maximum level of this inrush current is
given by Equation 16. It doesn’t matter if LDO is enabled or
disabled as this inrush current spike is related only to CIN
and it can’t be suppressed by the LDO, it is matter of
previous power block. This inrush current spike is shown at
Figure 61, point (1).
The second inrush current spike is generated by the LDO’s
output capacitor (COUT) charging from zero to nominal
output voltage level. It happens when the LDO is enabled by
any way (by driving EN pin or by internal UVLO when EN
pin is connected to IN pin). This inrush current is limited by
the LDO’s soft−start and current limit functions.
Soft−start function limits the speed of the output voltage
rise to avoid possible latch−up of application circuit caused
by high dV/dt what naturally suppresses input inrush current
(related to Equation 16).
The current limit function, used to guard the LDO and
application against the overcurrent, is also used during the
LDO’s startup to limit the input inrush current.
Now focus onto the NCV8730 device. At the next picture
we can see both, soft−start and current limit functions have
been implemented, shown in red. At this device, the startup
current limit level is the same as the normal operation
current limit level (specified at the parametric table).
current limit value). While at the case of big output capacitor
(for example 47 mF), the soft−start time is not slow enough
and the input current needs to be limited by the current limit
function.
Next picture shows both startup cases – with small (1 mF)
and big (47 mF) output capacitors. Startup is caused by IN
voltage rise, EN pin is connected to IN pin and device
voltage version is 5.0 V.
(3)
C1: VIN
C2: VOUT
C4: I IN
IEN −PU = 300nA
EN
V CCEN
V−REFERENCE
AND SOFT−START
V REF
1.2V
EA
RADJ1
RADJ2
DV OUT
t START
5V*0V
+ 470 mA (eq. 20)
500 ms
Therefore, in this case the current limit is activated and
limits the COUT charging current to about 280 mA (from the
picture, point−3). This leads to enlarging of startup time to:
ADJ
t START + C OUT @
GND
DV OUT
I LIMIT
5V*0V
t START + 47 mF @
+ 870 ms
270 mA
DEGLITCH
DELAY TMR
(eq. 19)
With the COUT = 47 mF, the inrush current should be
47−times higher than in case of 1 mF:
THERMAL
SHUTDOWN
PG Comparator
93 % of V REF
200 μs/div
1.0V/div
1.0V/div
200mA/div
5V*0V
i INRUSH−1mF + 1 mF @
+ 9 mA
550 ms
Enable
0.9 V
47μF
i INRUSH−47mF + 47 mF @
V FB =1.2V
EN Comparator
1μF
i INRUSH + C OUT @
Current limit
UVLO
IIN
VIN
VOUT
With the COUT = 1 mF, the inrush current (seen at IIN
signal at point−2) is almost zero, its level is defined by
soft−start time which is about 550 ms (from the picture).
OUT
1.95 V
47μF
Figure 61.
IN
UVLO Comparator
1μF
(2)
0³6 V, t R = 10μs
(1)
PG
(eq. 21)
One additional thing could be seen at the picture above
and it is a small current spike highlighted as a point−1 at the
IIN curve. It is the inrush current caused by input voltage
transient (from 0 V to 6 V in 10 ms) and input capacitor
CIN = 100 nF. As stated before, for this current spike is
responsible the prior power source, not the LDO (in this case
the test equipment which generates the VIN transient). The
CIN inrush current amplitude is:
NC
Figure 60.
A few practical notes. If the LDO’s output capacitor value
is small (for example 1 mF), then soft−start limited output
voltage rise is slow enough to suppress the inrush current
(output capacitor charging current, generated by dVOUT/dt,
based on Equation 16, is significantly smaller than the
i INRUSH_POINT−1 + 100 nF @
www.onsemi.com
20
6V*0V
+ 60 mA (eq. 22)
10 ms
NCV8730
Power Supply Rejection Ratio
different power supply voltage to the LDO’s VOUT level.
Below are the connections examples.
The LDO features high power supply rejection ratio even
it is very low quiescent current device. See the Typical
characteristics section for the graphs over different
conditions.
The PSRR at higher frequencies (from about 100 kHz) can
be tuned by the selection of COUT capacitor, applied input
voltage and proper PCB layout (minimizing impedance
from load to COUT).
IN
5.0V
OUT
COUT
1 mF
BMT500
EN
VCC
RPG
PG
GND
Application
PGI
CTRL
PG Output
Version B of the NCV8730 device contains PG circuit for
the VOUT voltage level monitoring. Internally it is combined
from PG comparator, deglitch/delay timer and output
NMOS transistor (highlighted by red color at picture
below). At both, ADJ and FIX versions, the PG comparator
compares internal feedback signal voltage (VFB) with the
93% of VREF (typ.) what makes the function independent to
the output voltage absolute value (it always compares set
VOUT with 93% of its nominal value).
Figure 63. Circuit Example – PG Connected to LDO’s
Output
IN
5.0V
OUT
BMT500
EN
VCCA
COUT
1 mF
PG
GND
3.3V
VCCD
R PG
IN
OUT
UVLO
I EN −PU = 300 nA
1.95 V
V CCEN
V−REFERENCE
AND SOFT−START
VR EF
1.2V
EA
ADJ
Enable
0.9 V
RADJ2
GND
THERMAL
SHUTDOWN
PG
PG Comparator
93% of VR EF
Following timing diagrams show the situation when LDO
falls out of regulation 3 times (output voltage drops down
from nominal value) because of (for example) insufficient
IN pin voltage.
Note that the VPG voltage at “power ok state” follows the
voltage where the RPG is connected because the PG output
is in Hi−Z state and just RPG connection point defines the
VPG level. In the first example when RPG is connected to
LDO’s output, the VPG follows the LDO’s VOUT including
the drops. In the second example the RPG is connected to
LDO independent power rail (3.3 V) so the VPG is not
following the LDO’s output voltage.
RADJ1
EN Comparator
Appl.
Part 2
(MCU)
Figure 64. Circuit Example – PG Connected to
Application Power Supply
VFB =1.2V
EN
PGI
CTRL
Current limit
UVLO Comparator
Appl.
Part 1
(analog)
DEGLITCH
DELAY TMR
NC
Note: Blue objects are valid for ADJ version
Green objects are valid for FIX version
Red objects are valid for B version (with PG)
t OUT−LOW < t PG−DG
t PG−DG
5V
Figure 62. Power Good Output Block Diagram
The PG output is in high impedance state (Hi−Z) to show
“power ok state” when the VOUT voltage is above the PG
threshold level (VPG-TH) or is shorted to GND pin to show
“power fail state” when the VOUT falls below the level
(VPG-TH – VPG-HY).
The PG threshold voltage is 93% of VOUT-NOM (typ.) and
the hysteresis is 2% of VOUT-NOM (typ.).
Because the PG output is open drain type it needs to be
connected by external pull resistor to a voltage level, which
defines the PG pin voltage at time when it is in Hi−Z state.
It allows connections of PG pin to circuit with the same or
t PG−DLY
V PG−TH
V PG−TH – VPG−HY
VOUT
R PG~10kW (t~500ns)
5V
R PG ~100kW (t~5ms)
V PG
Time
Time
region
1
2
3
4
Figure 65. Timing – PG Connected to LDO’s Output
www.onsemi.com
21
NCV8730
t OUT−LOW < t PG−DG
t PG−DG
5V
t PG−DLY
through the RPG to the grounded PG pin. This is just a case
of the power fail state so probably not a concern too.
At the electrical characteristics table we can find the
parameter “PG Output Low Level Voltage (VPG-OL)” which
defines the drop across the PG internal transistor when it
sinks current 1 mA. We can take this current condition
(1 mA) as a maximal PG current (IPG−MAX) for the RPG−MIN
computation (as we know the PG drop at this level, 0.4 V
max.). If the application input current IPGI is negligible to
IRPG we can compute the RPGI−MIN by:
V PG−TH
V PG−TH – VPG−HY
VOUT
R PG~10kW (t~500ns)
3.3V
R PG ~100kW (t~5ms)
VPG
Time
Time
region
1
2
3
R PG−MIN +
4
Figure 66. Timing – PG Connected to Application
Power Supply 3.3 V
V CC−RPG
I PG−MAX
(eq. 23)
And, for example, when RPG is connected to 3.3 V power
rail:
The timing diagrams have been divided into 4 time
regions to show different situations:
In region−1, the VOUT drop is not deep enough so the PG
output shows “power ok state”.
In region−2, the VOUT drop is deeper and crosses the
VPG-TH threshold level but the duration of the drop is shorter
then PG deglitch time (tPG-DG = 160 ms typ.) so the PG
output still shows “power ok state”. Note that the deglitch
time has been intentionally implemented to filter out
spurious output voltage drops (caused for example by fast
load transients etc.).
In both two first regions the VPG is high and follows the
voltage level where the RPG resistor is connected to
(VLDO(OUT) or VCCD).
In region−3, the VOUT drop is deep enough and the
duration is longer then tPG-DG time so the PG output is
shorted to GND pin and shows power fail state.
In region−4, the VOUT returns back to its nominal value.
When it crosses the level (VPG-TH – VPG-HY) the PG output
turns from short to GND into Hi−Z state, not immediately,
but after the PG delay time (tPG-DLY = 320 ms typ.). The PG
delay ensures that low PG pulse, showing “power fail state”,
is always longer than the tPG-DLY time and then could be
caught by the application circuit (for example by MCU).
R PG−MIN +
V CC−RPG
3.3 V
+
+ 3.3 kW (eq. 24)
I PG−MAX
1 mA
V CC−RPG
R PG
I RPG
BMTxxx
Application
V PG
PG
I PG
GND
PGI
I PGI
Note: I PG = I RPG when I PGI = 0mA
Figure 67. Circuit Example for RPG Value Selection
From the opposite side, RPG is limited to its maximum
value, based on: maximum PG leakage current
IPG−LK−MAX, maximum threshold voltage of the application
input VPGI−TH−MAX and maximum application input
leakage current IPGI−LK−MAX. Then:
R PG−MAX +
V CC−RPG * V PGI−TH−MAX
I PG−LK−MAX ) I PGI−LK−MAX
(eq. 25)
For example, when RPG is connected to 3.3 V power rail,
max. threshold voltage of the application input is 1.3 V and
application input leakage current is 3 mA max.:
RPG Value Selection
R PG−MAX +
As shown on the Figure 65 and Figure 66 in the time
region-4, the steepness of PG signal return to high level
depends on the RPG pull−up resistance (with relation to
capacitance of LDO’s PG output, parasitic capacitance of
PG signal PCB traces and the application circuit PGI input
capacitance. The lower RPG resistance the faster PG return
to high level.
At the most applications, the PG return speed to high level
is not a concern, mainly because of the fact that the LDO
already delays the PG return by the tPG-DLY time (320 ms
typ.) intentionally so the returning speed itself is negligible.
The next view to the RPG value is the power consumption
at “power fail state” when the current from the supply flows
+
V CC−RPG * V PGI−TH−MAX
I PG−LK−MAX ) I PGI−LK−MAX
(eq. 26)
3.3 V * 1.3 V
+ 500 kW
1 mA ) 3 mA
Based on results above, the RPG value could be selected
in range from 3.3 kW to 500 kW to fit the example
application.
Thermal Shutdown
When the LDO’s die temperature exceeds the thermal
shutdown threshold value the device is internally disabled.
The IC will remain in this state until the die temperature
decreases by the thermal shutdown hysteresis value. Once
www.onsemi.com
22
NCV8730
the IC temperature falls this way, the LDO is back enabled.
The thermal shutdown feature provides the protection
against overheating due to some application failure and it is
not intended to be used as a normal working function.
Where: (TJ − TA) is the temperature difference between the
junction and ambient temperatures and θJA is the thermal
resistance (dependent on the PCB as mentioned above).
For reliable operation junction temperature should be less
than +125°C.
The power dissipated by the LDO for given application
conditions can be calculated by the next equation:
Power Dissipation
Power dissipation caused by voltage drop across the LDO
and by the output current flowing through the device needs
to be dissipated out from the chip. The maximum power
dissipation is dependent on the PCB layout, number of used
Cu layers, Cu layers thickness and the ambient temperature.
The maximum power dissipation can be computed by
following equation:
P D(MAX) +
TJ * TA
125 * T A
+
[W]
q JA
q JA
P D + V IN @ I GND ) ǒV IN * V OUTǓ @ I OUT [W] (eq. 28)
Where: IGND is the LDO’s ground current, dependent on the
output load current.
Connecting the exposed pad and NC pin to a large ground
planes helps to dissipate the heat from the chip.
The relation of θJA and PD(MAX) to PCB copper area and
Cu layer thickness could be seen on the Figures 68 and 69.
(eq. 27)
Figure 68. qJA and PD(MAX) vs. Copper Area
Figure 69. qJA and PD(MAX) vs. Copper Area
Figure 70. Maximum Output Current vs. Input
Voltage
Figure 71. Maximum Output Current vs. Input
Voltage
www.onsemi.com
23
NCV8730
PCB Layout Recommendations
Besides the LDO application circuit, each demo board
includes some supporting staff, the same at all boards:
• Positions for optional through hole SMB connectors at
IN, OUT and EN pins (Molex 73100−0258 or
compatible) mainly for line/load transients, PSRR,
noise and startup testing the demo board includes.
• Edge connector where all these signal leads too (the
appropriate receptacle type is SAMTEC
MECF−20−01−L−DV−WT).
• Thermal management circuit (heating transistor and
diodes as temperature sensors).
To obtain good LDO’s stability, transient performance
and good regulation characteristics place CIN and COUT
capacitors as close as possible to the device pins and make
the PCB traces wide, short and place capacitors to the same
layer as the LDO is (to avoid connection through vias). The
same rules should be applied to the connections between
COUT and the load – the less parasitic impedance the better
transients and regulation at the point of load.
To minimize the solution size, use 0402 or 0201 capacitor
sizes with appropriate effective capacitance in mind.
Regarding high impedance ADJ pin, prevent capacitive
coupling of the trace to any switching signals in the circuitry.
Adequate input power filtering is always a good practice.
For load transients the input capacitor value must be high
enough to cover the current demands especially if the power
source is connected by long traces/wires with high
impedance.
Demo Boards
Below are the main part of the schematics and top/bottom
board layout pictures of the NCV8730 demo boards for
various packages. These boards have been used during
evaluation to capture the data shown in this datasheet like:
transients, PSRR, startups etc. At some of these pictures are
shown details of PCB traces surrounding the LDO including
CIN, COUT, resistor divider R1/R2, feed forward capacitor
CFF and IN/OUT−FORCE/SENSE connections.
Generally, when testing LDOs dynamic performance on
demo board which is connected to laboratory power supply
typically by long cables, the device needs additional input
capacitor. This capacitor covers the voltage drop generated
by the load current transients at the impedance of long
connection cables (note this is very different to normal
application where the distance of the LDO to its power
source is short).
Figure 72. Edge Connector Pinout (All Demo Boards)
Figure 73. Thermal Circuit (All Demo Boards)
www.onsemi.com
24
NCV8730
NCV8730ASN/BSN (TSOP−5 package) Demo Board (2 layer PCB, rev. 1)
Figure 74. TSOP−5 Demo Board (2 layer, rev. 1) – Schematics (Main Part)
Figure 76. TSOP−5 Demo Board (2 layer, rev. 1) –
PCB Bottom Layer
Figure 75. NCV8730 Demo Board (2 layer, rev. 1) –
PCB Top Layer
Figure 77. TSOP−5 Demo Board (2 layer, rev. 1) – PCB Top Layer, Zoomed, Added Signal Labels
www.onsemi.com
25
NCV8730
NCV8730AMT/BMT (WDFN−6 2x2 package) Demo Board (2 layer PCB, rev. 1)
Figure 78. WDFN−6 2x2 Demo Board (2 layer, rev. 1) – Schematics (Main Part)
Figure 79. WDFN−6 2x2 Demo Board (2 layer, rev. 1) –
PCB Top Layer
Figure 80. WDFN−6 2x2 Demo Board (2 layer, rev. 1) –
PCB Bottom Layer
Figure 81. WDFN−6 2x2 Demo Board (2 layer, rev. 1) – PCB Top Layer, Zoomed, Added Signal Labels
www.onsemi.com
26
NCV8730
ORDERING INFORMATION
Part Number
Marking
Voltage Option (VOUT−NOM)
NCV8730ASNADJT1G
PA2
ADJ
NCV8730ASN180T1G
PAH
1.8 V
NCV8730ASN330T1G
PAE
3.3 V
NCV8730ASN500T1G
PAG
5.0 V
NCV8730BMTWADJTBG
Q2
ADJ
NCV8730BMTW330TBG
QF
3.3 V
NCV8730BMTW500TBG
QG
5.0 V
NCV8730BMTW1500TBG
QH
15.0 V
Version
Package
Shipping
Without PG
TSOP−5
(Pb−Free)
3000 / Tape & Reel
With PG
WDFNW6
2x2
(Pb−Free)
3000 / Tape & Reel
NOTE: To order any other package, voltage version or PG / non PG variant, please contact your ON Semiconductor representative.
www.onsemi.com
27
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
5
1
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
D 5X
NOTE 5
2X
DATE 12 AUG 2020
0.20 C A B
0.10 T
M
2X
0.20 T
5
B
1
4
2
B
S
3
K
DETAIL Z
G
A
A
TOP VIEW
DIM
A
B
C
D
G
H
J
K
M
S
DETAIL Z
J
C
0.05
H
C
SIDE VIEW
SEATING
PLANE
END VIEW
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
0.95
0.037
MILLIMETERS
MIN
MAX
2.85
3.15
1.35
1.65
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
0_
10 _
2.50
3.00
1.9
0.074
5
5
XXXAYWG
G
1
1
Analog
2.4
0.094
XXX = Specific Device Code
A
= Assembly Location
Y
= Year
W = Work Week
G
= Pb−Free Package
1.0
0.039
XXX MG
G
Discrete/Logic
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ARB18753C
TSOP−5
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFNW6 2x2, 0.65P
CASE 511DW
ISSUE B
DATE 15 JUN 2018
SCALE 4:1
GENERIC
MARKING DIAGRAM*
XXMG
G
M
G
= Month Code
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON79327G
WDFNW6 2x2, 0.65P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
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