LDO Regulator, 100 mA,
18V, 1 mA IQ, with PG
NCV8711
The NCV8711 device is based on unique combination of features −
very low quiescent current, fast transient response and high input and
output voltage ranges. The NCV8711 is CMOS LDO regulator
designed for up to 18 V input voltage and 100 mA output current.
Quiescent current of only 1 mA makes this device ideal solution for
battery− powered, always−on systems. Several fixed output voltage
versions are available as well as the adjustable version.
The device (version B) implements power good circuit (PG) which
indicates that output voltage is in regulation. This signal could be used
for power sequencing or as a microcontroller reset.
Internal short circuit and over temperature protections saves the
device against overload conditions.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Operating Input Voltage Range: 2.7 V to 18 V
Output Voltage: 1.2 V to 17 V
Capable of Sourcing 140 mA Peak Output Current
Very Low Quiescent Current: 1 mA typ.
Low Dropout: 215 mV typ. at 100 mA
Output Voltage Accuracy ±1%
Power Good Output (Version B)
Stable with Small 1 mF Ceramic Capacitors
Built−in Soft Start Circuit to Suppress Inrush Current
Over−Current and Thermal Shutdown Protections
Available in Small TSOP−5 and WDFNW6 (2x2) Packages
These Devices are Pb−Free and are RoHS Compliant
Typical Applications
•
•
•
•
Body Control Modules
LED Lighting
On Board Charger
General Purpose Automotive
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MARKING DIAGRAMS
5
TSOP−5
CASE 483
SN SUFFIX
5
1
XXXAYWG
G
1
XXX = Specific Device Code
A
= Assembly Location
Y
= Year
W = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
WDFNW6 (2x2)
CASE 511DW
MTW SUFFIX
1
XX M
XX = Specific Device Code
M = Date Code
PIN ASSIGNMENTS
TSOP−5
IN
1
GND
2
EN
3
5
OUT
4
NC/ADJ/PG
CASE 483
WDFNW6 (2x2)
6 IN
OUT 1
NC/ADJ 2
GND 3
EP
5 NC/PG
4 EN
CASE511DW
(Top Views)
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
© Semiconductor Components Industries, LLC, 2020
September, 2020 − Rev. 2
1
Publication Order Number:
NCV8711/D
NCV8711
TYPICAL APPLICATION SCHEMATICS
VIN=6−18V
IN
C IN
1mF
ON
OUT
NCV8711A 5.0V
TSOP−5 / WDFN−6
EN
OFF
GND
VIN=6−18V
VOUT=5.0V
COUT
1mF
C IN
1mF
IN
C IN
1mF
NCV8711B 5.0V
TSOP−5 / WDFN−6
NC
EN
OFF
GND
VOUT=5V
OUT
NCV8711A ADJ
TSOP−5 / WDFN−6
EN
ADJ
GND
R1
2M4
PG
R PG
100k
COUT
1mF
R2
750k
Figure 2. Adjustable Output Voltage Application (No PG)
VIN=6−18V
VOUT=5.0V
C OUT
1mF
C FF
1nF
1.2V
OFF
OUT
ON
ON
NC
Figure 1. Fixed Output Voltage Application (No PG)
VIN=6−18V
IN
IN
C IN
1mF
ON
NCV8711B ADJ
Only WDFN−6
1.2V
ADJ
EN
PG
VOUT=5V
OUT
GND
PG
OFF
R1
2M4
C FF
1nF
R2
750k
COUT
1mF
R PG
100k
PG
Figure 3. Fixed Output Voltage Application with PG
Figure 4. Adjustable Output Voltage Application with PG
ǒ
V OUT + V ADJ @ 1 )
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2
Ǔ
R1
) I ADJ @ R 1
R2
NCV8711
SIMPLIFIED BLOCK DIAGRAMS
IN
OUT
Current limit
UVLO Comparator
UVLO
I EN−PU = 300nA
1.95 V
V CCEN
V−REFERENCE
AND SOFT−START
V REF
1.2V
EA
RADJ1
V FB =1.2V
EN
ADJ
Enable
RADJ2
EN Comparator
GND
THERMAL
SHUTDOWN
0.9 V
PG
PG Comparator
DEGLITCH
DELAY TMR
93% of V REF
NC
Note: Blue objects are valid for ADJ version
Green objects are valid for FIX version
Brown objects are valid for B version (with PG)
Figure 5. Internal Block Diagram
PIN DESCRIPTION
Pin No. TSOP−5 Pin No. WDFNW6
Pin Name
Description
1
6
IN
Power supply input pin.
2
3
GND
Ground pin.
5
1
OUT
LDO output pin.
3
4
EN
Enable input pin (high − enabled, low − disabled). If this pin is connected to IN pin
or if it is left unconnected (pull−up resistor is not required) the device is enabled.
4 (Note 1)
2
ADJ
Adjust input pin. Connect it to the output resistor divider or directly to the OUT pin.
4 (Note 1)
5
PG
Power good output pin. Could be left unconnected or could be connected to GND
if not needed. High level for power ok, low level for fail.
4 (Note 1)
2, 5
NC
Not internally connected. This pin can be tied to the ground plane to improve
thermal dissipation.
NA
EP
EPAD
Connect the exposed pad to GND.
1. Pin function depends on device version.
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3
NCV8711
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VIN
−0.3 to 22
V
VOUT Voltage
VOUT
−0.3 to [(VIN + 0.3) or 22 V; whichever is lower]
V
EN Voltage
VEN
−0.3 to (VIN + 0.3)
V
ADJ Voltage
VFB/ADJ
−0.3 to 5.5
V
PG Voltage
VPG
−0.3 to (VIN + 0.3)
V
Output Current
IOUT
Internally limited
mA
PG Current
IPG
3
mA
TJ(MAX)
150
°C
TSTG
−55 to 150
°C
ESD Capability, Human Body Model (Note 3)
ESDHBM
2000
V
ESD Capability, Charged Device Model (Note 3)
ESDCDM
1000
V
VIN Voltage (Note 2)
Maximum Junction Temperature
Storage Temperature
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per ANSI/ESDA/JEDEC JS−001, EIA/JESD22−A114 (AEC−Q100−002)
ESD Charged Device Model tested per ANSI/ESDA/JEDEC JS−002, EIA/JESD22−C101 (AEC−Q100−011D)
THERMAL CHARACTERISTICS (Note 4)
Characteristic
Symbol
WDFNW6 2x2
TSOP−5
Unit
RthJA
63
147
°C/W
Thermal Resistance, Junction−to−Case (top)
RthJCt
204
82
°C/W
Thermal Resistance, Junction−to−Case (bottom)
RthJCb
15
N/A
°C/W
Thermal Resistance, Junction−to−Board (top)
RthJBt
47
113
°C/W
Thermal Characterization Parameter, Junction−to−Case (top)
PsiJCt
4
22
°C/W
Thermal Characterization Parameter, Junction−to−Board [FEM]
PsiJB
46
113
°C/W
Thermal Resistance, Junction−to−Air
4. Measured according to JEDEC board specification (board 1S2P, Cu
of the board can be found in JESD51−7.
layer thickness 1 oz, Cu area 650 mm2,
no airflow). Detailed description
ELECTRICAL CHARACTERISTICS (VIN = VOUT−NOM + 1 V and VIN ≥ 2.7 V, VEN = 1.2 V, IOUT = 1 mA, CIN = COUT = 1.0 mF
(effective capacitance – Note 5), TJ = −40°C to 125°C, ADJ tied to OUT, unless otherwise specified) (Note 6)
Parameter
Test Conditions
Recommended Input Voltage
Output Voltage Accuracy
TJ = −40°C to +85°C
Symbol
Min
Typ
Max
Unit
VIN
2.7
−
18
V
VOUT
−1
−
1
%
−1
−
2
TJ = −40°C to +125°C
ADJ Reference Voltage
ADJ version only
VADJ
−
1.2
−
V
ADJ Input Current
VADJ = 1.2 V
IADJ
−0.1
0.01
0.1
mA
Line Regulation
VIN = VOUT−NOM + 1 V to 18 V and VIN ≥ 2.7 V
DVO(DVI)
−
−
0.2
%VOUT
Load Regulation
IOUT = 0.1 mA to 100 mA
DVO(DIO)
−
−
0.4
%VOUT
Quiescent Current (version A)
VIN = VOUT−NOM + 1 V to 18 V, IOUT = 0 mA
IQ
−
1.3
2.5
mA
Quiescent Current (version B)
VIN = VOUT−NOM + 1 V to 18 V, IOUT = 0 mA
−
1.8
3.0
Ground Current
IOUT = 100 mA
IGND
−
325
450
mA
Shutdown Current (Note 10)
VEN = 0 V, IOUT = 0 mA, VIN = 18 V
ISHDN
−
0.35
1.5
mA
Output Current Limit
VOUT = VOUT−NOM − 100 mV
IOLIM
140
250
450
mA
Short Circuit Current
VOUT = 0 V
IOSC
140
250
450
mA
Dropout Voltage (Note 7)
IOUT = 100 mA
VDO
−
215
355
mV
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4
NCV8711
ELECTRICAL CHARACTERISTICS (VIN = VOUT−NOM + 1 V and VIN ≥ 2.7 V, VEN = 1.2 V, IOUT = 1 mA, CIN = COUT = 1.0 mF
(effective capacitance – Note 5), TJ = −40°C to 125°C, ADJ tied to OUT, unless otherwise specified) (Note 6) (continued)
Parameter
Power Supply Ripple Rejection
Test Conditions
VIN = VOUT−NOM + 2 V
IOUT = 10 mA
Symbol
Min
Typ
Max
Unit
PSRR
−
80
−
dB
10 kHz
−
70
−
100 kHz
−
42
−
1 MHz
−
48
−
VN
−
240
−
mVRMS
V
10 Hz
Output Noise
f = 10 Hz to 100 kHz, VOUT−NOM = 5.0 V
EN Threshold
VEN rising
VEN−TH
0.7
0.9
1.05
EN Hysteresis
VEN falling
VEN−HY
0.01
0.1
0.2
V
EN Internal Pull−up Current
VEN = 1 V, VIN = 5.5 V
IEN−PU
0.01
0.3
1
mA
EN Input Leakage Current
VEN = 18 V, VIN = 18 V
IEN−LK
−1
0.05
1
mA
Start−up time (Note 8)
VOUT−NOM ≤ 3.3 V
tSTART
100
250
500
ms
300
600
1000
VOUT−NOM > 3.3 V
Internal UVLO Threshold
Ramp VIN up until output is turned on
VIUL−TH
1.6
1.95
2.6
V
Internal UVLO Hysteresis
Ramp VIN down until output is turned off
VIUL−HY
0.05
0.2
0.3
V
PG Threshold (Note 9)
VOUT falling
VPG−TH
90
93
96
%
PG Hysteresis (Note 9)
VOUT rising
VPG−HY
0.1
2
4
%
PG Deglitch Time (Note 9)
tPG−DG
75
160
270
ms
PG Delay Time (Note 9)
tPG−DLY
120
320
600
ms
PG Output Low Level Voltage (Note 9) IPG = 1 mA
VPG−OL
−
0.2
0.4
V
PG Output Leakage Current (Note 9)
VPG = 18 V
IPG−LK
−
0.01
1
mA
Thermal Shutdown Temperature
Temperature rising from TJ = +25°C
TSD
−
165
−
°C
Thermal Shutdown Hysteresis
Temperature falling from TSD
TSDH
−
20
−
°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Effective capacitance, including the effect of DC bias, tolerance and temperature. See the Application Information section for more
information.
6. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at TA = 25°C.
Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.
7. Dropout measured when the output voltage falls 100 mV below the nominal output voltage. Limits are valid for all voltage versions.
8. Startup time is the time from EN assertion to point when output voltage is equal to 95% of VOUT−NOM.
9. Applicable only to version B (device option with power good output). PG threshold and PG hysteresis are expressed in percentage of nominal
output voltage.
10. Shutdown current includes EN Internal Pull−up Current.
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5
NCV8711
TYPICAL CHARACTERISTICS
VIN = VOUT−NOM + 1 V and VIN ≥ 2.7 V, VEN = 1.2 V, IOUT = 1 mA, COUT = 1.0 mF, ADJ tied to OUT, TJ = 25°C, unless otherwise specified
VIN = (VOUT-NOM+ 1 V) to 18 V, VIN ≥ 2.7 V
IOUT = 1 to 100 mA
(V)
1.5%
High limit
2.3
1.0%
OUT
OUTPUT VOLTAGE, V
2.5
High limit
QUIESCENT CURRENT, IQ (mA)
2.0%
VOUT-NOM= 15 V
0.5%
VOUT-NOM= 5 V
0.0%
VOUT-NOM= 1.2 V
-0.5%
Low limit
-1.0%
-1.5%
1.9
1.7
1.5
Version-A
(non PG)
1.3
1.1
VIN = 18 V
IOUT= 0 mA
0.9
-2.0%
-40
-20
0
20
40
60
80
100
JUNCTION TEMPERATURE, TJ ( °C)
0.7
-40
120
Figure 6. Output Voltage vs. Temperature
-20
0
20
40
60
80
JUNCTION TEMPERATURE, TJ ( °C)
100
120
Figure 7. Quiescent Current vs. Temperature
1.6
1.10
ENABLE THRESHOLD VOLTAGE, VEN -TH (V)
High limit
1.4
SHUTDOWN CURRENT, I SHDN ( μA)
Version-B
(with PG)
2.1
Note:
Shutdown current is measured at IN pin
and includes EN pin pull-up current.
1.2
1.0
0.8
0.6
0.4
VIN = 18 V
VEN = 0 V
0.2
0.0
-40
-20
0
20
40
60
80
100
1.05
High limit
1.00
0.95
0.90
0.85
0.80
0.75
Low limit
0.70
0.65
0.60
-40
120
-20
JUNCTION TEMPERATURE, T J ( °C)
0
20
40
60
80
100
120
JUNCTION TEMPERATURE, TJ (°C)
Figure 8. Shutdown Current vs. Temperature
Figure 9. Enable Threshold Voltage vs.
Temperature
0.10
1.4
1.2
ADJ INPUT CURRENT, I ADJ (μA)
ENABLE PULL - UP CURRENT, I EN-PU ( μA)
1.6
High limit
1.0
0.8
0.6
0.4
0.2
High limit
0.08
0.06
0.04
0.02
VEN = 1 V
0.0
-40
-20
0
20
40
60
80
100
0.00
-40
120
TEMPERATURE (°C)
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 10. Enable Internal Pull−Up Current vs.
Temperature
Figure 11. ADJ Input Current vs. Temperature
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6
NCV8711
TYPICAL CHARACTERISTICS
VIN = VOUT−NOM + 1 V and VIN ≥ 2.7 V, VEN = 1.2 V, IOUT = 1 mA, COUT = 1.0 mF, ADJ tied to OUT, TJ = 25°C, unless otherwise specified
400
High limit
DROPOUT VOLTAGE, V DROP (mV)
350
300
VOUT = VOUT-NOM - 100 mV
IOUT = 100 mA
All output voltage versions
250
200
150
100
50
0
-40
-20
0
20
40
60
80
100
JUNCTION TEMPERATURE, TJ ( °C)
Figure 12. Dropout Voltage vs. Temperature
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7
120
NCV8711
TYPICAL CHARACTERISTICS
VIN = VOUT−NOM + 1 V and VIN ≥ 2.7 V, VEN = 1.2 V, IOUT = 1 mA, COUT = 1.0 mF, ADJ tied to OUT, TJ = 25°C, unless otherwise specified
Figure 14. PSRR − FIX−3.3 V, VIN = 4.3 V, IOUT =
100 mA
Figure 13. PSRR − FIX−3.3 V, COUT = 1 mF,
IOUT = 100 mA
Figure 15. PSRR − FIX−3.3 V, VIN = 8.3 V, IOUT =
100 mA
Figure 16. Noise – FIX − 5.0 V, IOUT = 10 mA,
Different COUT
Figure 17. Noise – ADJ−set−5.0 V with
Different CFF and FIX − 5.0 V
Figure 18. Noise – FIX, IOUT = 10 mA,
COUT = 1 mF, Different VOUT
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8
NCV8711
ORDERING INFORMATION
Part Number
Marking
Voltage Option (VOUT−NOM)
NCV8711ASNADJT1G
GGA
ADJ
NCV8711ASN300T1G
GGC
3.0 V
NCV8711ASN330T1G
GGD
3.3 V
NCV8711ASN500T1G
GGE
5.0 V
NCV8711BMTWADJTBG
GA
ADJ
NCV8711BMTW300TBG
GC
3.0 V
NCV8711BMTW330TBG
GD
3.3 V
NCV8711BMTW500TBG
GE
5.0 V
Version
Package
Shipping
Without PG
TSOP−5
(Pb−Free)
3000 / Tape & Reel
With PG
WDFNW6
(Pb−Free)
3000 / Tape & Reel
NOTE: To order other package, voltage version or PG / non PG variant, please contact your ON Semiconductor sales representative.
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
5
1
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
D 5X
NOTE 5
2X
DATE 12 AUG 2020
0.20 C A B
0.10 T
M
2X
0.20 T
5
B
1
4
2
B
S
3
K
DETAIL Z
G
A
A
TOP VIEW
DIM
A
B
C
D
G
H
J
K
M
S
DETAIL Z
J
C
0.05
H
C
SIDE VIEW
SEATING
PLANE
END VIEW
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
0.95
0.037
MILLIMETERS
MIN
MAX
2.85
3.15
1.35
1.65
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
0_
10 _
2.50
3.00
1.9
0.074
5
5
XXXAYWG
G
1
1
Analog
2.4
0.094
XXX = Specific Device Code
A
= Assembly Location
Y
= Year
W = Work Week
G
= Pb−Free Package
1.0
0.039
XXX MG
G
Discrete/Logic
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ARB18753C
TSOP−5
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFNW6 2x2, 0.65P
CASE 511DW
ISSUE B
DATE 15 JUN 2018
SCALE 4:1
GENERIC
MARKING DIAGRAM*
XXMG
G
M
G
= Month Code
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON79327G
WDFNW6 2x2, 0.65P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
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onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
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TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
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