NDD60N745U1-1G

NDD60N745U1 N-Channel Power MOSFET 600 V, 745 mW Features • 100% Avalanche Tested • These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS http://onsemi.com Compliant V(BR)DSS RDS(ON) MAX 600 V 745 mW @ 10 V ABSOLUTE MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Symbol Value Unit Drain−to−Source Voltage VDSS 600 V Gate−to−Source Voltage VGS ±25 V ID 6.6 A Continuous Drain Current RqJC Steady State Power Dissipation – RqJC Steady State TC = 25°C TC = 100°C 84 W IDM 27 A TJ, TSTG −55 to +150 °C IS 6.6 A Single Pulse Drain−to−Source Avalanche Energy (ID = 2.5 A) EAS 38 mJ Peak Diode Recovery (Note 1) dv/dt 15 V/ns TL 260 °C tp = 10 ms Operating Junction and Storage Temperature Source Current (Body Diode) Lead Temperature for Soldering Leads Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. ISD < 6.6 A, di/dt ≤ 400 A/ms, VDS peak ≤ V(BR)DSS, VDD = 80% V(BR)DSS THERMAL RESISTANCE Parameter Symbol Value Unit NDD60N745U1 RqJC 1.5 °C/W Junction−to−Ambient Steady State (Note 3) NDD60N745U1 (Note 2) NDD60N745U1−1 (Note 2) NDD60N745U1−35 RqJA Junction−to−Case (Drain) D (2) 4.2 PD Pulsed Drain Current TC = 25°C N−Channel MOSFET °C/W 47 98 95 G (1) S (3) 4 1 4 1 2 2 3 IPAK CASE 369D STYLE 2 3 DPAK CASE 369C STYLE 2 4 12 3 IPAK CASE 369AD STYLE 2 ORDERING INFORMATION See detailed ordering and shipping information on page 3 of this data sheet. 2. Insertion mounted 3. Surface mounted on FR4 board using 1″ sq. pad size (Cu area = 1.127 in sq [2 oz] including traces) © Semiconductor Components Industries, LLC, 2013 December, 2013 − Rev. 0 1 Publication Order Number: NDD60N745U1/D NDD60N745U1 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Test Conditions Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 1 mA 600 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Characteristic Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Leakage Current Gate−to−Source Leakage Current IDSS V 540 VDS = 600 V, VGS = 0 V IGSS mV/°C TJ = 25°C 1 TJ = 125°C 100 VGS = ±20 V ±100 mA nA ON CHARACTERISTICS (Note 4) VGS(TH) VDS = VGS, ID = 250 mA Negative Threshold Temperature Coefficient VGS(TH)/TJ Reference to 25°C, ID = 250 mA 7.6 Static Drain-to-Source On Resistance RDS(on) VGS = 10 V, ID = 3.25 A 610 gFS VDS = 15 V, ID = 3.25 A 5.6 S 440 pF Gate Threshold Voltage Forward Transconductance 2 3.2 4 V mV/°C 745 mW DYNAMIC CHARACTERISTICS Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Effective output capacitance, energy related (Note 6) Co(er) Effective output capacitance, time related (Note 7) Co(tr) VDS = 50 V, VGS = 0 V, f = 1 MHz 27 1.5 VGS = 0 V, VDS = 0 to 480 V ID = constant, VGS = 0 V, VDS = 0 to 480 V 21 71 nC Total Gate Charge Qg 15 Gate-to-Source Charge Qgs 2.9 Gate-to-Drain Charge Qgd Plateau Voltage VGP 5.3 V Gate Resistance Rg 4.4 W 8 ns VDS = 300 V, ID = 6.8 A, VGS = 10 V 7.3 RESISTIVE SWITCHING CHARACTERISTICS (Note 5) Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time td(on) tr td(off) VDD = 300 V, ID = 6.8 A, VGS = 10 V, RG = 0 W tf 10 19 7 SOURCE−DRAIN DIODE CHARACTERISTICS Diode Forward Voltage VSD Reverse Recovery Time trr Charge Time ta Discharge Time tb Reverse Recovery Charge Qrr IS = 6.6 A, VGS = 0 V TJ = 25°C 0.90 TJ = 100°C 0.82 260 VGS = 0 V, VDD = 30 V IS = 6.8 A, di/dt = 100 A/ms 1.6 V ns 130 130 2.1 mC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 5. Switching characteristics are independent of operating junction temperatures. 6. Co(er) is a fixed capacitance that gives the same stored energy as Coss while VDS is rising from 0 to 80% V(BR)DSS 7. Co(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% V(BR)DSS http://onsemi.com 2 NDD60N745U1 MARKING DIAGRAMS 4 Drain 4 Drain YWW 60N 745U1G YWW 60N 745U1G YWW 60N 745U1G 4 Drain 2 1 Drain 3 Gate Source 1 2 3 Gate Drain Source IPAK DPAK Y WW G 1 Gate 3 2 Source Drain IPAK = Year = Work Week = Pb−Free Package ORDERING INFORMATION Package Shipping† NDD60N745U1−1G IPAK (Pb-Free, Halogen-Free) 75 Units / Rail NDD60N745U1−35G IPAK (Pb-Free, Halogen-Free) 75 Units / Rali NDD60N745U1T4G DPAK (Pb-Free, Halogen-Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 3 NDD60N745U1 TYPICAL CHARACTERISTICS 12 ID, DRAIN CURRENT (A) 14 VGS = 10 V to 6.5 V VGS = 6.0 V 10 VGS = 5.5 V 8 6 VGS = 5.0 V 4 VGS = 4.5 V 2 VGS = 4.0 V 5 10 15 20 25 30 1.2 1.1 1.0 0.9 0.8 0.7 0.6 5 6 7 8 9 10 VGS, GATE VOLTAGE (V) Figure 3. On−Resistance vs. Gate−to−Source Voltage RDS(on), NORMALIZED DRAIN−TO− SOURCE RESISTANCE 2.6 ID = 3.25 A VGS = 10 V 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 −50 TJ = 150°C TJ = −55°C 2 3 4 6 5 8 7 9 10 12 14 Figure 2. Transfer Characteristics TJ = 25°C ID = 3.25 A 2.2 4 Figure 1. On−Region Characteristics 1.3 2.4 6 VGS, GATE−TO−SOURCE VOLTAGE (V) 1.4 4 8 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1.5 0.5 10 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 VDS = 15 V 2 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 BVDSS, NORMALIZED BREAKDOWN VOLTAGE RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 TJ = 25°C 12 ID, DRAIN CURRENT (A) 14 1.5 1.4 TJ = 25°C VGS = 10 V 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0 2 6 4 10 8 ID, DRAIN CURRENT (A) Figure 4. On−Resistance vs. Drain Current and Gate Voltage 1.125 1.100 ID = 250 mA 1.075 1.050 1.025 1.000 0.975 0.950 0.925 −50 Figure 5. On−Resistance Variation with Temperature −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) Figure 6. Breakdown Voltage Variation with Temperature http://onsemi.com 4 150 NDD60N745U1 10,000 1.15 1.10 ID = 250 mA IDSS, LEAKAGE (nA) 1.00 0.95 0.90 0.85 0.80 1000 TJ = 125°C 100 TJ = 100°C 10 0.75 −25 0 25 50 75 100 VGS = 0 V TJ = 25°C f = 1 MHz 10 1 10 100 12 400 500 600 300 10 9 8 7 1000 350 QT 11 VDS 200 QGD 150 4 3 2 1 0 250 VGS QGS 6 5 100 VDS = 300 V TJ = 25°C ID = 6.8 A 0 2 4 6 8 10 12 50 0 16 14 VDS, DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC) Figure 9. Capacitance Variation Figure 10. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge 100 1000 VGS = 10 V VDD = 300 V ID = 6.8 A TJ = 100°C IS, SOURCE CURRENT (A) t, TIME (ns) 300 Figure 8. Drain−to−Source Leakage Current vs. Voltage 100 td(off) 100 tr tf 10 1 200 Figure 7. Threshold Voltage Variation with Temperature CISS 0.1 100 VDS, DRAIN−TO−SOURCE VOLTAGE (V) CRSS 1 0 TJ, JUNCTION TEMPERATURE (°C) COSS 1000 1 150 125 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.70 −50 10,000 C, CAPACITANCE (pF) TJ = 150°C 1.05 VGS, GATE−TO−SOURCE VOLTAGE (V) VGS(th), NORMALIZED THRESHOLD VOLTAGE TYPICAL CHARACTERISTICS td(on) 1 10 TJ = 125°C 10 TJ = 150°C 1 0.1 100 TJ = 25°C TJ = −55°C 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 11. Resistive Switching Time Variation vs. Gate Resistance Figure 12. Diode Forward Voltage vs. Current http://onsemi.com 5 NDD60N745U1 TYPICAL CHARACTERISTICS ID, DRAIN CURRENT (A) 100 VGS ≤ 25 V Single Pulse TC = 25°C 10 10 ms 1 100 ms 0.1 1 ms 10 ms dc 0.01 RDS(on) Limit Thermal Limit Package Limit 0.1 1 10 100 1000 R(t), EFFECTIVE TRANSIENT THERMAL RESPONSE (°C/W) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 13. Maximum Rated Forward Biased Safe Operating Area 10 RqJC steady state = 1.5°C/W 1 Duty Cycle = 0.5 0.20 0.10 0.1 0.05 0.02 0.01 0.01 Single Pulse 1E−06 1E−05 1E−04 1E−03 1E−02 1E−01 1E+00 t, TIME (s) Figure 14. Thermal Impedance (Junction−to−Case) http://onsemi.com 6 1E+01 1E+02 1E+03 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS IPAK CASE 369D−01 ISSUE C SCALE 1:1 C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F D G DATE 15 DEC 2010 H 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− T MARKING DIAGRAMS STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE Discrete YWW xxxxxxxx STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR xxxxxxxxx A lL Y WW DOCUMENT NUMBER: DESCRIPTION: 98AON10528D Integrated Circuits xxxxx ALYWW x = Device Code = Assembly Location = Wafer Lot = Year = Work Week Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. IPAK (DPAK INSERTION MOUNT) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS 3.5 MM IPAK, STRAIGHT LEAD CASE 369AD ISSUE B DATE 18 APR 2013 SCALE 1:1 E E3 L2 E2 A1 D2 D L1 L T SEATING PLANE NOTES: 1.. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2.. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD GATE OR MOLD FLASH. A A1 b1 2X e A2 3X E2 b 0.13 M T D2 DIM A A1 A2 b b1 D D2 E E2 E3 e L L1 L2 MILLIMETERS MIN MAX 2.19 2.38 0.46 0.60 0.87 1.10 0.69 0.89 0.77 1.10 5.97 6.22 4.80 −−− 6.35 6.73 4.57 5.45 4.45 5.46 2.28 BSC 3.40 3.60 −−− 2.10 0.89 1.27 GENERIC MARKING DIAGRAMS* OPTIONAL CONSTRUCTION STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR Discrete AYWW XXX XXXXXG XXXXXX A L Y WW G Integrated Circuits XXXXXXG ALYWW = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DOCUMENT NUMBER: DESCRIPTION: 98AON23319D Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 3.5 MM IPAK, STRAIGHT LEAD PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F 4 1 2 DATE 21 JUL 2015 3 SCALE 1:1 A E b3 C A B c2 4 L3 Z D 1 L4 2 3 NOTE 7 b2 e c SIDE VIEW b 0.005 (0.13) TOP VIEW H DETAIL A M BOTTOM VIEW C Z H L2 GAUGE PLANE C L L1 DETAIL A Z SEATING PLANE BOTTOM VIEW A1 ALTERNATE CONSTRUCTIONS ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW AYWW XXX XXXXXG IC Discrete = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 6.17 0.243 SCALE 3:1 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z XXXXXX A L Y WW G 3.00 0.118 1.60 0.063 STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON10527D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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