NDT454P

NDT454P P-Channel Enhancement Mode Field Effect Transistor General Description Features Power SOT P-Channel enhancement mode power field effect transistors are produced using ON Semiconductor's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. -5.9A, -30V. RDS(ON) = 0.05Ω @ VGS = -10V RDS(ON) = 0.07Ω @ VGS = -6V RDS(ON) = 0.09Ω @ VGS = -4.5V. High density cell design for extremely low RDS(ON). High power and current handling capability in a widely used surface mount package. ____________________________________________________________________________________________ D G Absolute Maximum Ratings Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage ID Drain Current - Continuous D D S (Note 1a) Maximum Power Dissipation NDT454P Units -30 V ±20 V ±5.9 A ±15 (Note 1a) 3 (Note 1b) 1.3 (Note 1c) TJ,TSTG S T A = 25°C unless otherwise noted - Pulsed PD G Operating and Storage Temperature Range W 1.1 -65 to 150 °C THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W * Order option J23Z for cropped center drain lead. © 1997 Semiconductor Components Industries, LLC. September-2017, Rev. 4 Publication Order Number: NDT454P/D Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min -30 Typ Max Units -1 µA OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA IDSS Zero Gate Voltage Drain Current VDS = -24 V, VGS = 0 V -5 µA IGSSF Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V -100 nA VDS = -15 V, VGS = 0 V V TJ = 70°C ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 µA RDS(ON) Static Drain-Source On-Resistance VGS = -10 V, ID = -5.9 A 0.038 0.05 VGS = -6 V, ID = -5.2 A 0.046 0.07 VGS = -4.5 V, ID = -4.6 A 0.064 0.09 ID(on) gFS On-State Drain Current Forward Transconductance -1 VGS = -10 V, VDS = -5 V -15 VGS = -4.5, VDS = -5V -5 -2.7 V Ω A VDS = 15 V, ID = 5.9 A 10 S VDS = 15 V, VGS = 0 V, f = 1.0 MHz 950 pF 610 pF 220 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn - On Delay Time tr Turn - On Rise Time tD(off) Turn - Off Delay Time tf Turn - Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = -15 V, ID = -1 A, VGEN = -10 V, RGEN = 6 Ω VDS = -15 V, ID = -5.9 A, VGS = -10 V 10 30 ns 18 60 ns 80 120 ns 45 100 ns 29 40 nC 3 11 www.onsemi.com 2 Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units -1.9 A -1.3 V 100 ns DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = -5.9 A trr Reverse Recovery Time VGS = 0V, IF = -5.9 A, dIF/dt = 100 A/µs -0.85 (Note 2) Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. P D(t ) = T J −TA R θJA(t ) = T J −TA R θJC+RθCA(t ) = I 2D (t ) × RDS(ON ) TJ Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 42oC/W when mounted on a 1 in2 pad of 2oz copper. b. 95oC/W when mounted on a 0.066 in2 pad of 2oz copper. c. 110oC/W when mounted on a 0.0123 in2 pad of 2oz copper. 1a 1c 1b Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. www.onsemi.com 3 Typical Electrical Characteristics 3 -6.0 -25 -5.0 -4.5 RDS(on) , NORMALIZED I D , DRAIN-SOURCE CURRENT (A) VGS =-10V -4.0 -20 -15 -3.5 -10 -3.0 -5 DRAIN-SOURCE ON-RESISTANCE -30 0 V GS = -3.5V 2.5 -4.0V 2 -4.5V -5.0V 1.5 -6.0V -10V 1 0.5 0 -1 -2 -3 -4 V DS , DRAIN-SOURCE VOLTAGE (V) 0 -5 Figure 1. On-Region Characteristics. -16 -20 2 1.4 R DS(on) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE I D = -5.9A VGS = -10V 1.2 1 0.8 0.6 -50 V GS = -10V TJ = 125°C 1.5 25°C 1 -55°C 0.5 -25 0 25 50 75 100 125 150 0 -5 TJ , JUNCTION TEMPERATURE (°C) -10 I D , DRAIN CURRENT (A) -15 -20 Figure 4. On-Resistance Variation with Drain Current and Temperature. Figure 3. On-Resistance Variation with Temperature. 1.2 V DS = -10V TJ = -55°C 25 125 V th , NORMALIZED -16 -12 -8 -4 0 -1 -2 -3 -4 -VGS , GATE TO SOURCE VOLTAGE (V) -5 GATE-SOURCE THRESHOLD VOLTAGE -20 -ID , DRAIN CURRENT (A) -8 -12 I D , DRAIN CURRENT (A) Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.6 RDS(ON) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE -4 V DS = V GS 1.1 I D = -250µA 1 0.9 0.8 0.7 0.6 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) Figure 6. Gate Threshold Variation with Temperature. Figure 5. Transfer Characteristics. www.onsemi.com 4 125 150 Typical Electrical Characteristics (continued) 20 I D = -250µA 10 -I S , REVERSE DRAIN CURRENT (A) BV DSS , NORMALIZED DRAIN-SOURCE BREAKDOWN VOLTAGE 1.1 1.08 1.06 1.04 1.02 1 0.98 0.96 0.94 -50 VGS = 0V 5 1 TJ = 125°C 25°C -55°C 0.1 0.01 0.001 -25 0 25 TJ 50 75 100 125 150 0 I D = -5.9A , GATE-SOURCE VOLTAGE (V) C iss 1000 C oss 500 300 C rss f = 1 MHz GS CAPACITANCE (pF) 1.2 1.5 10 2000 V DS = -10V -15V 8 -20V 6 4 2 -V VGS = 0 V 0 0.3 1 3 10 30 0 10 -VDS , DRAIN TO SOURCE VOLTAGE (V) 30 40 Figure 10. Gate Charge Characteristics. -VDD ton t d(on) t off tr RL V IN 20 Q g , GATE CHARGE (nC) Figure 9. Capacitance Characteristics. t d(off) tf 90% 90% V OUT D VGS 0.9 Figure 8. Body Diode Forward Voltage Variation with Source Current and Temperature. 3000 100 0.1 0.6 -VSD , BODY DIODE FORWARD VOLTAGE (V) Figure 7. Breakdown Voltage Variation with Temperature. 200 0.3 , JUNCTION TEMPERATURE (°C) VOUT R GEN 10% 10% DUT G 90% S V IN 50% 50% 10% PULSE WIDTH Figure 11. Switching Test Circuit. Figure 12. Switching Waveforms. www.onsemi.com 5 INVERTED 3.5 20 V DS = -15V STEADY-STATE POWER DISSIPATION (W) g FS, TRANSCONDUCTANCE (SIEMENS) Typical Electrical and ThermalCharacteristics (continued) T J = -55°C 16 25°C 12 125°C 8 4 0 0 -5 -10 -15 1a 3 2.5 2 1.5 1b 1c 1 4.5"x5" FR-4 Board o TA = 2 5 C Still Air 0.5 0 -20 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) I D , DRAIN CURRENT (A) Figure 14. SOT-223 Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area. Figure 13. Transconductance Variation with Drain Current and Temperature. 7 30 10 1a 6 -I D, DRAIN CURRENT (A) I D , STEADY-STATE DRAIN CURRENT (A) 1 5 1b 4 1c 4.5"x5" FR-4 Board 3 3 RD S(O 10 0u 1m s s IT 10 10 0.3 1s 10 s DC VGS = -10V 0.1 ms 0m s SINGLE PULSE R 0.03 Still Air LIM 1 o TA = 2 5 C N) θJ A = See Note 1c T A = 25°C VG S = - 1 0 V 2 0 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) Figure 15. Maximum Steady-State Drain Current versus Copper Mounting Pad Area. 1 0.01 0.1 0.2 0.5 1 2 5 10 30 50 - VDS , DRAIN-SOURCE VOLTAGE (V) Figure 16. Maximum Safe Operating Area. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 0.5 D = 0.5 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 R JA (t) = r(t) * R JA θ θ R JA = See Note 1 c θ P(pk) 0.01 t1 0.005 (t) θJA Duty Cycle, D = t 1 / t 2 Single Pulse 0.002 0.001 0.0001 t2 TJ - TA = P * R 0.001 0.01 0.1 t 1 , TIME (sec) 1 10 Figure 15. Transient Thermal Response Curve. Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design. www.onsemi.com 6 100 300 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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