Intelligent Power Module
(IPM), 650 V, 50 A
NFAM5065L4B
General Description
The NFAM5065L4B is a fully-integrated inverter power module
consisting of an independent High side gate driver, LVIC, six IGBT’s
and a temperature sensor (VTS), suitable for driving permanent
magnet synchronous (PMSM) motors, brushless DC (BLDC) motors
and AC asynchronous motors. The IGBT’s are configured in
a three-phase bridge with separate emitter connections for the lower
legs for maximum flexibility in the choice of control algorithm.
The power stage has under voltage lockout protection (UVP).
Internal boost diodes are provided for high side gate boost drive.
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Features
•
•
•
•
•
•
•
•
Three-phase 650 V, 50 A IGBT Module with Independent Drivers
Active Logic Interface
Built-in Undervoltage Protection (UVP)
Integrated Bootstrap Diodes and Resistors
Separate Low-side IGBT Emitter Connections for Individual
Current Sensing of Each Phase
Temperature Sensor (VTS)
UL1557 Certified (File No.339285)
This Device is Pb−Free and RoHS Compliant
DIP39, 54.5x31.0 EP−2
CASE MODGX
MARKING DIAGRAM
Typical Applications
•
•
•
•
NFAM5065L4B
ZZZATYWW
Industrial Drives
Industrial Pumps
Industrial Fans
Industrial Automation
Device marking is on package top side
P
VS(U)
VB(U)
VDD(UH)
HIN(U)
High Side
HVIC1
HS1
VS(V)
VB(V)
VDD(VH)
HIN(V)
High Side
HVIC2
HS2
VS(W)
VB(W)
VDD(WH)
HIN(W)
High Side
HVIC3
HS3
VTS
LIN(U)
LIN(V)
LIN(W)
VFO
CFOD
CIN
VSS
VDD(L)
HS1
V
HS2
W
HS3
NFAM5065L4B
ZZZ
A
T
Y
WW
= Specific Device Code
= Assembly Lot Code
= Assembly Location
= Test Location
= Year
= Work Week
ORDERING INFORMATION
LS1
Low Side
LVIC
with
Protection
U
LS3
LS2
Device
LS1
NFAM5065L4B
LS2
LS3
NU
NV
Package
Shipping
DIP39
54.5 x 31.0
(Pb-Free)
90 / Box
NW
Figure 1. Application Schematic
© Semiconductor Components Industries, LLC, 2019
April, 2020 − Rev. 1
1
Publication Order Number:
NFAM5065L4B/D
NFAM5065L4B
APPLICATION SCHEMATIC
VB(U) (3)
N.C (38)
VS(U) (1)
P (37)
CS
HIN(U) (6)
VDD(UH) (4)
HIN
VDD
+ C1
VB
HOUT
HVIC1
VSS
VS
HIN
VB
HOUT
HVIC2
U (36)
VB(V) (9)
VS(V) (7)
HIN(V) (12)
VDD(VH) (10)
VDD
VSS
VS
V (35)
Motor
VB(W) (15)
VS(W) (13)
MCU
HIN(W) (18)
VDD(WH) (16)
VTS (20)
LIN(U) (21)
LIN(V) (22)
LIN(W) (23)
HIN
VDD
VSS
VB
HOUT
HVIC3
VS
W (34)
VTS
OUT(U)
LIN(U)
NU (33)
LIN(V)
LIN(W)
5V line
VFO (24)
CFOD (25)
CIN (26)
15V line
VDD(L) (28)
VSS (27)
VFO
LVIC
OUT(V)
CFOD
NV (32)
CIN
VDD
VSS
OUT(W)
NW (31)
Signal for over current trip
Figure 2. Application Schematic − Adjustable Option
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2
Phase current
NFAM5065L4B
BLOCK DIAGRAM
N.C (38)
VS(U) (1)
P (37)
VB(U) (3)
VB
VDD(UH) (4)
HIN(U) (6)
VDD
HOUT
HVIC1
HIN
VSS
VS
VDD
HOUT
U (36)
VS(V) (7)
VB(V)(9)
VB
VDD(VH) (10)
HIN(V) (12)
HVIC2
HIN
VSS
VS
VDD
HOUT
V (35)
VS(W) (13)
VB(W) (15)
VB
VDD(WH) (16)
HIN(W) (18)
HVIC3
HIN
VTS (20)
VTS
LIN(U) (21)
LIN(U)
LIN(V) (22)
LIN(V)
LIN(W) (23)
LIN(W)
VFO (24)
VFO
W (34)
VS
VSS
OUT(U)
NU (33)
OUT(V)
LVIC
CFOD (25)
CFOD
NV (32)
CIN (26)
CIN
VSS (27)
VSS
VDD(L) (28)
VDD
OUT(W)
NW (31)
Figure 3. Equivalent Block Diagram
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3
NFAM5065L4B
PIN FUNCTION DESCRIPTION
Pin
Name
1
VS(U)
(2)
−
3
VB(U)
Description
High−Side Bias Voltage GND for U phase IGBT Driving
Dummy
High−Side Bias Voltage for U phase IGBT Driving
4
VDD(UH)
(5)
−
High−Side Bias Voltage for U phase IC
6
HIN(U)
Signal Input for High−Side U Phase
7
VS(V)
High−Side Bias Voltage GND for V phase IGBT Driving
(8)
−
9
VB(V)
Dummy
Dummy
High−Side Bias Voltage for V phase IGBT Driving
10
VDD(VH)
(11)
−
High−Side Bias Voltage for V phase IC
12
HIN(V)
Signal Input for High−Side V Phase
13
VS(W)
High−Side Bias Voltage GND for W phase IGBT Driving
(14)
−
15
VB(W)
Dummy
Dummy
High−Side Bias Voltage for W phase IGBT Driving
16
VDD(WH)
(17)
−
High−Side Bias Voltage for W phase IC
18
HIN(W)
(19)
−
20
VTS
21
LIN(U)
Signal Input for Low−Side U Phase
22
LIN(V)
Signal Input for Low−Side V Phase
23
LIN(W)
Signal Input for Low−Side W Phase
24
VFO
25
CFOD
26
CIN
Input for Current Protection
27
VSS
Low−Side Common Supply Ground
Dummy
Signal Input for High−Side W Phase
Dummy
Voltage Output for LVIC Temperature Sensing Unit
Fault Output
Capacitor for Fault Output Duration Selection
28
VDD(L)
(29)
−
Low−Side Bias Voltage for IC and IGBTs Driving
Dummy
(30)
−
Dummy
31
NW
Negative DC−Link Input for U Phase
32
NV
Negative DC−Link Input for V Phase
33
NU
Negative DC−Link Input for W Phase
34
W
Output for U Phase
35
V
Output for V Phase
36
U
Output for W Phase
37
P
Positive DC−Link Input
38
N.C
(39)
−
No Connection
Dummy
1. Pins of () are the dummy for internal connection. These pins should be no connection.
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4
NFAM5065L4B
ABSOLUTE MAXIMUM RATINGS (TC = 25°C) (Note 2)
Symbol
Value
Unit
Supply Voltage
P−NU, NV, NW
450
V
VPN(surge)
Supply Voltage (Surge)
P−NU, NV, NW (Note 3)
550
V
VPN(PROT)
Self Protection Supply Voltage Limit
(Short−Circuit Protection Capability)
VDD = VBS = 13.5 V ~16.5 V, TJ = 150°C,
VCES < 650 V, Non−Repetitive, < 2 ms
400
V
VPN
Vces
Rating
Conditions
Collector−emitter voltage
650
V
Maximum Repetitive
Revers Voltage
650
V
±Ic
Each IGBT Collector Current
±30
A
Iop
Output current (peak)
PWM control
±50
A
±Icp
Each IGBT Collector
Current (Peak)
Under 1 ms Pulse Width
±100
A
VDD
Control Supply Voltage
VDD(UH,VH,WH), VDD(L)−VSS
−0.3 to 20
V
VBS
High−Side
Control Bias voltage
VB(U)−VS(U), VB(V)−VS(V),
VB(W)−VS(W)
−0.3 to 20
V
VIN
Input Signal Voltage
HIN(U), HIN(V), HIN(W), LIN(U), LIN(V),
LIN(W)–VSS
−0.3 to VDD
V
VFO
Fault Output Supply Voltage
VFO–VSS
−0.3 to VDD
V
IFO
Fault Output Current
Sink Current at VFO pin
2
mA
Current Sensing
Input Voltage
CIN–VSS
−0.3 to VDD
V
Pc
Corrector Dissipation
Per One Chip
125
W
TJ
Operating Junction Temperature
−40 to +150
°C
Storage temperature
−40 to +125
°C
Module Case Operation Temperature
−40 to +125
°C
2500
Vrms
VRRM
VCIN
Tstg
Tc
VISO
Isolation voltage
60 Hz, Sinusoidal, AC 1 minute,
Connection
Pins to Heat Sink Plate
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
3. This surge voltage developed by the switching operation due to the wiring inductance between P and NU, NV, NW terminal.
THERMAL CHARACTERISTICS
Symbol
Rth(j-c)Q
Rth(j-c)F
Rating
Junction-to-Case Thermal
Resistance
Conditions
Min
Typ
Max
Unit
Inverter IGBT Part (per 1/6 module)
−
−
1.0
°C/W
Inverter FWD Part (per 1/6 module)
−
−
1.7
°C/W
4. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
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5
NFAM5065L4B
RECOMMENDED OPERATING CONDITIONS (Note 5)
Symbol
Rating
Conditions
Min
Typ
Max
Unit
−
300
400
V
VPN
Supply Voltage
P−NU, NV, NW
VDD
Gate Driver Supply
Voltages
VDD(UH,VH,WH), VDD(L)−VSS
13.5
15
16.5
V
VB(U)−VS(U), VB(V)−VS(V),
VB(W)−VS(W)
13.0
15
18.5
V
Supply Voltage Variation
−1
−
1
V/ms
PWM Frequency
1
−
20
kHz
1.5
−
−
ms
fPWM = 5 kHz
−
−
30.0
Arms
fPWM = 15 kHz
−
−
21.2
200 V ≤ VPN ≤ 400 V
13.5 V ≤ VDD ≤ 16.5 V
13.0 V ≤ VBS ≤ 18.5 V
−20°C ≤ Tc ≤ 100°C
1.0
−
−
1.5
−
−
M3 type screw
0.6
0.7
0.9
VBS
dVDD / dt,
dVBS / dt
fPWM
DT
Io
PWIN (on)
Dead Time
Turn-off to Turn-on (external)
Allowable r.m.s. Current
VPN = 300 V,
VDD = 15 V,
P.F. = 0.8
Tc ≤ 125°C,
Tj ≤ 150°C
(Note 5)
Allowable Input Pulse
Width
PWIN (off)
Package Mounting Torque
ms
Nm
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. Allowable r.m.s current depends on the actual conditions.
6. Flatness tolerance of the heatsink should be within −50 mm to +100 mm.
ELECTRICAL CHARACTERISTICS (TC = 25°C, VDD = 15 V, VBS = 15 V, unless otherwise specified.) (Note 7)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
INVERTERSECTION
Ices
Collector-Emitter Leakage
Current
Vce = Vces, TJ = 25°C
−
−
1
mA
Vce = Vces, TJ = 150°C
−
−
10
mA
Collector-Emitter Saturation
Voltage
VDD = VBS = 15 V, IN = 5 V
Ic = 50 A, TJ = 25°C
−
1.65
2.30
V
VDD = VBS = 15 V, IN = 5 V
Ic = 50 A, TJ = 150°C
−
1.85
−
V
IN = 0 V, Ic = 50 A, TJ = 25°C
−
2.00
2.40
V
IN = 0 V, Ic = 50 A, TJ = 150°C
−
2.00
−
V
0.90
1.50
2.10
ms
−
0.40
0.70
ms
toff
−
1.80
2.40
ms
tc(off)
−
0.25
0.75
ms
VCE(sat)
VF
ton
FWDi Forward Voltage
Switching Times
High Side
tc(on)
VPN = 300 V, VDD(H) = VDD(L) = 15 V
Ic = 50 A, TJ = 25°C, IN = 0 ⇔ 5 V
Inductive Load
−
0.25
−
ms
0.90
1.50
2.10
ms
−
0.30
0.60
ms
toff
−
1.70
2.30
ms
tc(off)
−
0.25
0.75
ms
trr
−
0.25
−
ms
trr
ton
tc(on)
Low Side
VPN = 300 V, VDD(H) = VDD(L) = 15 V
Ic = 50 A, TJ = 25°C, IN = 0 ⇔ 5 V
Inductive Load
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NFAM5065L4B
ELECTRICAL CHARACTERISTICS (TC = 25°C, VDD = 15 V, VBS = 15 V, unless otherwise specified.) (Note 7) (continued)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
DRIVER SECTION
IQDDH
Quiescent VDD Supply
Current
IQDDL
IPDDH
Operating VCC Supply
Current
IPDDL
VDD(UH,VH,WH) = 15 V,
HIN(U,V,W) = 0 V
VDD(UH)−VSS
VDD(VH)−VSS
VDD(WH)−VSS
−
−
0.30
mA
VDD(L) = 15 V,
LIN(U,V,W) = 0 V
VDD(L)−VSS
−
−
3.50
mA
VDD(UH,VH,WH) = 15 V,
fPWM = 20 kHz, Duty = 50%,
Applied to one PWM Signal
Input for High-Side
VDD(UH)−VSS
VDD(VH)−VSS
VDD(WH)−VSS
−
−
0.40
mA
VDD(L) = 15 V,
fPWM = 20 kHz, Duty = 50%,
Applied to one PWM Signal
Input for Low-Side
VDD(L)−VSS
−
−
6.00
mA
IQBS
Quiescent VBS Supply
Current
VBS = 15 V,
HIN(U,V,W) = 0 V
VB(U)−VS(U)
VB(V)−VS(V)
VB(W)−VS(W)
−
−
0.30
mA
IPBS
Operating VBS Supply
Current
VDD = VBS = 15 V,
fPWM = 20 kHz, Duty = 50%,
Applied to one PWM Signal
Input for High-Side
VB(U)−VS(U)
VB(V)−VS(V)
VB(W)−VS(W)
−
−
5.00
mA
VIN(ON)
ON Threshold Voltage
HIN(U,V,W)−VSS, LIN(U,V,W)−VSS
−
−
2.6
V
VIN(OFF)
OFF Threshold Voltage
0.8
−
−
V
VCIN(ref)
Short Circuit Trip Level
VDD = 15 V, CIN−VSS
0.46
0.48
0.50
V
Supply Circuit
Under-Voltage Protection
Detection Level
10.3
−
12.5
V
Reset Level
10.8
−
13.0
V
UVBSD
Detection Level
10.0
−
12.0
V
UVBSR
Reset Level
10.5
−
12.5
V
Voltage Output for LVIC
Temperature Sensing Unit
VTS−VSS = 10 nF, Temp. = 25°C
0.905
1.030
1.155
V
Fault Output Voltage
VDD = 0 V, CIN = 0 V,
VFO Circuit: 10 kW to 5 V Pull-up
4.9
−
−
V
VDD = 0 V, CIN = 1 V,
VFO Circuit: 10 kW to 5 V Pull-up
−
−
0.95
V
CFOD = 22 nF
1.6
2.4
−
ms
If = 0.1 A
3.4
4.6
5.8
V
30
38
46
W
UVDDD
UVDDR
VTS
VFOH
VFOL
tFOD
Fault-Output Pulse Width
BOOTSTRAP SECTION
VF
RBOOT
Bootstrap Diode Forward
Voltage
Built-in Limiting Resistance
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25_C.
Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
8. The fault−out pulse width tFOD depends on the capacitance value of CFOD according to the following approximate equation:
tFOD = 0.1 × 106 × CFOD (s).
9. Values based on design and/or characterization.
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7
NFAM5065L4B
Temperature of LVIC versus VTS Characteristics
4.0
VTS Output Voltage (V)
3.5
3.0
2.5
2.0
1.5
1.0
40
45
50
55
60
65
70
75
80
85
90
95 100 105 110 115 120 125 130
LVIC Temperature (5C)
Figure 4. Temperature of LVIC versus VTS Characteristics
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DIP39, 54.5x31.0 EP−2
CASE MODGX
ISSUE O
DATE 02 APR 2019
GENERIC
MARKING DIAGRAM*
XXXXXXXXXXXXXXXXX
ZZZATYWW
XXXXX = Specific Device Code
ZZZ
= Assembly Lot Code
AT
= Assembly & Test Location
Y
= Year
WW = Work Week
*This information is generic. Please refer to device data
sheet for actual part marking. Pb−Free indicator, “G” or
microdot “ G”, may or may not be present. Some products
may not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON05290H
DIP39, 54.5x31.0 EP−2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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