NLAST4599DFT2G

DATA SHEET www.onsemi.com Low Voltage Single Supply SPDT Analog Switch MARKING DIAGRAMS NLAST4599 The NLAST4599 is an advanced high speed CMOS single pole − double throw analog switch fabricated with silicon gate CMOS technology. It achieves high speed propagation delays and low ON resistances while maintaining low power dissipation. This switch controls analog and digital voltages that may vary across the full power−supply range (from VCC to GND). The device has been designed so the ON resistance (RON) is much lower and more linear over input voltage than RON of typical CMOS analog switches. The channel select input structure provides protection when voltages between 0 V and 5.5 V are applied, regardless of the supply voltage. This input structure helps prevent device destruction caused by supply voltage − input/output voltage mismatch, battery backup, hot insertion, etc. Features • • • • • • • • • • • • Select Pin Compatible with TTL Levels Channel Select Input Over−Voltage Tolerant to 5.5 V Fast Switching and Propagation Speeds Break−Before−Make Circuitry Low Power Dissipation: ICC = 2 A (Max) at TA = 25°C Diode Protection Provided on Channel Select Input Improved Linearity and Lower ON Resistance over Input Voltage Latch−up Performance Exceeds 300 mA ESD Performance: HBM > 2000 V; MM > 200 V Chip Complexity: 38 FETs NLVAST Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant SELECT 1 6 NO V+ 2 5 COM GND 3 4 NC TSOP−6 DT SUFFIX CASE 318G A1MG G 1 SC−88/SC−70/SOT−363 DF SUFFIX CASE 419B A1MG G 1 A1 = Specific Device Code A = Assembly Location M = Date Code* G = Pb−Free Package (Note: Microdot may be in either location) *Date Code orientation and/or position and underbar may vary depending upon manufacturing location. FUNCTION TABLE Select ON Channel L H NC NO ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. Figure 1. Pin Assignment 2X1 NO U U COM 2X0 U CHANNEL SELECT NC Figure 2. Logic Symbol © Semiconductor Components Industries, LLC, 2006 September, 2021 − Rev. 10 1 Publication Order Number: NLAST4599/D NLAST4599 MAXIMUM RATINGS (Note 1) Symbol Value Unit Positive DC Supply Voltage Parameter VCC −0.5 to +7.0 V Analog Input Voltage (VNO or VCOM) VIS −0.5 ≤ VIS ≤ VCC )0.5 V Digital Select Input Voltage VIN −0.5 ≤ VI ≤ + 7.0 V DC Current, Into or Out of Any Pin IIK $50 mA PD 200 200 mW TSTG −65 to +150 °C Lead Temperature, 1mm from Case for 10 seconds TL 260 °C Junction Temperature Under Bias TJ 150 °C VESD 2000 200 N/A V ILATCHUP $300 mA JA 333 333 °C/W Power Dissipation in Still Air SC−88 TSOP6 Storage Temperature Range ESD Withstand Voltage Latchup Performance Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) Above VCC and Below GND at 125°C (Note 5) Thermal Resistance SC−88 TSOP6 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. 2. Tested to EIA/JESD22−A114−A 3. Tested to EIA/JESD22−A115−A 4. Tested to JESD22−C101−A 5. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Max Unit DC Supply Voltage VCC 2.0 5.5 V Digital Select Input Voltage VIN GND 5.5 V Analog Input Voltage (NC, NO, COM) VIS GND VCC V Operating Temperature Range TA −55 +125 Input Rise or Fall Time SELECT tr, tf VCC = 3.3 V + 0.3 V VCC = 5.0 V + 0.5 V 0 0 100 20 °C ns/V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 TJ = 80°C 117.8 TJ = 90°C 1,032,200 TJ = 100°C 80 TJ = 110°C Time, Years TJ = 120°C Time, Hours FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 130°C Junction Temperature 5C NORMALIZED FAILURE RATE DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES 1 1 10 TIME, YEARS 100 1000 Figure 3. Failure Rate vs. Time Junction Temperature www.onsemi.com 2 NLAST4599 DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND) Guaranteed Limit Symbol VCC −55 to 255C