NTMSD3P303R2
FETKY™
P−Channel Enhancement−Mode
Power MOSFET and Schottky Diode
Dual SO−8 Package
Features
• High Efficiency Components in a Single SO−8 Package
• High Density Power MOSFET with Low RDS(on),
•
•
•
•
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MOSFET
−3.05 AMPERES
−30 VOLTS
0.085 W @ VGS = −10 V
Schottky Diode with Low VF
Independent Pin−Outs for MOSFET and Schottky Die
Allowing for Flexibility in Application Use
Less Component Placement for Board Space Savings
SO−8 Surface Mount Package,
Mounting Information for SO−8 Package Provided
Pb−Free Package is Available
SCHOTTKY DIODE
3.0 AMPERES
30 VOLTS
420 mV @ IF = 3.0 A
Applications
• DC−DC Converters
• Low Voltage Motor Control
• Power Management in Portable and Battery−Powered Products, i.e.:
A
Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones
A
MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
S
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Thermal Resistance −
Junction−to−Ambient (Note 1)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 70°C
Pulsed Drain Current (Note 4)
Thermal Resistance −
Junction−to−Ambient (Note 2)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 70°C
Pulsed Drain Current (Note 4)
Thermal Resistance −
Junction−to−Ambient (Note 3)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 70°C
Pulsed Drain Current (Note 4)
Operating and Storage
Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = −30 Vdc, VGS = −4.5 Vdc,
Peak IL = −7.5 Apk, L = 5 mH, RG = 25 )
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
VDSS
VGS
−30
"20
V
V
G
RJA
PD
ID
ID
IDM
171
0.73
−2.34
−1.87
−8.0
°C/W
W
A
A
A
RJA
PD
ID
ID
IDM
100
1.25
−3.05
−2.44
−12
°C/W
W
A
A
A
RJA
PD
ID
ID
IDM
TJ, Tstg
62.5
2.0
−3.86
−3.10
−15
−55 to
+150
140
°C/W
W
A
A
A
°C
EAS
mJ
March, 2006 − Rev. 2
8
2
7
C
C
6
D
3
4
D
5
(TOP VIEW)
MARKING DIAGRAM &
PIN ASSIGNMENT
C
C
D D
8
8
E3P303
AYWW G
G
1
SO−8
CASE 751
STYLE 18
1
A
A
S G
E3P303 = Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
TL
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Minimum FR−4 or G−10 PCB, Steady State.
2. Mounted onto a 2″ square FR−4 Board
(1in sq, 2 oz Cu 0.06″ thick single sided), Steady State.
3. Mounted onto a 2″ square FR−4 Board
(1 in sq, 2 oz Cu 0.06″ thick single sided), t ≤ 10 seconds.
4. Pulse Test: Pulse Width = 300 s, Duty Cycle = 2%.
© Semiconductor Components Industries, LLC, 2006
1
1
Device
Package
Shipping†
NTMSD3P303R2
SO−8
2500/Tape & Reel
NTMSD3P303R2G
SO−8
2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NTMSD3P303R2/D
NTMSD3P303R2
SCHOTTKY MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Peak Repetitive Reverse Voltage
DC Blocking Voltage
VRRM
VR
30
V
Thermal Resistance − Junction−to−Ambient (Note 5)
RJA
197
°C/W
Thermal Resistance − Junction−to−Ambient (Note 6)
RJA
97
°C/W
Thermal Resistance − Junction−to−Ambient (Note 7)
RJA
62.5
°C/W
IO
3.0
A
Peak Repetitive Forward Current (Note 7)
(Rated VR, Square Wave, 20 kHz, TA = 105°C)
IFRM
6.0
A
Non−Repetitive Peak Surge Current (Note 7)
(Surge Applied at Rated Load Conditions, Half−Wave, Single Phase, 60 Hz)
IFSM
30
A
Rating
Average Forward Current (Note 7)
(Rated VR, TA = 100°C)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
5. Minimum FR−4 or G−10 PCB, Steady State.
6. Mounted onto a 2″ square FR−4 Board (1 in sq, 2 oz Cu 0.06″ thick single sided), Steady State.
7. Mounted onto a 2″ square FR−4 Board (1 in sq, 2 oz Cu 0.06″ thick single sided), t ≤ 10 seconds.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (Note 8)
Symbol
Characteristic
Min
Typ
Max
−30
−
−
−30
−
−
−
−
−
−
−1.0
−25
−
−
−100
−
−
100
−1.0
−
−1.7
3.6
−2.5
−
−
−
0.063
0.090
0.085
0.125
−
5.0
−
Ciss
−
520
750
Coss
−
170
325
Crss
−
70
135
Unit
OFF CHARACTERISTICS
V(BR)DSS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = −250 Adc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = −30 Vdc, VGS = 0 Vdc, TJ = 25°C)
(VDS = −30 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate−Body Leakage Current
(VGS = −20 Vdc, VDS = 0 Vdc)
IGSS
Gate−Body Leakage Current
(VGS = +20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
Adc
nAdc
nAdc
ON CHARACTERISTICS
Gate Threshold Voltage
(VDS = VGS, ID = −250 Adc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−State Resistance
(VGS = −10 Vdc, ID = −3.05 Adc)
(VGS = −4.5 Vdc, ID = −1.5 Adc)
RDS(on)
Forward Transconductance
(VDS = −15 Vdc, ID = −3.05 Adc)
gFS
Vdc
Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(VDS = −24 Vdc,
VGS = 0 Vdc,
f = 1.0 MHz)
8. Handling precautions to protect against electrostatic discharge are mandatory.
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2
pF
NTMSD3P303R2
MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (Note 9)
Characteristic
Symbol
Min
Typ
Max
Unit
td(on)
−
12
22
ns
tr
−
16
30
td(off)
−
45
80
SWITCHING CHARACTERISTICS (Notes 10 & 11)
Turn−On Delay Time
(VDD = −24 Vdc,
ID = −3.05 Adc,
VGS = −10 Vdc,
RG = 6.0 )
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
(VDD = −24 Vdc,
ID = −1.5 Adc,
VGS = −4.5 Vdc,
RG = 6.0 )
Rise Time
Turn−Off Delay Time
Fall Time
Total Gate Charge
(VDS = −24 Vdc,
VGS = −10 Vdc,
ID = −3.05 Adc)
Gate−Source Charge
Gate−Drain Charge
tf
−
45
80
td(on)
−
16
−
tr
−
42
−
td(off)
−
32
−
tf
−
35
−
Qtot
−
16
25
ns
nC
Qgs
−
2.0
−
Qgd
−
4.5
−
VSD
−
−
−0.96
−0.78
−1.25
−
Vdc
trr
−
34
−
ns
ta
−
18
−
tb
−
16
−
QRR
−
0.03
−
BODY−DRAIN DIODE RATINGS (Note 10)
Diode Forward On−Voltage
(IS = −3.05 Adc, VGS = 0 Vdc)
(IS = −3.05 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(IS = −3.05 Adc,
VGS = 0 Vdc,
dIS/dt = 100 A/ s)
Reverse Recovery Stored Charge
C
9. Handling precautions to protect against electrostatic discharge is mandatory.
10. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%.
11. Switching characteristics are independent of operating junction temperature.
SCHOTTKY RECTIFIER ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (Note 12)
VF
Maximum Instantaneous Forward Voltage
IF = 100 mAdc
IF = 3.0 Adc
IF = 6.0 Adc
Maximum Instantaneous Reverse Current
Maximum Voltage Rate of Change
VR = 30 Vdc
VR = 30 Vdc
12. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%.
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3
IR
TJ = 25°C
TJ = 125°C
Volts
0.28
0.42
0.50
0.13
0.33
0.45
Volts
TJ = 25°C
TJ = 125°C
250
dV/dt
25
10,000
A
mA
V/s
NTMSD3P303R2
TYPICAL MOSFET ELECTRICAL CHARACTERISTICS
−ID, DRAIN CURRENT (AMPS)
VGS = −4 V
VGS = −4.6 V
VGS = −6 V
4
VGS = −4.8 V
TJ = 25°C
VGS = −3.6 V
VGS = −2.8 V
VGS = −3.2 V
VGS = −5 V
3
2
VGS = −2.6 V
1
0
0.25
0.5
0.75
1
1.25
VGS = −3 V
1.5
1.75
TJ = −55°C
1
1
2
3
4
5
Figure 2. Transfer Characteristics
ID = −3.05 A
TJ = 25°C
0.4
0.3
0.2
0.1
5
4
6
7
8
0.7
ID = −1.5 A
TJ = 25°C
0.6
0.5
0.4
0.3
0.2
0.1
0
2
4
3
5
6
7
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Gate−to−Source
Voltage
0.25
TJ = 25°C
0.2
VGS = −4.5 V
0.15
VGS = −10 V
0.1
1
TJ = 25°C
2
Figure 1. On−Region Characteristics
0.5
0.05
TJ = 100°C
3
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.6
3
4
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.7
0
VDS > = −10 V
5
0
2
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
VGS = −4.4 V
VGS = −8 V
5
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
6
VGS = −10 V
2
3
4
5
6
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
−ID, DRAIN CURRENT (AMPS)
6
1.6
1.4
ID = −3.05 A
VGS = −10 V
1.2
1
0.8
0.6
−50
−25
0
25
50
75
100
125
−ID, DRAIN CURRENT (AMPS)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance vs. Drain Current and
Gate Voltage
Figure 6. On Resistance Variation with
Temperature
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4
150
NTMSD3P303R2
VGS = 0 V
VDS = 0 V
1200
C, CAPACITANCE (pF)
IDSS, LEAKAGE (nA)
10000
TJ = 150°C
1000
TJ = 125°C
100
VGS = 0 V
Ciss
1000
800
Ciss
Crss
600
400
Coss
200
10
6
10
14
18
22
26
0
10
30
5
QT
15
6
10
Q2
2
4
6
8
10
12
0
16
14
30
100
td(off)
tf
tr
10
1
1
100
10
RG, GATE RESISTANCE ()
Figure 9. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
Figure 10. Resistive Switching Time Variation
vs. Gate Resistance
3
VDS = −24 V
ID = −1.5 A
VGS = −4.5 V
tr
tf
1
25
Qg, TOTAL GATE CHARGE (nC)
100
10
20
5
ID = −3.05 A
TJ = 25°C
0
15
td(on)
2
1000
t, TIME (ns)
20
t, TIME (ns)
VDS
VGS
0
10
VDS = −24 V
ID = −3.05 A
VGS = −10 V
25
10
IS, SOURCE CURRENT (AMPS)
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
30 1000
4
−VDS
Figure 8. Capacitance Variation
12
Q1
5
GATE−TO−SOURCE OR DRAIN−TO−SOURCE
VOLTAGE (VOLTS)
Figure 7. Drain−to−Source Leakage Current
vs. Voltage
8
0
−VGS
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
10
Crss
TJ = 25°C
td(off)
td(on)
100
VGS = 0 V
TJ = 25°C
2.5
2
1.5
1
0.5
0
0.2
0.4
0.6
0.8
1
RG, GATE RESISTANCE ()
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 11. Resistive Switching Time Variation
vs. Gate Resistance
Figure 12. Diode Forward Voltage vs. Current
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5
1.2
NTMSD3P303R2
VGS = 12 V
SINGLE PULSE
TA = 25°C
10
1.0 ms
di/dt
10 ms
IS
dc
1.0
trr
ta
0.1
0.01
1
0.25 IS
tp
10
1.0
tb
TIME
RDS(on)
THERMAL LIMIT
PACKAGE LIMIT
IS
100
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 13. Maximum Rated Forward Biased
Safe Operating Area
Figure 14. Diode Reverse Recovery Waveform
1.0
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESPONSE
−ID, DRAIN CURRENT (AMPS)
100
D = 0.5
0.2
0.1
0.1
Normalized to RJA at Steady State (1″ pad)
Chip
Junction 2.32
18.5
50.9
37.1
56.8
0.05
0.02
0.01
1E−03
0.0014 F
0.01
0.0073 F
0.022 F
0.105 F
0.484 F
3.68 F
Ambient
Single Pulse
1E−02
24.4
1E−01
1E+00
t, TIME (s)
Figure 15. FET Thermal Response
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6
1E+01
1E+02
1E+03
NTMSD3P303R2
10
85°C
25°C
−40 °C
TJ = 125°C
1.0
0.1
0.1
0.2
0.3
0.4
0.5
0.6
0.7
10
85°C
TJ = 125°C
0.1
0
0.1
0.2
0.3
0.4
0.6
0.5
0.7
VF, MAXIMUM INSTANTANEOUS FORWARD VOLTAGE (VOLTS)
Figure 16. Typical Forward Voltage
Figure 17. Maximum Forward Voltage
IR, MAXIMUM REVERSE CURRENT (AMPS)
TJ = 125°C
0.01
85°C
0.001
0.0001
25°C
0.8
0.1
TJ = 125°C
0.01
0.001
25°C
0.0001
0.00001
0.00001
0.000001
0.000001
0
5.0
10
15
20
25
30
0
5.0
VR, REVERSE VOLTAGE (VOLTS)
IO , AVERAGE FORWARD CURRENT (AMPS)
100
10
5.0
10
15
20
20
25
30
Figure 19. Maximum Reverse Current
1000
0
15
10
VR, REVERSE VOLTAGE (VOLTS)
Figure 18. Typical Reverse Current
C, CAPACITANCE (pF)
25°C
1.0
VF, INSTANTANEOUS FORWARD VOLTAGE (VOLTS)
0.1
IR, REVERSE CURRENT (AMPS)
IF, INSTANTANEOUS FORWARD CURRENT (AMPS)
IF, INSTANTANEOUS FORWARD CURRENT (AMPS)
TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS
25
30
5.0
dc
4.5
FREQ = 20 kHz
4.0
3.5
SQUARE WAVE
3.0
Ipk/Io =
2.5
Ipk/Io = 5.0
2.0
1.5
Ipk/Io = 10
1.0
Ipk/Io = 20
0.5
0
0
VR, REVERSE VOLTAGE (VOLTS)
20
40
60
80
100
120
TA, AMBIENT TEMPERATURE (°C)
Figure 20. Typical Capacitance
Figure 21. Current Derating
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7
140
160
NTMSD3P303R2
PFO , AVERAGE POWER DISSIPATION (WATTS)
TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS
1.75
dc
1.50
SQUARE
WAVE
Ipk/Io =
1.25
Ipk/Io = 5.0
1.00
Ipk/Io = 10
0.75
Ipk/Io = 20
0.50
0.25
0
1.0
0
2.0
3.0
5.0
4.0
IO, AVERAGE FORWARD CURRENT (AMPS)
Figure 22. Forward Power Dissipation
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE
1.0
D = 0.5
0.2
0.1
0.1
NORMALIZED TO RJA AT STEADY STATE (1″ PAD)
0.05
0.02
0.1010
CHIP
JUNCTION 39.422 F
0.01
0.01
1.2674
27.987 30.936 36.930
493.26 F 0.0131 F
0.2292 F 2.267 F
SINGLE PULSE
0.001
1.0E−05
1.0E−04
AMBIENT
1.0E−03
1.0E−02
1.0E−01
t, TIME (s)
1.0E+00
Figure 23. Schottky Thermal Response
FETKY is a trademark of International Rectifier Corporation.
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8
1.0E+01
1.0E+02
1.0E+03
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
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© Semiconductor Components Industries, LLC, 2019
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SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
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