NVD5890NT4G-VF01

NVD5890N Power MOSFET 40 V, 123 A, Single N−Channel DPAK Features • • • • • Low RDS(on) to Minimize Conduction Losses MSL 1/260°C AEC Q101 Qualified and PPAP Capable 100% Avalanche Tested These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com V(BR)DSS RDS(on) ID 40 V 3.7 mW @ 10 V 123 A Applications • Motor Drivers • Pump Drivers for Automotive Braking, Steering and Other High D Current Systems MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS 40 V Gate−to−Source Voltage VGS "20 V ID 123 A PD 107 Continuous Drain Current (RqJC) TC = 25°C Power Dissipation (RqJC) TC = 25°C Continuous Drain Current (RqJA) (Note 1) TC = 85°C Steady State tp=10ms Current Limited by Package ID 18.5 4.0 W TA = 25°C IDM 400 A TA = 25°C IDmaxPkg 100 A TJ, Tstg −55 to 175 °C IS 100 A Drain to Source dV/dt dV/dt 6.0 V/ns Single Pulse Drain−to−Source Avalanche Energy (VDD = 32 V, VGS = 10 V, L = 0.3 mH, IL(pk) = 40 A, RG = 25 W) EAS 240 mJ TL 260 °C Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 3 CASE 369C DPAK (Bent Lead) STYLE 2 A 24 PD Source Current (Body Diode) 1 2 W TA = 25°C Operating Junction and Storage Temperature 4 95 TA = 85°C Power Dissipation (RqJA) (Note 1) Pulsed Drain Current TA = 25°C S MARKING DIAGRAMS & PIN ASSIGNMENT 4 Drain AYWW 58 90NG Parameter N−Channel G 2 1 Drain 3 Gate Source A Y WW 5890N G = Assembly Location* = Year = Work Week = Device Code = Pb−Free Package * The Assembly Location Code (A) is front side optional. In cases where the Assembly Location is stamped in the package bottom (molding ejecter pin), the front side assembly code may be blank. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2012 May, 2017 − Rev. 2 1 Publication Order Number: NVD5890N/D NVD5890N THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Unit Junction−to−Case (Drain) Parameter RqJC 1.4 °C/W Junction−to−Ambient − Steady State (Note 1) RqJA 37 Junction−to−Ambient − Steady State (Note 2) RqJA 76 1. Surface−mounted on FR4 board using 650 mm2 pad size, 2 oz Cu. 2. Surface−mounted on FR4 board using 36 mm2 pad size. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 40 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Parameter Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current V 40 VGS = 0 V, VDS = 40 V mV/°C TJ = 25°C 1.0 TJ = 150°C 100 IGSS VDS = 0 V, VGS = "20 V VGS(TH) VGS = VDS, ID = 250 mA mA "100 nA 3.5 V ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance Forward Transconductance 1.5 7.4 mV/°C RDS(on) VGS = 10 V, ID = 50 A 2.9 3.7 gFS VDS = 15 V, ID = 15 A 16.8 S 4975 pF mW CHARGES AND CAPACITANCES Input Capacitance Ciss VGS = 0 V, f = 1.0 MHz, VDS = 12 V 785 VGS = 0 V, f = 1.0 MHz, VDS = 25 V 4760 Output Capacitance Coss Reverse Transfer Capacitance Crss Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 385 Total Gate Charge QG(TOT) 74 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD 16 td(on) 14 VGS = 10 V, VDS = 15 V, ID = 50 A 490 pF 580 100 nC 5.0 17 SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(off) VGS = 10 V, VDS = 20 V, ID = 50 A, RG = 2.0 W tf 55 35 7.0 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 2 ns NVD5890N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Typ Max Unit V DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge VSD VGS = 0 V, IS = 50 A TJ = 25°C 0.9 1.2 VGS = 0 V, IS = 20 A TJ = 25°C 0.8 1.0 tRR ta tb 35 VGS = 0 V, dIs/dt = 100 A/ms, IS = 50 A QRR 20 15 40 www.onsemi.com 3 ns nC NVD5890N 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 10 V 6V TJ = 25°C 7V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) TYPICAL PERFORMANCE CURVES VGS = 5 V 4.5 V 4.2 V 4V 3.8 V 3.6 V 0 1 2 3 4 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 5 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 VDS ≥ 10 V TJ = 25°C TJ = 150°C TJ = −55°C 2 3 4 5 VGS, GATE−TO−SOURCE VOLTAGE (V) 20 Figure 2. Transfer Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) Figure 1. On−Region Characteristics TJ = 25°C 18 16 14 ID = 50 A 12 10 8 6 4 2 0 3 4 6 5 7 9 8 10 VGS, GATE−TO−SOURCE VOLTAGE (V) 20 16 14 12 VGS = 5 V 10 8 6 VGS = 10 V 4 2 0 40 0 80 120 160 200 240 280 ID, DRAIN CURRENT (A) Figure 4. On−Resistance vs. Drain Current and Gate Voltage 2.0 1000 VGS = 0 V VGS = 10 V ID = 50 A IDSS, LEAKAGE (mA) RDS(on), NORMALIZED DRAIN−TO−SOURCE RESISTANCE (mW) TJ = 25°C 18 Figure 3. On−Resistance vs. Drain Current 1.75 6 1.5 1.25 1.0 100 TJ = 175°C TJ = 150°C 10 0.75 0.5 −50 −25 0 25 50 75 100 125 150 175 1 0 TJ, JUNCTION TEMPERATURE (°C) 4 8 12 16 20 24 28 32 36 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 4 40 NVD5890N C, CAPACITANCE (pF) 6000 VGS = 0 V TJ = 25°C f = 1 MHz Ciss 5000 4000 3000 2000 Coss 1000 0 Crss 0 5 10 15 20 25 30 35 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 20 VGS, GATE−TO−SOURCE VOLTAGE (V) 7000 40 QT QDS QGS VDS = 15 V ID = 50 A TJ = 25°C 20 10 40 30 50 60 70 5 0 80 Qg, TOTAL GATE CHARGE (nC) Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge Figure 7. Capacitance Variation 100 1000 VGS = 10 V VDD = 20 V ID = 50 A IS, SOURCE CURRENT (A) td(off) tf tr 100 td(on) 10 1 10 100 TJ = 150°C 10 100°C 1 0.1 0.3 0.4 0.5 25°C 0.6 0.7 TJ = −55°C 0.8 0.9 1.0 1.1 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 1000 I D, DRAIN CURRENT (AMPS) t, TIME (ns) VGS 10 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1 15 VDS VDS, DRAIN−TO−SOURCE VOLTAGE (V) TYPICAL PERFORMANCE CURVES 10 ms 100 100 ms 10 1 0.1 VGS ≤ 20 V SINGLE PULSE TC = 25°C 1 ms 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 dc 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area www.onsemi.com 5 100 1.2 NVD5890N r(t), EFFECTIVE TRANSIENT THERMAL RESPONSE (°C/W) TYPICAL PERFORMANCE CURVES 10 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE 0.001 0.000001 0.00001 RqJC = 1.4°C/W Steady State 0.0001 0.001 0.01 t, TIME (s) 0.1 1 10 100 1000 Figure 12. Thermal Response ORDERING INFORMATION Package Shipping† NVD5890NT4G DPAK (Pb−Free) 2500/Tape & Reel NVD5890NT4G−VF01 DPAK (Pb−Free) 2500/Tape & Reel Order Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F 4 1 2 DATE 21 JUL 2015 3 SCALE 1:1 A E b3 C A B c2 4 L3 Z D 1 L4 2 3 NOTE 7 b2 e c SIDE VIEW b 0.005 (0.13) TOP VIEW H DETAIL A M BOTTOM VIEW C Z H L2 GAUGE PLANE C L L1 DETAIL A Z SEATING PLANE BOTTOM VIEW A1 ALTERNATE CONSTRUCTIONS ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW AYWW XXX XXXXXG IC Discrete = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 6.17 0.243 SCALE 3:1 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z XXXXXX A L Y WW G 3.00 0.118 1.60 0.063 STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON10527D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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