NVTFS4823NTAG

NVTFS4823N Power MOSFET 30 V, 10.5 mW, 30 A, Single N−Channel Features • • • • • Small Footprint (3.3x3.3 mm) for Compact Design Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses NV Prefix for Automotive and Other Applications Requiring AEC−Q101 Qualified Site and Change Controls These are Pb−Free Devices http://onsemi.com V(BR)DSS 30 V RDS(on) MAX 10.5 mW @ 10 V 17.5 mW @ 4.5 V N−Channel ID MAX 30 A MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current RYJ−mb (Notes 1, 2, 3, 4) Power Dissipation RYJ−mb (Notes 1, 2, 3) Continuous Drain Current RqJA (Notes 1, 3, & 4) Power Dissipation RqJA (Notes 1, 3) Pulsed Drain Current Tmb = 25°C Steady State Tmb = 100°C Tmb = 25°C Tmb = 100°C TA = 25°C Steady State TA = 100°C TA = 25°C TA = 100°C TA = 25°C, tp = 10 ms IDM TJ, Tstg IS EAS PD ID PD Symbol VDSS VGS ID Value 30 "20 30 21 21 11 13 9.0 3.1 1.6 198 − 55 to 175 19 28.8 A °C A mJ 4823 A Y WW G W A 1 Unit V V A G (4) D (5 − 8) W S (1, 2, 3) MARKING DIAGRAM WDFN8 (m8FL) CASE 511AB 1 S S S G 4823 AYWWG G D D D D Operating Junction and Storage Temperature Source Current (Body Diode) Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 24 V, VGS = 10 V, IL(pk) = 24 A, L = 0.1 mH, RG = 25 W) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) TL 260 °C ORDERING INFORMATION Device NVTFS4823NTAG NVTFS4823NTWG Package Shipping† WDFN8 1500/Tape & Reel (Pb−Free) WDFN8 5000/Tape & Reel (Pb−Free) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. THERMAL RESISTANCE MAXIMUM RATINGS (Note 1) Parameter Junction−to−Mounting Board (top) − Steady State (Note 2, 3) Junction−to−Ambient − Steady State (Note 3) Symbol RYJ−mb RqJA Value 7.0 47 Unit °C/W †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Psi ( Y ) is used as required per JESD51 −12 for packages in which substantially less than 100% of the heat flows to single case surface. 3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 4. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. © Semiconductor Components Industries, LLC, 2011 January, 2011 − Rev. 0 1 Publication Order Number: NVTFS4823N/D NVTFS4823N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Zero Gate Voltage Drain Current V(BR)DSS IDSS IGSS VGS(TH) RDS(on) gFS Ciss Coss Crss QG(TOT) QG(TH) QGS QGD QG(TOT) td(on) tr td(off) tf VSD tRR ta tb QRR VGS = 0 V, dIS/dt = 100 A/ms, IS = 15 A VGS = 0 V, IS = 15 A TJ = 25°C TJ = 125°C VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W VGS = 10 V, VDS = 15 V, ID = 15 A VGS = 4.5 V, VDS = 15 V, ID = 15 A VGS = 0 V, f = 1.0 MHz, VDS = 12 V VGS = 0 V, ID = 250 mA VGS = 0 V, VDS = 30 V TJ = 25°C TJ = 125°C 30 1.0 10 "100 nA V mA Symbol Test Condition Min Typ Max Unit Gate−to−Source Leakage Current ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Drain−to−Source On Resistance VDS = 0 V, VGS = "20 V VGS = VDS, ID = 250 mA VGS = 10 V, ID = 15 A VGS = 4.5 V, ID = 15 A VDS = 1.5 V, ID = 20 A 1.5 8.1 13.5 34 2.5 10.5 17.5 V mW Forward Transconductance CHARGES AND CAPACITANCES Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate−to−Source Charge Gate−to−Drain Charge Total Gate Charge S 750 175 100 6.0 0.8 2.4 2.4 12 pF nC nC SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time 12 22 14 4 ns DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage 0.85 0.72 12 6.0 6.0 5.0 nC ns 1.1 V Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge 5. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 6. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NVTFS4823N TYPICAL CHARACTERISTICS 60 50 40 30 20 3.2 V 10 2.9 V 0 0 1 2 3 4 5 0 1 60 VDS ≥ 10 V ID, DRAIN CURRENT (A) 50 40 30 20 TJ = 125°C 10 TJ = 25°C 2 TJ = −55°C 3 4 5 10 V 5.5 V VGS = 4.5 V TJ = 25°C 4.1 V 3.8 V ID, DRAIN CURRENT (A) 3.5 V VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.020 0.019 0.018 0.017 0.016 0.015 0.014 0.013 0.012 0.011 0.010 0.009 0.008 0.007 0.006 0.025 Figure 2. Transfer Characteristics TJ = 25°C 0.020 VGS = 4.5 V 0.015 0.010 0.005 0 5 ID = 15 A TJ = 25°C VGS = 10 V 3 4 5 6 7 8 9 10 10 15 20 25 30 35 40 45 50 55 60 VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage 1.8 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1.6 1.4 1.2 1.0 0.8 0.6 ID = 15 A VGS = 10 V IDSS, LEAKAGE (nA) 1000 10000 Figure 4. On−Resistance vs. Drain Current and Gate Voltage VGS = 0 V TJ = 150°C TJ = 125°C 100 50 25 0 25 50 75 100 125 150 175 10 5 10 15 20 25 30 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 NVTFS4823N TYPICAL CHARACTERISTICS 1200 VGS = 0 V 1000 C, CAPACITANCE (pF) 800 600 400 Coss 200 0 Crss 0 5 10 15 20 25 DRAIN−TO−SOURCE VOLTAGE (V) 30 Ciss TJ = 25°C VGS, GATE−TO−SOURCE VOLTAGE (V) 10 QT 8 6 4 2 0 Qgs Qgd VDS = 15 V ID = 15 A TJ = 25°C 0 2 Figure 7. Capacitance Variation Figure 8. Gate−to−Source Voltage vs. Total Charge 40 IS, SOURCE CURRENT (A) VGS = 0 V TJ = 25°C 30 4 6 8 Qg, TOTAL GATE CHARGE (nC) 10 12 1000 VDD = 15 V ID = 10 A VGS = 10 V t, TIME (ns) 100 tr 10 td(off) td(on) tf 10 100 RG, GATE RESISTANCE (W) 20 10 1.0 1 0 0.5 0.6 0.7 0.8 0.9 1.0 Figure 9. Resistive Switching Time Variation vs. Gate Resistance 1000 VGS = 10 V Single Pulse TC = 25°C 10 ms 10 100 ms 10 ms 1 ms RDS(on) Limit Thermal Limit Package Limit dc 30 Figure 10. Diode Forward Voltage vs. Current VSD, SOURCE−TO−DRAIN VOLTAGE (V) EAS, SINGLE PULSE DRAIN−TO− SOURCE AVALANCHE ENERGY (mJ) ID = 24 A 25 20 15 10 5 0 ID, DRAIN CURRENT (A) 100 1 0.1 0.1 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 100 25 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (°C) 200 Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 4 NVTFS4823N TYPICAL CHARACTERISTICS 100 RqJA(t) (°C/W) EFFECTIVE TRANSIENT THERMAL RESISTANCE Duty Cycle = 0.5 10 0.2 0.1 0.05 0.02 0.01 0.1 Single Pulse 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 Figure 13. Thermal Response PULSE TIME (sec) http://onsemi.com 5 NVTFS4823N PACKAGE DIMENSIONS WDFN8 3.3x3.3, 0.65P CASE 511AB−01 ISSUE B 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS. 2X 0.20 C D D1 8765 A B 0.20 C E1 E 4X q 1234 TOP VIEW 0.10 C A 0.10 C SIDE VIEW 8X b CAB c A1 6X C SEATING PLANE e DETAIL A DETAIL A DIM A A1 b c D D1 D2 E E1 E2 e G K L L1 M q MILLIMETERS MIN NOM MAX 0.70 0.75 0.80 0.00 −−− 0.05 0.23 0.30 0.40 0.15 0.20 0.25 3.30 BSC 2.95 3.05 3.15 1.98 2.11 2.24 3.30 BSC 2.95 3.05 3.15 1.47 1.60 1.73 0.65 BSC 0.30 0.41 0.51 0.64 −−− −−− 0.30 0.43 0.56 0.06 0.13 0.20 1.40 1.50 1.60 0_ −−− 12 _ INCHES NOM 0.030 −−− 0.012 0.008 0.130 BSC 0.116 0.120 0.078 0.083 0.130 BSC 0.116 0.120 0.058 0.063 0.026 BSC 0.012 0.016 0.025 −−− 0.012 0.017 0.002 0.005 0.055 0.059 0_ −−− MIN 0.028 0.000 0.009 0.006 MAX 0.031 0.002 0.016 0.010 0.124 0.088 0.124 0.068 0.020 −−− 0.022 0.008 0.063 12 _ SOLDERING FOOTPRINT* e/2 1 4 0.10 0.05 c L 0.42 K PACKAGE OUTLINE 8X 0.65 PITCH 0.66 4X E2 8 5 M D2 BOTTOM VIEW L1 0.75 0.57 2.30 3.60 G 0.47 2.37 3.46 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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