SVD14N03RT4G

NTD14N03R, NVD14N03R MOSFET – Power, N-Channel, DPAK 14 A, 25 V Features • • • • • • • www.onsemi.com Planar HD3e Process for Fast Switching Performance Low RDS(on) to Minimize Conduction Loss Low Ciss to Minimize Driver Loss Low Gate Charge Optimized for High Side Switching Requirements in High−Efficiency DC−DC Converters NVD and SVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant 14 AMPERES, 25 VOLTS RDS(on) = 70.4 mW (Typ) D N−CHANNEL G S 4 MAXIMUM RATINGS (TJ = 25°C unless otherwise specified) Symbol Value Unit Drain−to−Source Voltage VDSS 25 Vdc Gate−to−Source Voltage − Continuous VGS ±20 Vdc Thermal Resistance − Junction−to−Case Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C, Chip − Continuous @ TA = 25°C, Limited by Package − Single Pulse (tp ≤ 10 ms) RqJC PD ID ID ID 6.0 20.8 14 11.4 28 °C/W W A A A Thermal Resistance, Junction−to−Ambient (Note 1) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C RqJA 80 °C/W PD ID 1.56 3.1 W A Thermal Resistance, Junction−to−Ambient (Note 2) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C RqJA 120 °C/W PD ID 1.04 2.5 W A Operating and Storage Temperature Range TJ, Tstg −55 to 150 °C Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using 0.5 sq. in pad size. 2. When surface mounted to an FR4 board using minimum recommended pad size. 1 2 3 DPAK CASE 369C (Surface Mount) STYLE 2 MARKING DIAGRAM & PIN ASSIGNMENTS 4 Drain AYWW T14 N03G Parameter 1 Gate A Y WW 14N03 G 2 Drain 3 Source = Assembly Location* = Year = Work Week = Device Code = Pb−Free Package * The Assembly Location code (A) is front side optional. In cases where the Assembly Location is stamped in the package, the front side assembly code may be blank. ORDERING INFORMATION See detailed ordering and shipping information on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2016 May, 2019 − Rev. 9 1 Publication Order Number: NTD14N03R/D NTD14N03R, NVD14N03R ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Characteristics Symbol Min Typ Max Drain−to−Source Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) V(br)DSS 25 − 28 − − − − − − − 1.0 10 − − ±100 1.0 − 1.5 − 2.0 − − − 117 70.4 130 95 − 7.0 − Ciss − 115 − Coss − 62 − Crss − 33 − td(on) − 3.8 − tr − 27 − td(off) − 9.6 − tf − 2.0 − QT − 1.8 − Q1 − 0.8 − Q2 − 0.7 − − − 0.93 0.82 1.2 − trr − 6.6 − ta − 4.75 − tb − 1.88 − QRR − 0.002 − Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C mAdc nAdc ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (Note 3) (VGS = 4.5 Vdc, ID = 5 Adc) (VGS = 10 Vdc, ID = 5 Adc) RDS(on) Forward Transconductance (Note 3) (VDS = 10 Vdc, ID = 5 Adc) gFS Vdc mV/°C mW Mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 20 Vdc, VGS = 0 V, f = 1 MHz) Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time (VGS = 10 Vdc, VDD = 10 Vdc, ID = 5 Adc, RG = 3 W) Fall Time Gate Charge (VGS = 5 Vdc, ID = 5 Adc, VDS = 10 Vdc) (Note 3) ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 5 Adc, VGS = 0 Vdc) (Note 3) (IS = 5 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (IS = 5 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) (Note 3) Reverse Recovery Stored Charge VSD Vdc ns mC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 2 NTD14N03R, NVD14N03R TYPICAL CHARACTERISTICS 14 8V 5V 7V 6V 10 ID, DRAIN CURRENT (AMPS) 12 4.5 V 8 4V 6 3.5 V 4 3V 2 VGS = 2.5 V 0 2 4 6 10 8 6 TJ = 25°C 4 TJ = 125°C 2 0 1 2 TJ = −55°C 3 4 5 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics VGS = 10 V 0.12 TJ = 125°C 0.08 TJ = 25°C TJ = −55°C 0.04 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 8 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.16 2 0 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.20 0 VDS ≥ 10 V 12 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 10 V 4 6 8 10 12 14 TJ = 125°C 0.16 TJ = 25°C 0.12 TJ = −55°C 0.08 0.04 VGS = 4.5 V 0 0 2 4 6 8 10 12 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Drain Current and Temperature Figure 4. On−Resistance versus Drain Current and Temperature 14 1000 1.8 1.6 6 0.20 VGS = 0 V ID = 5 A VGS = 10 V IDSS, LEAKAGE (nA) ID, DRAIN CURRENT (AMPS) 14 1.4 1.2 1 TJ = 150°C 100 TJ = 125°C 0.8 0.6 −50 −25 0 25 50 75 100 125 150 10 0 5 10 15 20 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage www.onsemi.com 3 25 NTD14N03R, NVD14N03R C, CAPACITANCE (pF) 200 TJ = 25°C VDS = 0 V VGS = 0 V Ciss 160 Crss Ciss 120 80 Coss 40 Crss 0 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) TYPICAL CHARACTERISTICS 10 VGS 0 VDS 5 5 10 15 20 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) 8 6 QT 2 ID = 5 A TJ = 25°C 0 0 IS, SOURCE CURRENT (AMPS) td(off) td(on) tf 1 1.6 2.0 10 50 40 30 TJ = 150°C 20 10 0 100 VGS = 0 V 60 TJ = 25°C 0 0.2 0.4 0.6 0.8 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current 100 ID, DRAIN CURRENT (A) t, TIME (ns) 1.2 70 tr 1 0.8 Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge VDS = 10 V ID = 5 A VGS = 10 V 10 0.4 Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation 100 VGS Q2 Q1 4 10 ms 10 100 ms 1 ms 1 0.1 0.01 10 ms 0 V < VGS < 20 V Single Pulse TA = 25°C RDS(on) Limit Thermal Limit Package Limit 0.1 dc 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 11. Maximum Rated Forward Biased Safe Operating Area www.onsemi.com 4 100 1.0 NTD14N03R, NVD14N03R TYPICAL CHARACTERISTICS 1000 R(t) (°C/W) 100 D = 0.5 0.2 0.1 0.05 0.02 1 0.01 10 0.1 SINGLE PULSE 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 t, TIME (s) Figure 12. Thermal Response ORDERING INFORMATION Package Shipping† NTD14N03RT4G DPAK (Pb−Free) 2500 / Tape & Reel NVD14N03RT4G* DPAK (Pb−Free) 2500 / Tape & Reel SVD14N03RT4G* DPAK (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NVD and SVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F 4 1 2 DATE 21 JUL 2015 3 SCALE 1:1 A E b3 C A B c2 4 L3 Z D 1 L4 2 3 NOTE 7 b2 e c SIDE VIEW b 0.005 (0.13) TOP VIEW H DETAIL A M BOTTOM VIEW C Z H L2 GAUGE PLANE C L L1 DETAIL A Z SEATING PLANE BOTTOM VIEW A1 ALTERNATE CONSTRUCTIONS ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW AYWW XXX XXXXXG IC Discrete = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 6.17 0.243 SCALE 3:1 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z XXXXXX A L Y WW G 3.00 0.118 1.60 0.063 STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON10527D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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