8402010AKIT

ICS8402010I FEMTOCLOCK™ CRYSTAL-TOLVDS/LVCMOS CLOCK GENERATOR GENERAL DESCRIPTION FEATURES ICS8402010I is a low phase noise Clock Generator ICS and is a member of the HiperClockS™ family of high HiPerClockS™ performance clock solutions from IDT. The device provides three banks of outputs and a reference clock. Each bank can be independently enabled by using output enable pins. A 25MHz, 18pF parallel resonant crystal is used to generate the 16.66MHz, 62.5MHz and 25MHz frequencies. The typical RMS phase jitter for this device is less than 1ps. • Three banks of outputs: Bank A/B: three single-ended LVCMOS outputs at 16.66MHz Bank C: three differential LVDS outputs at 62.5MHz One single-ended reference clock output at 25MHz • Crystal input frequency: 25MHz • Maximum output frequency: 62.5MHz • RMS phase jitter @ 62.5MHz, using a 25MHz crystal, Integration Range (1.875MHz - 20MHz): 0.375ps (typical) • Full 3.3V operating supply • -40°C to 85°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS6) packages BLOCK DIAGRAM 3 OE[2:0] Pullup LVCMOS - 16.66MHz QA0 ÷30 PIN ASSIGNMENT QA1 QA2 XTAL_IN LVCMOS - 16.66MHz GND VDDA OE0 OE1 OSC OE2 XTAL_IN XTAL_OUT GND 25MHz XTAL_OUT QB0 VCO Phase Detector 500MHz ÷30 QB1 32 31 30 29 28 27 26 25 QB2 VDDO_REF 1 24 VDDO_C REF_OUT 2 23 nQC2 GND 3 22 QC2 QC0 GND 4 21 nQC1 nQC0 QA0 5 20 QC1 QA1 6 19 nQC0 QA2 7 18 QC0 VDDO_A 8 17 VDDO_C ICS8402010I 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View ÷20 LVDS 62.5MHz ÷8 QC1 nQC1 QC2 nQC2 9 10 11 12 13 14 15 16 GND VDD MR GND QB2 QB1 QB0 VDDO_B LVCMOS - 25MHz IDT ™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR REF_OUT 1 ICS8402010AKI REV. A AUGUST 28, 2008 ICS8402010I FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1 VDDO_REF Power Type 2 REF_OUT Output Description Output power supply pin for REF_OUT output. Single-ended reference clock output. LVCMOS/LVTTL interface levels. 3, 4, 13, 16, 25, 32 5, 6, 7 GND Power Power supply ground. QA0, QA1, QA2 Output Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels. 8 VDDO_A Power Output power supply pin for Bank A LVCMOS outputs. 9 VDDO_B Power 10, 11, 12 QB0, QB1, QB2 Output 14 MR Input Output power supply pin for Bank B LVCMOS outputs. Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels. Master reset, resets the internal dividers. During reset, LVCMOS outputs are pulled LOW and LVDS outputs are pulled LOW and Pulldown HIGH, (QCx pulled LOW, nQCx pulled HIGH). LVCMOS/LVTTL interface levels. Core supply pin. 15 VDD Power 17, 24 VDDO_C Power 18, 19 QC0, nQC0 Output Differential Bank C clock outputs. LVDS interface levels. 20, 21 QC1, nQC1 Output Differential Bank C clock outputs. LVDS interface levels. 22, 23 QC2, nQC2 Output Differential Bank C clock outputs. LVDS interface levels. 26 VDDA Power Analog supply pin. Output power supply pin for Bank C LVDS outputs. Output enable pins. See Table 3. LVCMOS/LVTTL interface levels. 27, 28, 29 OE0, OE1, OE2 Input Pullup 30, XTAL_IN, Cr ystal oscillator interface. XTAL_OUT is the output. Input 31 XTAL_OUT XTAL_IN is the input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions CPD Power Dissipation Capacitance (per output) RPULLUP Input Pullup Resistor RPULLDOWN Input Pulldown Resistor ROUT QA[0:2], QB[0:2], REF_OUT VDD, VDDO_A = VDDO_B = VDDO_REF = 3.465V QA[0:2], QB[0:2], REF_OUT Output Impedance Minimum Typical Maximum Units 4 pF 15 pF 51 kΩ 51 kΩ 20 Ω TABLE 3. OE FUNCTION TABLE Inputs OE2 X OE1 X OE0 0 Output States QA0, QB0, QC0 disabled X X 1 QA0, QB0, QC0 enabled X 0 X QA1, QB1, QC1 disabled X 1 X QA1, QB1, QC1 enabled 0 X X QA2, QB2, QC2 disabled 1 X X QA2, QB2, QC2 enabled IDT ™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR 2 ICS8402010AKI REV. A AUGUST 28, 2008 ICS8402010I FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD NOTE: Stresses beyond those listed under Absolute Maximum 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVCMOS) -0.5V to VDDO_A, _B + 0.5V Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. 10mA 15mA Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Outputs, IO (LVDS, VDDO_C) Continuous Current Surge Current Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA Junction-to-Ambient 37.0°C/W (0 mps) Package Thermal Impedance, θJB Junction-to-Board 0.5°C/W Package Thermal Impedance, θJC Junction-to-Case 29.6°C/W TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_REF = VDDO_C = 3.3V ± 5%,TA = -40°C TO 85°C Symbol V DD Parameter Core Supply Voltage VDDA VDDO_A, VDDO_B, VDDO_C, VDDO_REF I DD Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 Units V Analog Supply Voltage VDD – 0.15 3.3 VDD V Output Supply Voltage 3.135 3.3V 3.465 V Power Supply Current 25 mA IDDA Analog Supply Current 15 mA IDDO_A + IDDO_B + IDDO_C + IDDO_REF Output Supply Current 30 mA TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_REF = 3.3V ± 5%,TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current OE0, OE1, OE2 VDD = VIN = 3.465V 5 µA MR VDD = VIN = 3.465V 150 µA IIL Input Low Current OE0, OE1, OE2 VDD = 3.465V, VIN = 0V -150 µA MR VDD = 3.465V, VIN = 0V -5 µA VOH Output High Voltage; NOTE 1 REF_OUT, QA[0:2], QB[0:2] VDDO_X = 3.465V 2.6 V Output REF_OUT, VDDO_X = 3.465V Low Voltage; NOTE 1 QA[0:2], QB[0:2] NOTE: VDDO_X denotes VDDO_A, VDDO_B and VDDO_REF. NOTE 1: Outputs terminated with 50Ω to VDDO_A, _B, _REF/2. See Parameter Measurement Information, Output Load Test Circuit diagram. VOL IDT ™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR 3 0.5 V ICS8402010AKI REV. A AUGUST 28, 2008 ICS8402010I FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR TABLE 3C. LVDS DC CHARACTERISTICS, VDD = VDDO_C = 3.3V ± 5%,TA = -40°C TO 85°C Symbol Parameter VOD Differential Output Voltage Test Conditions Δ VOD VOD Magnitude Change VOS Offset Voltage Δ VOS VOS Magnitude Change Minimum Typical Maximum Units 300 450 550 mV 50 mV 1.325 1.450 1.575 V 50 mV Maximum Units TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Mode of Oscillation Minimum Typical Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW Maximum Units NOTE: Characterized using an 18pF parallel resonant cr ystal. TABLE 5. AC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_REF = VDDO_C = 3.3V ± 5%,TA = -40°C TO 85°C Symbol fOUT Parameter Output Frequency tsk(o) Output Skew; NOTE 1, 2 tsk(b) Bank Skew; NOTE 2, 3 Test Conditions QC[0:2]/ nQC[0:2] REF_OUT QA[0:2], QB[0:2] QA[0:2], QB[0:2] QC[0:2]/ nQC[0:2] QA[0:2] Minimum Typical 62.5 MHz 25 MHz 16.66 MHz QB[0:2] RMS Phase Jitter QC[0:2]/ 62.5MHz, Integration Range: tjit(Ø) 0.375 (Random); NOTE 4 nQC[0:2] 1.875MHz – 20MHz QC[0:2]/ 20% to 80% 165 nQC[0:2] Output tR / tF Rise/Fall Time QA[0:2], 20% to 80% 450 QB[0:2] QC[0:2]/ 47 nQC[0:2] odc Output Duty Cycle QA[0:2], 45 QB[0:2] NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO_X/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. NOTE 4: Please refer to the Phase Noise Plot. IDT ™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR 4 125 ps 60 ps 100 ps 125 ps ps 450 ps 1000 ps 53 % 55 % ICS8402010AKI REV. A AUGUST 28, 2008 ICS8402010I FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR ➤ TYPICAL PHASE NOISE AT 62.5MHZ (LVDS) 62.5MHz Ethernet Filter Raw Phase Noise Data ➤ ➤ NOISE POWER dBc Hz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.375ps (typical) Phase Noise Result by adding Ethernet Filter to raw data OFFSET FREQUENCY (HZ) IDT ™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR 5 ICS8402010AKI REV. A AUGUST 28, 2008 ICS8402010I FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 1.65V±5% 1.65V±5% VDD, VDDO_A, VDDO_B, VDDO_REF SCOPE Qx VDD, VDDO_C 3.3V±5% POWER SUPPLY + Float GND – SCOPE VDDA Qx LVCMOS VDDA LVDS GND nQx -1.65V±5% 3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT 3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT Phase Noise Plot V DDO Noise Power Qx Phase Noise Mask 2 V DDO Qy f1 Offset Frequency 2 tsk(o) f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER LVCMOS OUTPUT SKEW nQCx QCx QXx VDDO 2 nQCy VDDO 2 QXy QCy tsk(b) tsk(b) Where X = A or B LVDS BANK SKEW IDT ™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR LVCMOS BANK SKEW 6 ICS8402010AKI REV. A AUGUST 28, 2008 ICS8402010I FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION, CONTINUED nQC[0:2] V DDO 2 QA[0:2], QB[0:2] QC[0:2] t PW t PW t odc = t PERIOD t PW PERIOD t PW odc = x 100% x 100% t PERIOD t PERIOD LVDS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD nQC[0:2] 80% 80% 80% 80% VOD QC[0:2] QA[0:2], QB[0:2], REF_OUT 20% 20% tR tF 20% 20% VOS tR tF GND LVDS OUTPUT RISE/FALL TIME LVCMOS OUTPUT RISE/FALL TIME VDDO VDDO 100 DC Input VOD/Δ VOD out LVDS ➤ LVDS out ➤ ➤ DC Input ➤ out out ➤ VOS/Δ VOS ➤ DIFFERENTIAL OUTPUT VOLTAGE SETUP IDT ™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR OFFSET VOLTAGE SETUP 7 ICS8402010AKI REV. A AUGUST 28, 2008 ICS8402010I FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS8402010I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO_X should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS Control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. LVCMOS OUTPUTS All unused LVCMOS output can be left floating. There should be no trace attached. IDT ™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR LVDS OUTPUTS All unused LVDS outputs should be terminated with 100Ω resistor between the differential pair. 8 ICS8402010AKI REV. A AUGUST 28, 2008 ICS8402010I FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR CRYSTAL INPUT INTERFACE The ICS8402010I has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_IN C1 27p X1 18pF Parallel Crystal XTAL_OUT C2 27p FIGURE 2. CRYSTAL INPUt INTERFACE LVCMOS TO XTAL INTERFACE (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver VDD VDD R1 Ro .1uf Rs Zo = 50 XTAL_IN R2 Zo = Ro + Rs XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER IDT ™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR 9 TO XTAL INPUT INTERFACE ICS8402010AKI REV. A AUGUST 28, 2008 ICS8402010I FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 4. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 3.3V LVDS_Driv er + R1 100 - 100 Ohm Differiential Transmission Line FIGURE 4. TYPICAL LVDS DRIVER TERMINATION VFQFN EPAD THERMAL RELEASE PATH In order to maximize both the removal of heat from the package and the electrical performance, a land patter n must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadfame Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE SOLDER LAND PATTERN THERMAL VIA PIN PIN PAD (GROUND PAD) FIGURE 5. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE) IDT ™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR 10 ICS8402010AKI REV. A AUGUST 28, 2008 ICS8402010I FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8402010I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8402010I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core and Output Power Dissipation • Power (core, output) = VDD_MAX * (IDD + IDDO_X + IDDA ) = 3.465V * (25mA + 30mA + 15mA) = 242.6mW LVCMOS Output Power Dissipation • Output Impedance ROUT Power Dissipation due to Loading 50Ω to VDDO/2 Output Current IOUT = VDDO_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 20Ω)] = 24.7mA • Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 20Ω * (24.7mA)2 = 12.25mW per output • Total Power Dissipation on the ROUT Total Power (ROUT) = 12.25mW * 6 = 73.5mW Total Power Dissipation • Total Power = Power (core, output) + Power Dissipation (ROUT) = 242.6mW + 73.5mW = 316.1mW IDT ™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR 12 ICS8402010AKI REV. A AUGUST 28, 2008 ICS8402010I FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37°C/W per Table 6. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.316W * 37°C/W = 96.7°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board. TABLE 6. THERMAL RESISTANCE θJA FOR 32-LEAD VFQFN, FORCED CONVECTION θ JA vs. Air Flow (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT ™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR 13 0 1 2.5 37.0°C/W 32.4°C/W 29.0°C/W ICS8402010AKI REV. A AUGUST 28, 2008 ICS8402010I FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN θ JA vs. Air Flow (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 37.0°C/W 32.4°C/W 29.0°C/W TRANSISTOR COUNT The transistor count for ICS8402010I is: 7782 IDT ™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR 14 ICS8402010AKI REV. A AUGUST 28, 2008 ICS8402010I FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD VFQFN NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below. TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS (VHHD -2/ -4) SYMBOL Minimum Maximum 32 N A 0.80 1. 0 A1 0 0.05 0.25 Reference A3 b 0.18 0.30 e 0.50 BASIC ND 8 NE 8 5.0 BASIC D, E D2, E2 3.0 3.3 L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 IDT ™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR 15 ICS8402010AKI REV. A AUGUST 28, 2008 ICS8402010I FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 8402010AKI ICS402010AI 32 Lead VFQFN Tray -40°C to 85°C 8402010AKIT ICS402010AI 32 Lead VFQFN 1000 Tape & Reel -40°C to 85°C 8402010AKILF ICS02010AIL 32 Lead "Lead-Free" VFQFN Tray -40°C to 85°C 8402010AKILFT ICS02010AIL 32 Lead "Lead-Free" VFQFN 1000 Tape & Reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR 16 ICS8402010AKI REV. A AUGUST 28, 2008 ICS8402010I FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support Corporate Headquarters 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT netcom@idt.com +480-763-2056 Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA