ICS841608AKIT

841608 FemtoClock® Crystal-to-HCSL Clock Generator Datasheet General Description Features The 841608 is an optimized PCIe and sRIO clock generator. The device uses a 25MHz parallel crystal to generate 100MHz and 125MHz clock signals, replacing solutions requiring multiple oscillator and fanout buffer solutions. The device has excellent phase jitter (< 1ps rms) suitable to clock components requiring precise and low-jitter PCIe or sRIO or both clock signals. Designed for telecom, networking and industrial applications, the 841608 can also drive the high-speed sRIO and PCIe SerDes clock inputs of communication processors, DSPs, switches and bridges. • Eight HCSL outputs: configurable for PCIe (100MHz) and sRIO (125MHz) clock signals • Selectable crystal oscillator interface, 25MHz, 18pF parallel resonant crystal or LVCMOS/LVTTL single-ended reference clock input • • • • • Supports the following output frequencies: 100MHz or 125MHz • • • Full 3.3V operating supply VCO: 500MHz PLL bypass and output enable PCI Express (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant RMS phase jitter at 125MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.37ps (typical) -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment 32 31 30 29 28 27 26 25 XTAL_IN 1 24 VDD XTAL_OUT 2 23 nQ7 MR/nOE 3 22 Q7 VDD 4 21 nQ6 Q0 5 20 Q6 Q3 nQ0 6 19 GND nQ3 Q1 7 18 nQ5 nQ1 8 17 Q5 nQ1 Q2 M = ÷20 nQ2 BYPASS Pulldown FSEL Q1 REF_SEL Pulldown IREF IREF ÷4 ÷5 (default) BYPASS VCO = 500MHz nQ0 ÷N VDDA 1 REF_IN REF_IN Pulldown 0 VDD FemtoClock PLL XTAL_OUT Q0 1 0 GND OSC REF_SEL XTAL_IN FSEL Pulldown Q4 nQ4 Q4 VDD nQ3 Q3 nQ2 Q2 GND nQ4 9 10 11 12 13 14 15 16 Q5 nQ5 Q6 nQ6 841608 32-Lead VFQFPN 5mm x 5mm x 0.925mm package body K Package Top View Q7 nQ7 MR/nOE Pulldown ©2020 Renesas Electronics Corporation 1 March 9, 2020 841608 Datasheet Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name 1, 2 XTAL_IN, XTAL_OUT Type Description Input Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. Active HIGH master reset. Active LOW output enable. When logic HIGH, the internal dividers are reset and the outputs are in high impedance (Hi-Z). When logic LOW, the internal dividers and the outputs are enabled. Asynchronous function. LVCMOS/LVTTL interface levels. See Table 3D. 3 MR/nOE Input 4, 14, 24, 31 VDD Power Pulldown Core supply pins. 5, 6 Q0, nQ0 Output Differential output pair. HCSL interface levels. 7, 8 Q1, nQ1 Output Differential output pair. HCSL interface levels. 9, 19, 32 GND Power Power supply ground. 10, 11 Q2, nQ2 Output Differential output pair. HCSL interface levels. 12,13 Q3, nQ3 Output Differential output pair. HCSL interface levels. 15, 16 Q4, nQ4 Output Differential output pair. HCSL interface levels. 17, 18 Q5, nQ5 Output Differential output pair. HCSL interface levels. 20, 21 Q6, nQ6 Output Differential output pair. HCSL interface levels. 22, 23 Q7, nQ7 Output 25 FSEL Input 26 IREF Output 27 BYPASS Input 28 VDDA Power 29 REF_SEL Input Pulldown Reference select. Selects the input reference source. LVCMOS/LVTTL interface levels. See Table 3A. 30 REF_IN Input Pulldown LVCMOS/LVTTL PLL reference clock input. Differential output pair. HCSL interface levels. Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels. See Table 3B. HCSL current reference resistor output. An external fixed precision resistor (475) from this pin to ground provides a reference current used for differential current-mode Qx, nQx clock outputs. Pulldown Selects PLL operation/PLL bypass operation. Asynchronous function. LVCMOS/LVTTL interface levels. See Table 3C. Analog supply pin. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 k ©2020 Renesas Electronics Corporation Test Conditions 2 Minimum Typical Maximum Units March 9, 2020 841608 Datasheet Function Tables Table 3A. REF_SEL Function Table Input REF_SEL Input Reference 0 XTAL (default) 1 REF_IN Table 3B. FSEL Function Table (fREF = 25MHz) Inputs Outputs FSEL N Divider Q[0:7], nQ[0:7] 0 5 VCO/5 (100MHz) PCIe (default) 1 4 VCO/4 (125MHz) sRIO Table 3C. BYPASS Function Table Input BYPASS PLL Configuration 0 PLL enabled (default) 1 PLL bypassed (fOUT = fREF/N) Table 3D. MR/nOE Function Table Inputs MR/nOE Function 0 Outputs enabled (default) 1 Device reset, outputs disabled (high-impedance) ©2020 Renesas Electronics Corporation 3 March 9, 2020 841608 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 37C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.15 3.3 VDD V IDD Power Supply Current 87 mA IDDA Analog Supply Current 15 mA Maximum Units Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current REF_IN, REF_SEL, BYPASS, FSEL, MR/nOE VDD = VIN = 3.465V 150 µA IIL Input Low Current REF_IN, REF_SEL, BYPASS, FSEL, MR/nOE VDD = 3.465V, VIN = 0V -5 µA Table 5. Crystal Characteristics Parameter Test Conditions Mode of Oscillation Minimum Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50  Shunt Capacitance 7 pF NOTE: Characterized using an 18pF parallel resonant crystal. ©2020 Renesas Electronics Corporation 4 March 9, 2020 841608 Datasheet AC Electrical Characteristics Table 6B. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter fMAX Output Frequency tjit(Ø) RMS Phase Jitter (Random); NOTE 1 tj Phase Jitter Peak-to-Peak; NOTE 2 tREFCLK_HF_RMS Phase Jitter RMS; NOTE 3 Test Conditions Minimum VCO/5 Typical Maximum Units 100 MHz VCO/4 125 MHz 100MHz (1.875MHz – 20MHz) 0.39 ps 125MHz (1.875MHz – 20MHz) 0.37 ps 100MHz, (1.2MHz – 50MHz 106 Samples, 25MHz Crystal Input 24.36 ps 125MHz, (1.2MHz – 62.5MHz 106 Samples, 25MHz Crystal Input 23.76 ps 100MHz, 106 Samples, 25MHz Crystal Input 2.44 ps 125MHz, 106 Samples, 25MHz Crystal Input 2.37 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 4 50 ps tsk(o) Output Skew; NOTE 4, 5 105 ps Rise Edge Rate Rising Edge Rate; NOTE 6, 7 0.6 4 V/ns Fall Edge Rate Falling Edge Rate; NOTE 6, 7 0.6 4 V/ns VRB Ringback Voltage; NOTE 6, 8 -100 100 mV VMAX Absolute Maximum Output Voltage; NOTE 9, 10 1150 mV VMIN Absolute Minimum Output Voltage; NOTE 9, 11 -300 VCROSS Absolute Crossing Voltage; NOTE 9, 12, 13 250 VCROSS Total Variation of VCROSS; NOTE 9, 12, 14 odc Output Duty Cycle; NOTE 6, 15 48 tSTABLE Power-up Stable Clock Output; NOTE 6, 8 500 tL PLL Lock Time mV 550 mV 140 mV 52 % ps 90 ms NOTE: All specifications are taken at 100MHz and 125MHz. NOTE 1: Refer to the Phase Noise Plot. NOTE 2: RMS jitter after applying system transfer function. See IDT Application Note, PCI Express Reference Clock Requirements. Maximum limit for PCI Express is 86ps peak-to-peak. NOTE 3: RMS jitter after applying system transfer function. The pole frequencies for H1 and H2 for PCIe Gen 2 are 8-16MHz and 5-16MHz. See IDT Application Note, PCI Express Reference Clock Requirements. Maximum limit for PCI Express Generation 2 is 3.1ps RMS. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 6: Measurement taken from a differential waveform. NOTE 7: Measured from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. See Parameter Measurement Information Section. NOTE 8: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB ±100 differential range. See Parameter Measurement Information Section. NOTE 9: Measurement taken from a single-ended waveform. NOTE 10: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 11: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. ©2020 Renesas Electronics Corporation 5 March 9, 2020 841608 Datasheet NOTE 12: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx. See Parameter Measurement Information Section. NOTE 13: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. See Parameter Measurement Information Section. NOTE 14: Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the VCROSS for any particular system. See Parameter Measurement Information Section. NOTE 15: Input duty cycle must be 50%. ©2020 Renesas Electronics Corporation 6 March 9, 2020 841608 Datasheet Typical Phase Noise at 100MHz Noise Power dBc Hz ? 100MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.39ps Filter ? ? Raw Phase Noise Data Phase Noise Result by adding a filter to raw data Offset Frequency (Hz) ©2020 Renesas Electronics Corporation 7 March 9, 2020 841608 Datasheet Typical Phase Noise at 125MHz ? ? Noise Power dBc Hz ? 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.37ps Filter Raw Phase Noise Data Phase Noise Result by adding a filter to raw data Offset Frequency (Hz) ©2020 Renesas Electronics Corporation 8 March 9, 2020 841608 Datasheet Parameter Measurement Information 3.3V±5% 3.3V±5% 3.3V±5% 3.3V±5% VDD Measurement Point VDD VDDA VDDA 2pF Measurement Point IREF GND 2pF 0V 0V This load condition is used for IDD, tjit and tsk(o) measurements. 3.3V HCSL Output Load AC Test Circuit 3.3V HCSL Output Load AC Test Circuit nQx Qx nQy Qy Output Skew Rise Edge Rate RMS Phase Jitter TSTABLE Fall Edge Rate VRB +150mV VRB = +100mV 0.0V VRB = -100mV -150mV +150mV 0.0V -150mV Q - nQ Q - nQ VRB TSTABLE Differential Measurement Points for Rise/Fall Time ©2020 Renesas Electronics Corporation Differential Measurement Points for Ringback 9 March 9, 2020 841608 Datasheet Parameter Measurement Information, continued Single-ended Measurement Points for Delta Cross Point Single-ended Measurement Points for Absolute Cross Point/Swing 20 0 -3dB 1.2MHz Mag (dB) -20 -3dB 21.9MHz -40 -60 -80 -100 104 105 106 107 108 Frequency (Hz) H3(s) * (H1(s) – H2(s)) Composite PCIe Transfer Function Differential Measurement Points for Duty Cycle/Period ©2020 Renesas Electronics Corporation 10 March 9, 2020 841608 Datasheet Applications Information Recommendations for Unused Input and Output Pins Inputs: Outputs: Crystal Inputs HCSL Outputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. All unused HCSL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS Control Pins All control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. REF_IN Input For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_IN to ground. Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 841608 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10µF bypass capacitor be connected to the VDDA pin. ©2020 Renesas Electronics Corporation 2.5V VDD .01µF 10Ω .01µF 10µF VDDA Figure 1. Power Supply Filtering 11 March 9, 2020 841608 Datasheet Crystal Input Interface The 841608 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_IN C1 27pF X1 18pF Parallel Crystal XTAL_OUT C2 27pF Figure 2. Crystal Input Interface LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupler capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. VDD R1 Ro Rs 0.1µf 50Ω XTAL_IN Zo = Ro + Rs R2 XTAL_OUT Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface ©2020 Renesas Electronics Corporation 12 March 9, 2020 841608 Datasheet Recommended Termination Figure 4A is the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50Ω impedance. Figure 4A. Recommended Termination Figure 4B is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same PCB. All traces should all be 50Ω impedance. Figure 4A. Recommended Termination ©2020 Renesas Electronics Corporation 13 March 9, 2020 841608 Datasheet VFQFPN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ©2020 Renesas Electronics Corporation 14 March 9, 2020 841608 Datasheet Schematic Example Figure 6 shows an example of 841608 application schematic. In this example, the device is operated at VDD = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1 = 27pF and C2 = 27pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. Two examples of HCSL terminations are shown in this schematic. The decoupling capacitors should be located as close as possible to the power pin. VDD VDD R1 VDDA 10 R2 475 C3 0.1u C4 10 u R3 33 R4 33 Zo = 50 FSEL BYPASS REF_SEL VDD X1 Zo = 50 F p 8 1 25MHz 32 31 30 29 28 27 26 25 C1 27pF - TL1 C2 27pF VDD 1 2 3 4 5 6 7 8 MR/n OE + TL2 GND VD D REF_ IN REF_SEL VDDA BYPASS I REF FSEL U1 R5 50 VDD nQ7 Q7 nQ6 Q6 GND nQ5 Q5 XTAL_IN XTAL_OUT MR/nOE VDD Q0 nQ0 Q1 nQ1 R6 50 Recommended for PCI Express Add-In Card VDD 24 23 22 21 20 19 18 17 V DD=3.3V ICS84160 8I Logic Control Input Examples Set Logic Input to '1 ' RU1 1K VDD Set Logic Input to '0' VDD VDD 9 10 11 12 13 14 15 16 GND Q2 nQ2 Q3 nQ3 VDD Q4 nQ4 HCSL Termination VDD Zo = 50 RU2 Not Ins tall - TL3 Zo = 50 To Logic Input pin s RD1 Not Inst all To Logic Input pins RD2 1K + TL4 R7 50 (U1 :6) C6 .1uf VDD (U1 :14) C7 . 1uf (U1: 24) VDD(U1:31 ) C8 . 1uf R8 50 Recommended for PCI Express Point-to-Point Connection VDD C5 0. 1u Figure 6. 841608 Application Schematic ©2020 Renesas Electronics Corporation 15 March 9, 2020 841608 Datasheet Power Considerations This section provides information on power dissipation and junction temperature for the 841608 Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 841608 is the sum of the core power plus the analog power plus the power dissipation in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipation in the load. • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (87mA + 15mA) = 353.43mW • Power (outputs)MAX = 44.5mW/Loaded Output pair If all outputs are loaded, the total power is 8 * 44.5mW = 356mW Total Power_MAX = (3.465V, with all outputs switching) = 353.43mW + 356mW = 709.43mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature for devices is 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.709W * 37°C/W = 111.2°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance JA for 32-Pin VFQFPN, Forced Convection JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ©2020 Renesas Electronics Corporation 0 1 2.5 37.0°C/W 32.4°C/W 29.0°C/W 16 March 9, 2020 841608 Datasheet 3. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 7. VDD IOUT = 17mA VOUT RREF = 475Ω ± 1% RL 50Ω IC Figure 7. HCSL Driver Circuit and Termination HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation, use the following equations which assume a 50 load to ground. The highest power dissipation occurs when VDD is HIGH. Power = (VDD_HIGH – VOUT) * IOUT, since VOUT – IOUT * RL = (VDD_HIGH – IOUT * RL) * IOUT = (3.465V – 17mA * 50) * 17mA Total Power Dissipation per output pair = 44.5mW ©2020 Renesas Electronics Corporation 17 March 9, 2020 841608 Datasheet Reliability Information Table 8. JA vs. Air Flow Table for a 32 Lead VFQFPN JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 37.0°C/W 32.4°C/W 29.0°C/W Transistor Count The transistor count for 841608 is: 2785 Package Outline Drawings The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available. www.idt.com/us/en/document/psc/32-vfqfpn-package-outline-drawing-50-x-50-x-090-mm-body-epad-315-x-315-mm-nlg32p1 Ordering Information Table 10. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 841608AKILF ICS41608AIL “Lead-Free”, 32 Lead VFQFPN Tray -40C to 85C 841608AKILFT ICS41608AIL “Lead-Free”, 32 Lead VFQFPN Tape and Reel -40C to 85C Revision History Sheet Date March 9, 2020 Description of Change • Corrected package typo in Ordering Information table. • Updated Package Outline Drawings section. • Updated Package Information. • Ordering Information Table - deleted tray count and table note. May 3, 2016 • Deleted HiperClocks references through out the datasheet. • Deleted “ICS” prefix and “I” suffix in part number. • Updated datasheet header/footer. ©2020 Renesas Electronics Corporation 18 March 9, 2020 32-VFQFPN, Package Outline Drawing 5.0 x 5.0 x 0.90 mm Body, Epad 3.15 x 3.15 mm. NLG32P1, PSC-4171-01, Rev 02, Page 1 32-VFQFPN, Package Outline Drawing 5.0 x 5.0 x 0.90 mm Body, Epad 3.15 x 3.15 mm. NLG32P1, PSC-4171-01, Rev 02, Page 2 Package Revision History Description Date Created Rev No. April 12, 2018 Rev 02 New Format Feb 8, 2016 Rev 01 Added "k: Value IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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