FemtoClock® Crystal-to- 3.3V LVPECL
Frequency Synthesizer
843252
Datasheet
General Description
Features
The 843252 is a 2 differential output LVPECL Synthesizer designed
to generate Ethernet reference clock frequencies. Using a 25MHz,
18pF parallel resonant crystal, the following frequencies can be
generated based on the settings of 4 frequency select pins
(SELA[1:0], SELB[1:0]): 625MHz, 312.5MHz, 156.25MHz, and
125MHz.
•
•
Two differential LVPECL output pairs
•
•
•
Crystal oscillator interface
•
•
•
•
Full 3.3V supply mode
The two banks have their own dedicated frequency select pins and
can be independently set for the frequencies mentioned above. The
843252 IDT’s 3rd generation low phase noise VCO technology and
can achieve 1ps or lower typical rms phase jitter, easily meeting
Ethernet jitter requirements. The 843252 is packaged in a small
16-pin TSSOP package.
Using a 25MHz crystal, the two output banks can be
independently set for 625MHz, 312.5MHz, 156.25MHz or 125MHz
VCO frequency: 490MHz – 680MHz
RMS Phase Jitter @ 156.25MHz, (1.875MHz – 20MHz) using a
25MHz crystal: 0.47ps (typical)
0°C to 70°C ambient operating temperature
Industrial temperature available upon request
Available in lead-free (RoHS 6) package
Pin Assignment
Block Diagram
SELA[0:1] Pullup
2
XTAL_IN
nQB
QB
Phase
Detector
OSC
XTAL_OUT
VCO
490MHz - 680MHz
Feedback Divider
0 = ÷25 (default)
1 = ÷32
00
01
10
11
÷1
÷2
÷3
÷4 (default)
00
01
10
11
÷2
÷4
÷5
÷8 (default)
2
©2016 Integrated Device Technology, Inc.
nQA
QB
nQB
VCCO_B
SELB1
SELB0
VCCO_A
QA
nQA
16
15
14
13
12
11
10
9
XTAL_IN
XTAL_OUT
VEE
SELA1
SELA0
VCC
VCCA
FB_SEL
843252
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
FB_SEL Pulldown
SELB[0:1] Pullup
QA
1
2
3
4
5
6
7
8
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Revision B, January 20, 2016
843252 Datasheet
Pin Description and Pin Characteristics
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2
nQB, QB
Output
Bank B differential output pair. LVPECL interface levels.
3
VCCO_B
Power
Output supply pin for QB, nQB outputs.
4,
5
SELB1,
SELB0
Input
6
VCCO_A
Power
Output supply pin for QA, nQA outputs.
7, 8
QA, nQA
Output
Bank A differential output pair. LVPECL interface levels.
9
FB_SEL
Input
10
VCCA
Power
Analog supply pin.
11
VCC
Power
Core supply pin.
12,
13
SELA0,
SELA1
Input
14
VEE
Power
Negative supply pin.
15,
16
XTAL_OUT
XTAL_IN
Input
Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output.
Pullup
Pulldown
Pullup
Division select pins for Bank B. LVCMOS/LVTTL interface levels.
Feedback divide select. When LOW, the feedback divider is set for ÷25. When HIGH,
the feedback divider is set for ÷32. LVCMOS/LVTTL interface levels.
Division select pins for Bank A. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
k
51
k
RPULLDOWN Input Pulldown Resistor
©2016 Integrated Device Technology, Inc.
2
Minimum
Typical
Maximum
Units
Revision B, January 20, 2016
843252 Datasheet
Function Tables
Table 3A. Bank A Frequency Table
Inputs
M/N
Multiplication
Factor
QA, nQA
Output
Frequency
(MHz)
FB_SEL
SELA1
SELA0
Feedback
Divider
Bank A
Output
Divider
25
0
0
0
25
1
25
625
25
0
0
1
25
2
12.5
312.5
20
0
0
1
25
2
12.5
250
22.5
0
1
0
25
3
8.333
187.5
25
0
1
1
25
4
6.25
156.25
24
0
1
1
25
4
6.25
150
20
0
1
1
25
4
6.25
125
19.44
1
0
0
32
1
32
622.08
19.44
1
0
1
32
2
16
311.04
15.625
1
0
1
32
2
16
250
18.75
1
1
0
32
3
10.667
200
19.44
1
1
1
32
4
8
155.52
18.75
1
1
1
32
4
8
150
15.625
1
1
1
32
4
8
125
Crystal Frequency
(MHz)
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843252 Datasheet
Table 3B. Bank B Frequency Table
Inputs
M/N
Multiplicatio
n Factor
QB, nQB
Output
Frequency
(MHz)
FB_SEL
SELB1
SELB0
Feedback
Divider
Bank B
Output
Divider
25
0
0
0
25
2
12.5
312.5
20
0
0
0
25
2
12.5
250
25
0
0
1
25
4
6.25
156.25
24
0
0
1
25
4
6.25
150
20
0
0
1
25
4
6.25
125
25
0
1
0
25
5
5
125
25
0
1
1
25
8
3.125
78.125
24
0
1
1
25
8
3.125
75
20
0
1
1
25
8
3.125
62.5
19.44
1
0
0
32
2
16
311.04
15.625
1
0
0
32
2
16
250
19.44
1
0
1
32
4
8
155.52
18.75
1
0
1
32
4
8
150
15.625
1
0
1
32
4
8
125
15.625
1
1
0
32
5
6.4
100
19.44
1
1
1
32
8
4
77.76
18.75
1
1
1
32
8
4
75
15.625
1
1
1
32
8
4
62.5
Crystal Frequency
(MHz)
Table 3D. Output Bank B Configuration Select
Function Table
Table 3C. Output Bank A Configuration Select
Function Table
Inputs
Outputs
Inputs
Outputs
SELA1
SELA0
QA, nQA
SELB1
SELB0
QB, nQB
0
0
÷1
0
0
÷2
0
1
÷2
0
1
÷4
1
0
÷3
1
0
÷5
1
1
÷4 (default)
1
1
÷8 (default)
Table 3E. Feedback Divider Configuration
Select Function Table
Input
FB_SEL
Feedback Divide
0
÷25 (default)
1
÷32
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843252 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuos Current
Surge Current
50mA
100mA
Package Thermal Impedance, JA
92.4C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
VCC
Core Supply Voltage
VCCA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VCC – 0.10
3.3
VCC
V
VCCO_A,
VCCO_B
Power Supply Voltage
3.135
3.3
3.465
V
ICCA
Analog Supply Current
10
mA
IEE
Power Supply Current
145
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,VCC = VCCO_A = VCCO_B = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
Input High Current
Input Low Current
Test Conditions
Minimum
Typical
Maximum
Units
2
VCC + 0.3
V
-0.3
0.8
V
FB_SEL
VCC = VIN = 3.465V
150
µA
SELA[1:0],
SELB[1:0]
VCC = VIN = 3.465V
5
µA
FB_SEL
VCC = 3.465V, VIN = 0V
-5
µA
SELA[1:0],
SELB[1:0]
VCC = 3.465V, VIN = 0V
-150
µA
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843252 Datasheet
Table 4C. LVPECL DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
Minimum
Typical
Maximum
Units
VCCO_X – 1.4
VCCO_X – 0.9
V
VCCO_X – 2.0
VCCO_X – 1.7
V
0.6
1.0
V
Maximum
Units
NOTE 1: Output termination with 50 to VCCO_A, _B – 2V.
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Fundamental
FB_SEL = ÷25
19.6
27.2
MHz
FB_SEL = ÷32
15.313
21.25
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7
pF
Drive Level
1
mW
Maximum
Units
Frequency
NOTE: Characterized using an 18pF parallel resonant crystal.
AC Electrical Characteristics
Table 6. AC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
fOUT
tsk(o)
tjit(Ø)
Parameter
Test Conditions
Minimum
Typical
Output Divider = ÷ 1
490
680
MHz
Output Divider = ÷ 2
245
340
MHz
Output Divider = ÷ 3
163.33
226.67
MHz
Output Divider = ÷ 4
122.5
170
MHz
Output Divider = ÷ 5
98
136
MHz
Output Divider = ÷8
61.25
85
MHz
Outputs @ Same Frequency
80
ps
Outputs @ Different Frequencies
190
ps
Output Frequency Range
Output Skew; NOTE 1, 2
RMS Phase Jitter, (Random);
NOTE 3
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
625MHz, (1.875MHz – 20MHz)
0.36
ps
312.5MHz, (1.875MHz – 20MHz)
0.43
ps
156.25MHz, (1.875MHz – 20MHz)
0.47
ps
125MHz, (1.875MHz – 20MHz)
0.47
ps
20% to 80%
300
700
ps
47
53
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential
cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plots.
©2016 Integrated Device Technology, Inc.
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843252 Datasheet
➝
Typical Phase Noise at 625MHz
10Gb Ethernet Filter
➝
Raw Phase Noise Data
➝
Noise Power
dBc
Hz
625MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.36ps (typical)
Phase Noise Result by adding a
10Gb Ethernet filter to raw data
Offset Frequency (Hz)
➝
Typical Phase Noise at 156.25MHz
10Gb Ethernet Filter
➝
Noise Power
dBc
Hz
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.47ps (typical)
➝
Raw Phase Noise Data
Phase Noise Result by adding a
10Gb Ethernet filter to raw data
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc.
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843252 Datasheet
Parameter Measurement Information
2V
Phase Noise Plot
Noise Power
2V
VCC,
VCCO_A,
VCCO_B V
CCA
Phase Noise Mask
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
-1.3V± 0.165V
3.3V LVPECL Output Load AC Test Circuit
RMS Phase Jitter
nQx
nQA, nQB
Qx
QA, QB
nQy
Qy
Output Skew
Output Duty Cycle/Pulse Width/Period
nQA, nQB
QA, QB
Output Rise/Fall Time
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843252 Datasheet
Application Information
Recommendations for Unused Input Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVPECL Outputs
All control pins have internal pullups and pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter per- formance,
power supply isolation is required. The 843252 provides separate
power supplies to isolate any high switching noise from the outputs to
the internal PLL. VCC, VCCA, VCCO_A, and VCCO_B should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic VCC pin and also shows that VCCA
requires that an additional 10 resistor along with a 10F bypass
capacitor be connected to the VCCA pin.
3.3V
VCC
0.01µF
VCCA
0.01µF
10µF
Figure 1. Power Supply Filtering
Crystal Input Interface
The 843252 has been characterized with 18pF parallel resonant
crystals. The capacitor values, C1 and C2, shown in Figure 2 below
were determined using a 25MHz, 18pF parallel resonant crystal and
were chosen to minimize the ppm error.
XTAL_IN
C1
22pF
X1
18pF Parallel Crystal
XTAL_OUT
C2
22pF
Figure 2. Crystal Input Interface
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843252 Datasheet
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The input
edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
VDD
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the crystal input will attenuate the signal in half. This can be done in
one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50 applications, R1 and R2
can be 100. This can also be accomplished by removing R1 and
making R2 50.
VDD
R1
Ro
Rs
0.1µf
50Ω
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
R3
125
3.3V
R4
125
3.3V
3.3V
Zo = 50
+
_
Input
Zo = 50
R1
84
Figure 4A. 3.3V LVPECL Output Termination
©2016 Integrated Device Technology, Inc.
R2
84
Figure 4B. 3.3V LVPECL Output Termination
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Revision B, January 20, 2016
843252 Datasheet
Schematic Example
Figure 5 shows an example of 843252 application schematic. In
this example, the device is operated at VCC = 3.3V. The 18pF
parallel resonant 25MHz crystal is used. The C1 = 22pF and C2 =
22pF are recommended for frequency accuracy. For different
board layouts, the C1 and C2 may be slightly adjusted for
optimizing frequency accuracy. Two examples of LVPECL
terminations are shown in this schematic. Additional termination
approaches are shown in the LVPECL Termination Application
Note.
Logic Input Pin Examples
Set Logic
Input to
'1'
VCC
Set Logic
Input to
'0'
VCC
RU1
1K
3.3V
RU2
Not Install
R1
133
Zo = 50 Ohm
To Logic
Input
pins
QA
To Logic
Input
pins
+
X1
RD2
1K
25MHz
C1
22pF
Zo = 50 Ohm
F
p
8
1
RD1
Not Install
R2
133
nQA
C2
22pF
R3
82.5
U1
VCCO_B
0.1u
C7
QB
nQB
SELB1
SELB0
QA
nQA
VCCO_A
1
2
3
4
5
6
7
8
nQB
QB
VCCO_B
SELB1
SELB0
VCCO_A
QA
nQA
XTAL_IN
XTAL_OUT
VEE
SELA1
SELA0
VCC
VCCA
FB_SEL
16
15
14
13
12
11
10
9
SELA1
SELA0
VCC
R4
82.5
Zo = 50 Ohm
QB
+
C3
FB_SEL
0.1u
Zo = 50 Ohm
nQB
0.1u
-
C4
R7
50
VCC
R8
50
R5
10
C5
0.1u
VCCA
VCC=3.3V
C6
10u
VCCO_A=3.3V
VCCO_B=3.3V
Optional
LVPECL
Y-Termination
R9
50
Figure 5. 843252 Schematic Example
©2016 Integrated Device Technology, Inc.
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843252 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 843252.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 843252 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 145mA = 502.43mW
•
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.3V, with all outputs switching) = 502.43mW + 60mW = 562.43mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature for devices is 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 92.4°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.562W * 92.4°C/W = 121.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
©2016 Integrated Device Technology, Inc.
0
1
2.5
92.4°C/W
88.0°C/W
85.9°C/W
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843252 Datasheet
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 6. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
VCCO – 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX – VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
©2016 Integrated Device Technology, Inc.
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843252 Datasheet
Reliability Information
Table 8. JA vs. Air Flow Table for a 16 Lead TSSOP
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
92.4°C/W
88.0°C/W
85.9°C/W
Transistor Count
The transistor count for 843252 is: 3822
Package Outline and Package Dimensions
Package Outline - G Suffix for 16-Lead TSSOP
Table 9. Package Dimensions for 16 Lead TSSOP
aaa C
9
A
ccc C
8
SID
0.08 C
NX L2
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
16
A
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
4.90
5.10
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
NX b2
7
bbb
C A B
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843252 Datasheet
Ordering Information
Table 10. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
843252AGLF
843252AL
16 Lead TSSOP, Lead-Free
Tube
0C to 70C
843252AGLFT
843252AL
16 Lead TSSOP, Lead-Free
Tape & Reel
0C to 70C
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843252 Datasheet
Revision History Sheet
Rev
B
Table
Page
T10
1
15
Description of Change
Date
“General Description” - deleted HiperClocks logo and reference text.
Ordering Information Table - deleted Tape & Reel count.
Deleted all HiperClocks references throughout the datasheet.
Deleted ICS prefix from part number throughout the datasheet.
Updated datasheet header/footer.
©2016 Integrated Device Technology, Inc.
16
1/19/16
Revision B, January 20, 2016
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