FemtoClock® Crystal-to-3.3V LVPECL
Clock Generator
ICS843252-04
DATA SHEET
General Description
Features
The ICS843252-04 is a 10Gb/12Gb Ethernet Clock Generator. The
ICS843252-04 can synthesize 10 Gigabit Ethernet and 12 Gigabit
Ethernet with a 25MHz crystal. It can also generate SATA and 10Gb
Fibre Channel reference clock frequencies with the appropriate
choice of crystals. The ICS843252-04 has excellent phase jitter
performance and is packaged in a small 16-pin TSSOP, making it
ideal for use in systems with limited board space.
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•
•
•
Two differential 3.3V LVPECL output pairs
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•
•
Full 3.3V supply mode
Crystal input frequency range: 20MHz – 30MHz
Output frequency range: 150MHz – 187.5MHz
VCO frequency: 600MHz – 750MHz
RMS Phase Jitter @ 156.25MHz, (1.875MHz – 20MHz):
0.31ps (typical)
0°C to 70°C ambient operating temperature
Lead-free (RoHS 6) packaging
Configuration Table with 25MHz Crystal
Inputs
Crystal Frequency
(MHz)
Feedback Divide
VCO Frequency
(MHz)
N Output Divide
Output Frequency
(MHz)
25
30
750
4
187.5
12 Gigabit Ethernet
25
25
625
4
156.25
10 Gigabit Ethernet
Application
Configuration Table with Selectable Crystals
Inputs
Crystal Frequency
(MHz)
Feedback Divide
VCO Frequency
(MHz)
N Output Divide
Output Frequency
(MHz)
20
30
600
4
150
21.25
30
637.5
4
159.375
24
25
600
4
150
25.5
25
637.5
4
159.375
10 Gigabit Ethernet
30
25
750
4
187.5
12 Gigabit Ethernet
Pullup
nPLL_SEL
Pulldown
REF_CLK
Pulldown
D
Q
LE
1
1
XTAL_IN
OSC
0
600MHz-750MHz
Q0
nQ0
÷4
VCO
Phase
Detector
0
Q1
nQ1
XTAL_OUT
CLK_SEL
Pulldown
10 Gigabit Ethernet
SATA
Pulldown
ICS843252AG-04 REVISION A MAY 15, 2013
nQ1
Q1
VCCO
OE
nPLL_SEL
VCCO
Q0
nQ0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XTAL_IN
XTAL_OUT
VEE
REF_CLK
CLK_SEL
VCC
VCCA
FREQ_SEL
ICS843252-04
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm
package body
G Package
Top View
0 = ÷25 (default)
1 = ÷30
FREQ_SEL
SATA
Pin Assignment
Block Diagram
OE
Application
1
©2013 Integrated Device Technology, Inc.
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
ICS843252-04 Data Sheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2
nQ1, Q1
Output
Differential clock output pair. LVPECL interface levels.
3, 6
VCCO
Power
Output supply pins.
4
OE
Input
Pullup
5
nPLL_SEL
Input
Pulldown
7, 8
Q0, nQ0
Output
9
FREQ_SEL
Input
10
VCCA
Power
Analog supply pin.
11
VCC
Power
Power supply pin.
12
CLK_SEL
Input
Pulldown
Clock select input. When LOW, selects the crystal inputs. When HIGH, selects
REF_CLK. LVCMOS/LVTTL interface levels.
13
REF_CLK
Input
Pulldown
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
14
VEE
Power
Negative supply pin.
15,
16
XTAL_OUT
XTAL_IN
Input
Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output.
Output enable. When HIGH, clock outputs follow clock input.
When LOW, Qx outputs are forced low, nQx outputs are forced high.
LVCMOS/LVTTL interface levels.
PLL select pin. When LOW, selects the PLL. When HIGH, bypasses the PLL.
LVCMOS/LVTTL interface levels.
Differential clock output pair. LVPECL interface levels.
Pulldown
Frequency select pin. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
RPULLUP
RPULLDOWN
Test Conditions
REF_CLK
Minimum
Typical
Maximum
Units
4
pF
Input Pullup Resistor
51
k
Input Pulldown Resistor
51
k
ICS843252AG-04 REVISION A MAY 15, 2013
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©2013 Integrated Device Technology, Inc.
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
ICS843252-04 Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V
Inputs, VI,
XTAL_IN
Other Inputs
0V to VCC
-0.5V to VCC + 0.5V
Outputs, IO
Continuos Current
Surge Current
50mA
100mA
Package Thermal Impedance, JA
81.2C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V; TA = 0°C to 70°C
Symbol
Parameter
VCC
Test Conditions
Minimum
Typical
Maximum
Units
Power Supply Voltage
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
VCC – 0.16
3.3
VCC
V
VCCO
Power Supply Voltage
3.135
3.3
3.465
V
ICC
Power Supply Current
76
mA
ICCA
Analog Supply Current
16
mA
IEE
Power Supply Current
113
mA
Table 3B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V; TA = 0°C to 70°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input
High Current
IIL
Input
Low Current
Test Conditions
Minimum
Typical
Maximum
Units
2
VCC + 0.3
V
-0.3
0.8
V
REF_CLK, CLK_SEL,
nPLL_SEL, FREQ_SEL
VCC = VIN = 3.465V
150
µA
OE
VCC = VIN = 3.465V
5
µA
REF_CLK, CLK_SEL,
nPLL_SEL, FREQ_SEL
VCC = 3.465V, VIN = 0V
-5
µA
OE
VCC = 3.465V, VIN = 0V
-150
µA
ICS843252AG-04 REVISION A MAY 15, 2013
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©2013 Integrated Device Technology, Inc.
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
ICS843252-04 Data Sheet
Table 3C. LVPECL DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V; TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
Minimum
Typical
Maximum
Units
VCCO – 1.4
VCCO – 0.9
V
VCCO – 2.0
VCCO – 1.7
V
0.55
1.0
V
NOTE 1: Output termination with 50 to VCCO – 2V.
Table 4. Crystal Characteristics
Parameter
Test Conditions
Minimum
Maximum
Units
30
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7
pF
18
pF
Mode of Oscillation
Typical
Fundamental
Frequency
20
Capacitive Loading (CL)
12
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V; TA = 0°C to 70°C
Symbol
Parameter
fOUT
Output Frequency
tjit(Ø)
RMS Phase Jitter
(Random); NOTE 1
tsk(o)
Output skew; NOTE 2, 3
t R / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
Typical
150
Maximum
Units
187.5
MHz
156.25MHz,
Integration Range: 1.875MHz – 20MHz
0.31
0.40
ps
159.375MHz,
Integration Range: 1.875MHz – 20MHz
0.31
0.35
ps
187.5MHz,
Integration Range: 1.875MHz – 20MHz
0.33
0.40
ps
5
15
ps
20% to 80%
300
600
ps
nPLL_SEL = 0
48
52
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: Characterized using crystal with CL = 18pF.
NOTE 1: Please refer to the Phase Noise plots.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoint.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
ICS843252AG-04 REVISION A MAY 15, 2013
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©2013 Integrated Device Technology, Inc.
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
ICS843252-04 Data Sheet
Typical Phase Noise at 156.25MHz
Noise Power
dBc
Hz
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.31ps (typical)
Offset Frequency (Hz)
ICS843252AG-04 REVISION A MAY 15, 2013
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©2013 Integrated Device Technology, Inc.
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
ICS843252-04 Data Sheet
Parameter Measurement Information
2V
Phase Noise Plot
VCC,
VCCO
Qx
Noise Power
2V
SCOPE
VCCA
nQx
Offset Frequency
f1
f2
RMS Phase Jitter =
1
* Area Under Curve Defined by the Offset Frequency Markers
2* *ƒ
VEE
-1.3V± 0.165V
3.3V LVPECL Output Load Test Circuit
RMS Phase Jitter
nQ0, nQ1
nQx
Q0, Q1
Qx
t PW
t
nQy
Qy
odc =
tsk(o)
PERIOD
t PW
x 100%
t PERIOD
Output Skew
LVPECL Output Duty Cycle/Pulse Width/Period
nQ0, nQ1
80%
80%
VSW I N G
Q0, Q1
20%
20%
tR
tF
Output Rise/Fall Time
ICS843252AG-04 REVISION A MAY 15, 2013
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©2013 Integrated Device Technology, Inc.
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
ICS843252-04 Data Sheet
Applications Information
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by one
side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 1A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
VCC
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50 applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and changing R2 to 50. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure 1B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
XTAL_OUT
R1
100
Ro
Rs
C1
Zo = 50 ohms
XTAL_IN
R2
100
Zo = Ro + Rs
.1uf
LVCMOS Driver
Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OUT
C2
Zo = 50 ohms
XTAL_IN
.1uf
Zo = 50 ohms
LVPECL Driver
R1
50
R2
50
R3
50
Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface
ICS843252AG-04 REVISION A MAY 15, 2013
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©2013 Integrated Device Technology, Inc.
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
ICS843252-04 Data Sheet
Recommendations for Unused Input Pins
Inputs:
Outputs:
Crystal Inputs
LVPECL Outputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
XTAL_IN to ground.
All unused LVPECL output pairs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
REF_CLK Input
For applications not requiring the use of the reference clock, it can be
left floating. Though not required, but for additional protection, a 1k
resistor can be tied from the REF_CLK to ground.
LVCMOS Control Pins
All control pins have internal pullup and pulldown resistors; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 2A and 2B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are a low impedance follower output that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
R3
125
3.3V
R4
125
3.3V
3.3V
Zo = 50
+
_
LVPECL
Input
Zo = 50
R1
84
Figure 2A. 3.3V LVPECL Output Termination
ICS843252AG-04 REVISION A MAY 15, 2013
R2
84
Figure 2B. 3.3V LVPECL Output Termination
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©2013 Integrated Device Technology, Inc.
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
ICS843252-04 Data Sheet
Schematic Example
Figure 3 (next page) shows an example of ICS843252-04 application
schematic. The schematic example focuses on functional
connections and is not configuration specific. Refer to the pin
description and functional tables in the datasheet to ensure the logic
control inputs are properly set.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS843252-04 provides
separate power supplies to isolate any high switching noise from
coupling into the internal PLL.
In this example, the device is operated VCC = VCCA = VCCO = 3.3V.
The 12pF parallel resonant 25MHz crystal is used. The load
capacitance C1 = C2 = 10pF are recommended for frequency
accuracy. Depending on the parasitic of the printed circuit board
layout, these values might require a slight adjustment to optimize the
frequency accuracy. For this device, the crystal load capacitors are
required for proper operation. Crystals with other load capacitance
specifications can be used, but will require different values for C1 and
C2.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side. The other components can be on the opposite side of the
PCB. Power supply filter recommendations are a general guideline to
be used for reducing external noise from coupling into the devices.
The filter performance is designed for wide range of noise frequency.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component with high amplitude
interference is known, such as switching power supplies frequencies,
it is recommended that component values be adjusted and if
required, additional filtering be added. Additionally general design
practice for power plane voltage stability suggests adding bulk
capacitances in the general area of all devices.
Two LVPECL terminations are shown for the outputs, one is a
standard DC termination and the other is an example of an AC
termination, typically used when connecting a 3.3V LVPECL driver to
a receiver operating at a lower supply voltage. For alternative
terminations see the IDT application note “Termination – LVPECL”.
ICS843252AG-04 REVISION A MAY 15, 2013
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©2013 Integrated Device Technology, Inc.
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
ICS843252-04 Data Sheet
Place each 0.1uF bypass cap directly adjacent
to its corresponding VCC, VCCA or VCCO pin.
3. 3V
FB1
2
VC C
1
BL M18 BB 22 1 SN 1
C6
0 . 1u F
R 1 10
C5
V CC A
C4
0. 1 uF
OE
4
nPLL _S EL
5
FR EQ_ S EL
9
OE
C LK _ SEL
12
3.3 V
C3
1 0uF
3 .3V
V CCA
VC C
U1
10
11
1 0u F
C7
0 . 1u F
3
2
VC C O
VC C O
C 10
0 . 1uF
nPL L_ SEL
VC C O
1
BL M1 8BB2 21 SN 1
C9
1 0 uF
FR E Q_S EL
C LK_ SE L
FB2
C8
0 .1 uF
6
C 11
0 .1 u F
Ro
=7 Ohm
R2
Zo = 5 0 O hm
13
R EF _C LK
Z o = 5 0 Oh m
43
Q0
7
+
LVC MOS D riv er
Z o = 5 0 Oh m
8
nQ 0
+3. 3V PE C L R ec ei v e r
R5
50
15
R4
50
XTAL_ OUT
2 5MH z ( 1 2pf )
16
C1
X1
R3
50
FOX Crystal #277LF-25-99
XTAL_ IN
C2
10 pF
2
Q1
1
nQ1
Q1
14
VE E
1 0p F
nQ 1
R 10
18 0
R 11
1 80
C 13
Z o = 50 Oh m
Q1
Logic Control Input Examples
VC C
Set Logic
Input to '1'
RU1
1K
VC C
Set Logic
Input to '0'
R8
RU2
N o t I n st a ll
To Logic
Input
pins
RD1
N ot I ns tall
VC C _R ec ei v e r
0. 0 1uF
C 14
0.01 uF
To Logic
Input
pins
C 12
R6
50
+
-
R9
R7
50
R ec e iv er
Zo = 5 0 Ohm
n Q1
RD2
1K
0.0 1u F
Alter nat e AC coupled LVPECL Termination
Select R3 and R4 t o center t he LVPECL swing in the
common mode cent er of the Receiver.
Figure 3. ICS843252-04 Schematic Layout
ICS843252AG-04 REVISION A MAY 15, 2013
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©2013 Integrated Device Technology, Inc.
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
ICS843252-04 Data Sheet
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS843252-04.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS843252-04 is the sum of the core power plus the power dissipated due to loading.
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading.
•
Power (core)MAX = VCCO_MAX * IEE_MAX = 3.465V * 113mA = 391.5mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 391.5mW + 60mW = 451.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 81.2°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.452W * 81.2°C/W = 106.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
ICS843252AG-04 REVISION A MAY 15, 2013
0
1
2.5
81.2°C/W
73.9°C/W
70.2°C/W
11
©2013 Integrated Device Technology, Inc.
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
ICS843252-04 Data Sheet
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 4. LVPECL Driver Circuit and Termination
To calculate power dissipation due to loading, use the following equations which assume a 50 load, and a termination voltage of VCCO – 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX – VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
ICS843252AG-04 REVISION A MAY 15, 2013
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©2013 Integrated Device Technology, Inc.
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
ICS843252-04 Data Sheet
Reliability Information
Table 7. JA vs. Air Flow Table for a 16 Lead TSSOP
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
81.2°C/W
73.9°C/W
70.2°C/W
Transistor Count
The transistor count for ICS843252-04 is: 2210
Package Outline and Package Dimensions
Package Outline - G Suffix for 16-Lead TSSOP
Table 8. Package Dimensions for 16 Lead TSSOP
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
16
A
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
4.90
5.10
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
ICS843252AG-04 REVISION A MAY 15, 2013
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©2013 Integrated Device Technology, Inc.
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
ICS843252-04 Data Sheet
Ordering Information
Table 9. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
843252AG-04LF
3252A04L
“Lead-Free” Lead-Free, 16 Lead TSSOP
Tube
0°C to 70°C
843252AG-04LFT
3252A04L
“Lead-Free” Lead-Free, 16 Lead TSSOP
Tape & Reel
0°C to 70°C
ICS843252AG-04 REVISION A MAY 15, 2013
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©2013 Integrated Device Technology, Inc.
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
ICS843252-04 Data Sheet
We’ve Got Your Timing Solution
6024 Silver Creek Valley Road
San Jose, California 95138
Sales
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
www.IDT.com/go/contactIDT
Technical Support
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