843252AG-45LF

FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer 843252-45 Datasheet General Description Features The 843252-45 is a 2 LVPECL output Synthesizer optimized to generate Ethernet reference clock frequencies. Using a 25MHz, 18pF parallel resonant crystal, the following frequencies can be generated: 156.25MHz and 125MHz. The 843252-45 uses IDT’s 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The 843252-45 is packaged in a small 16-pin TSSOP package. • • Two differential LVPECL output pairs • A 25MHz crystal generates output frequencies of: 156.25MHz and 125MHz • • VCO frequency: 625MHz • • • • Full 3.3V supply mode Crystal oscillator interface designed for a 25MHz, 18pF parallel resonant crystal RMS Phase Jitter @ 156.25MHz, (1.875MHz – 20MHz) using a 25MHz crystal: 0.54ps (typical) 0°C to 70°C ambient operating temperature Available in lead-free (RoHS 6) package For functional replacement part us 8T49N241 Pin Assignment Block Diagram CLK_EN_A Pullup XTAL_IN 125MHz QA 25MHz ÷5 OSC Phase Detector nQA VCO 156.25MHz QB 625MHz XTAL_OUT ÷4 nQB Feedback Divider ÷25 CLK_EN_A VEE QA nQA VCCOA nc VCCA VCC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CLK_EN_B VEE QB nQB VCCOB XTAL_IN XTAL_OUT VEE 843252-45 CLK_EN_B Pullup 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package ©2016 Integrated Device Technology, Inc. 1 Revision B, November 7, 2016 843252-45 Datasheet Table 1. Pin Descriptions Number Name Type 1 CLK_EN_A Input Description Pullup Output enable pin. LVCMOS/LVTTL interface levels. See Table 3A. 2, 9, 15 VEE Power Negative supply pins. 3, 4 QA, nQA Output Differential output pair. LVPECL interface levels. 5 VCCOA Power Output supply pin for QA/nQA outputs. 6 nc Unused 7 VCCA Power Analog supply pin. 8 VCC Power Power supply pin. 10 11 XTAL_OUT XTAL_IN Input No connect. Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output. 12 VCCOB Power Output supply pin for QB/nQB outputs. 13, 14 nQB, QB Output Differential output pair. LVPECL interface levels. 16 CLK_EN_B Input Pullup Output enable pin. LVCMOS/LVTTL interface levels. See Table 3B. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k Function Tables Table 3A. CLK_EN_A Function Table Input Table 3B. CLK_EN_B Function Table Outputs Input Outputs CLK_EN_A QA nQA CLK_EN_B QB nQB 0 LOW HIGH 0 LOW HIGH 1 (default) Active Active 1 (default) Active Active ©2016 Integrated Device Technology, Inc. 2 Revision B, November 7, 2016 843252-45 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, JA 92.4C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = VCCOA = VCCOB = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VCC Test Conditions Minimum Typical Maximum Units Power Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage VCC – 0.15 3.3 VCC V VCCOA, VCCOB Power Supply Voltage 3.135 3.3 3.465 V ICCA Analog Supply Current 15 mA IEE Power Supply Current 75 mA Maximum Units Table 4B. LVCMOS/LVTTL DC Characteristics,VCC = VCCOA = VCCOB = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage 2 VCC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current CLK_EN_A, CLK_EN_B VCC = VIN = 3.465V 5 µA IIL Input Low Current CLK_EN_A, CLK_EN_B VCC = 3.465V, VIN = 0V -150 µA Table 4C. LVPECL DC Characteristics, VCC = VCCOA = VCCOB = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VCCO – 1.4 VCCO – 0.9 V VCCO – 2.0 VCCO – 1.7 V 0.6 1.0 V NOTE 1: Output termination with 50 to VCCOA,B – 2V. ©2016 Integrated Device Technology, Inc. 3 Revision B, November 7, 2016 843252-45 Datasheet Table 5. Crystal Characteristics Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50  Shunt Capacitance 7 pF NOTE: Characterized using an 18pF parallel resonant crystal. AC Electrical Characteristics Table 6. AC Characteristics, VCC = VCCOA = VCCOB = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions fOUT Output Frequency tjit(Ø) RMS Phase Jitter (Random); NOTE 1 Minimum Typical Maximum Units QA/nQA 125 MHz QB/nQB 156.25 MHz 125MHz, Integration Range: 1.875MHz – 20MHz 0.56 ps 156.25MHz, Integration Range: 1.875MHz – 20MHz 0.54 ps t R / tF Output Rise/Fall Time odc Output Duty Cycle 20% to 80% 300 700 ps 49 51 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has been reached under these conditions. Using a 25MHz, 18pF quartz crystal. NOTE 1: Please refer to the Phase Noise plots. ©2016 Integrated Device Technology, Inc. 4 Revision B, November 7, 2016 843252-45 Datasheet ? Typical Phase Noise at 125MHz Ethernet Filter Raw Phase Noise Data ? ? Noise Power dBc Hz 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.56ps (typical) Phase Noise Result by adding an Ethernet filter to raw data Offset Frequency (Hz) ? Typical Phase Noise at 156.25MHz 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.54ps (typical) Raw Phase Noise Data ? ? Noise Power dBc Hz Ethernet Filter Phase Noise Result by adding an Ethernet filter to raw data Offset Frequency (Hz) ©2016 Integrated Device Technology, Inc. 5 Revision B, November 7, 2016 843252-45 Datasheet Parameter Measurement Information 2V Phase Noise Plot Noise Power 2V VCC, VCCOA, VCCA VCCOB Phase Noise Mask f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot -1.3V± 0.165V 3.3V LVPECL Output Load AC Test Circuit RMS Phase Jitter nQA, nQB nQA, nQB QA, QB QA, QB Output Rise/Fall Time Output Duty Cycle/Pulse Width/Period Application Information ©2016 Integrated Device Technology, Inc. 6 Revision B, November 7, 2016 843252-45 Datasheet Recommendations for Unused Input Pins Inputs: Outputs: LVCMOS Control Pins LVPECL Outputs All control pins have internal pullups; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 843252-45 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, VCCOA, and VCCOB should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VCCA pin. 3.3V VCC 0.01μF VCCA 0.01μF 10μF Figure 1. Power Supply Filtering Crystal Input Interface The 843252-45 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_IN C1 27pF X1 18pF Parallel Crystal XTAL_OUT C2 27pF Figure 2. Crystal Input Interface ©2016 Integrated Device Technology, Inc. 7 Revision B, November 7, 2016 843252-45 Datasheet LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VCC impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. VCC R1 Ro Rs 0.1µf 50Ω XTAL_IN Zo = Ro + Rs R2 XTAL_OUT Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 R3 125 3.3V R4 125 3.3V 3.3V Zo = 50 + _ Input Zo = 50 R1 84 Figure 4A. 3.3V LVPECL Output Termination ©2016 Integrated Device Technology, Inc. R2 84 Figure 4B. 3.3V LVPECL Output Termination 8 Revision B, November 7, 2016 843252-45 Datasheet Schematic Example Figure 5 shows an example of 843252-45 application schematic. In this example, the device is operated at VCC = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1 = 27pF and C2 = 27pF are recommended for frequency accuracy. For different board layouts, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. Two examples of LVPECL terminations are shown in this schematic. Additional termination approaches are shown in the LVPECL Termination Application Note. 3.3V R1 133 Zo = 50 Ohm R2 133 QA TL1 + Zo = 50 Ohm nQA U1 - TL2 CLK_ENB CLK_ENA VCCO_A 0.1u C4 VCC VCC 1 2 3 4 5 6 7 8 CLK_EN_A VEE QA nQA VCCOA nc VCCA VCC CLK_EN_B VEE QB nQB VCCO_B XTAL_IN XTAL_OUT VEE 16 15 14 13 12 11 10 9 R3 82.5 QB nQB R4 82.5 VCCO_B 0.1u C7 Zo = 50 Ohm R5 VCCA 10 C5 0.1u + C3 0.1u Zo = 50 Ohm C6 10u C1 R7 50 27pF VCC=3.3V X1 25MHz 18pF VCCO_A=3.3V Logic Input Pin Examples Set Logic Input to '1' VCC RU1 1K VCCO_B=3.3V C2 Set Logic Input to '0' VCC R8 50 Optional LVPECL Y-Termination R9 50 27pF RU2 Not Install To Logic Input pins RD1 Not Install To Logic Input pins RD2 1K Figure 5. 843252-45 Schematic Example ©2016 Integrated Device Technology, Inc. 9 Revision B, November 7, 2016 843252-45 Datasheet Power Considerations This section provides information on power dissipation and junction temperature for the 843252-45. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 843252-45 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 75mA = 259.9mW • Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.3V, with all outputs switching) = 259.9mW + 60mW = 319.9mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 92.4°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.320W * 92.4°C/W = 99.6°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 92.4°C/W 88.0°C/W 85.9°C/W 3. Calculations and Equations. ©2016 Integrated Device Technology, Inc. 10 Revision B, November 7, 2016 843252-45 Datasheet The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCCO Q1 VOUT RL 50Ω VCCO - 2V Figure 6. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCCO – 2V. • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX – VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW ©2016 Integrated Device Technology, Inc. 11 Revision B, November 7, 2016 843252-45 Datasheet Reliability Information Table 8. JA vs. Air Flow Table for a 16 Lead TSSOP JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 92.4°C/W 88.0°C/W 85.9°C/W Transistor Count The transistor count for 843252-45 is: 2039 Package Outline and Package Dimensions Package Outline - G Suffix for 16-Lead TSSOP Table 9. Package Dimensions for 16 Lead TSSOP All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75  0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ©2016 Integrated Device Technology, Inc. 12 Revision B, November 7, 2016 843252-45 Datasheet Ordering Information Table 10. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 843252AG-45LF 3252A45L “Lead-Free” 16 Lead TSSOP Tube 0C to 70C 843252AG-45LFT 3252A45L “Lead-Free” 16 Lead TSSOP Tape & Reel 0C to 70C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. Revision History Sheet Rev A A B Table Page Description of Change T10 13 Ordering Information - removed leaded devices. Updated data sheet format. 5/28/15 1 Product Discontinuation Notice - Last time buy expires November 2, 2016. PDN# CQ-15-05 11/5/15 Obsolete datasheet per PDN# CQ-15-05. Updated datasheet header/footer. 11/7/16 ©2016 Integrated Device Technology, Inc. Date 13 Revision B, November 7, 2016 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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