874003DG-02LF

Jitter Attenuator ICS874003D-02 PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016 DATA SHEET General Description Features The ICS874003D-02 is a high performance Differential-to-LVDS Jitter Attenuator. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874003D-02 has a bandwidth of 3MHz. The 3MHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. • • • Three differential LVDS output pairs • • • • • • • • • Input frequency range: 98MHz to 128MHz The ICS874003D-02 uses IDT’s 3rd Generation FemtoClock® PLL technology to achieve the lowest possible phase noise. The device is packaged in a 20-Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-on cards. One differential clock input CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, HCSL Output frequency range: 98MHz to 320MHz VCO range: 490MHz - 640MHz Cycle-to-Cycle jitter: 30ps (maximum) 3MHz PLL loop bandwidth 0°C to 70°C ambient operating temperature Full 3.3V operating supply Lead-free (RoHS 6) packaging For drop-in replacement use 874003AG-02 Pin Assignment F_SEL[2:0] Function Table Inputs Outputs F_SEL2 F_SEL1 F_SEL0 QA[0:1], nQA[0:1] QB0, nQB0 0 0 0 ÷2 (default) ÷2 (default) 1 0 0 ÷5 ÷2 0 1 0 ÷4 ÷2 1 1 0 ÷2 ÷4 0 0 1 ÷2 ÷5 1 0 1 ÷5 ÷4 0 1 1 ÷4 ÷5 1 1 1 ÷4 ÷4 ICS874003DG-02 REVISION A MARCH 11, 2016 QA1 VDDO QA0 nQA0 MR F_SEL0 nc VDDA F_SEL1 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nQA1 VDDO QB0 nQB0 F_SEL2 OEB GND nCLK CLK OEA ICS874003D-02 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View 1 ©2016 Integrated Device Technology, Inc. ICS874003D-02 Data Sheet JITTER ATTENUATOR Block Diagram OEA F_SEL2:0 Pullup Pulldown 3 QA0 ÷5 ÷4 ÷2 (default) nQA0 QA1 CLK nCLK Pulldown Pullup Phase Detector VCO nQA1 490 - 640MHz 3 ÷5 ÷4 ÷2 (default) M = ÷5 (fixed) MR OEB QB0 nQB0 Pulldown Pullup ICS874003DG-02 REVISION A MARCH 11, 2016 2 ©2016 Integrated Device Technology, Inc. ICS874003D-02 Data Sheet JITTER ATTENUATOR Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1, 20 QA1, nQA1 Output Differential output pair. LVDS interface levels. 2, 19 VDDO Power Output supply pins. 3, 4 QA0, nQA0 Output Differential output pair. LVDS interface levels. 5 MR Input Pulldown Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (Qx) to go low and the inverted outputs (nQx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 6, 9, 16 F_SEL0, F_SEL1, F_SEL2 Input Pulldown Frequency select pin for QAx, nQAx and QB0, nQB0 outputs. LVCMOS/LVTTL interface levels. 7 nc Unused 8 VDDA Power Analog supply pin. 10 VDD Power Core supply pin. 11 OEA Input Pullup 12 CLK Input Pulldown 13 nCLK Input Pullup 14 GND Power 15 OEB Input 17, 18 nQB0, QB0 Output No connect. Output enable pin for QAx pins. When HIGH, the QAx, nQAx outputs are active. When LOW, the QAx, nQAx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Non-inverting differential clock input. Inverting differential clock input. Power supply ground. Pullup Output enable pin for QB0 pins. When HIGH, the QB0, nQB0 outputs are active. When LOW, the QB0, nQB0 outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k Function Table Table 3. Output Enable Function Table Inputs Outputs OEA OEB QA[0:1], nQA[0:1] QB0, nQB0 0 0 Hi-Impedance Hi-Impedance 1 1 Enabled Enabled ICS874003DG-02 REVISION A MARCH 11, 2016 3 ©2016 Integrated Device Technology, Inc. ICS874003D-02 Data Sheet JITTER ATTENUATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA 86.7°C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. LVDS Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.15 3.3 VDD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 80 mA IDDA Analog Supply Current 15 mA IDDO Output Supply Current 75 mA Maximum Units Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current IIL Input Low Current OEA, OEB VDD = VIN = 3.465V 5 µA MR, F_SEL[2:0] VDD = VIN = 3.465V 150 µA OEA, OEB VDD = 3.465V, VIN = 0V -150 µA MR, F_SEL[2:0] VDD = 3.465V, VIN = 0V -5 µA ICS874003DG-02 REVISION A MARCH 11, 2016 4 ©2016 Integrated Device Technology, Inc. ICS874003D-02 Data Sheet JITTER ATTENUATOR Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical Maximum Units CLK VDD = VIN = 3.465V 150 µA nCLK VDD = VIN = 3.465V 5 µA CLK VDD = 3.465V, VIN = 0V -5 µA nCLK VDD = 3.465V, VIN = 0V -150 µA 0.15 1.3 V GND + 0.5 VDD – 0.85 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4D. LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 275 375 485 mV 50 mV 1.5 V 50 mV Maximum Units 320 MHz 1.2 1.35 Table 5. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter fOUT Output Frequency Test Conditions Minimum tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 30 ps tsk(o) Output Skew; NOTE 2, 3 185 ps 98 tsk(b) Bank Skew; NOTE 1, 4 Bank A tR / tF Output Rise/Fall Time 20% to 80% odc Output Duty Cycle Typical 65 ps 250 700 ps 47 53 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoints. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. ICS874003DG-02 REVISION A MARCH 11, 2016 5 ©2016 Integrated Device Technology, Inc. ICS874003D-02 Data Sheet JITTER ATTENUATOR Parameter Measurement Information VDD 3.3V ±5% VDD, VDDO nCLK VDDA V V Cross Points PP CMR CLK GND Differential Input Level 3.3V LVDS Output Load Test Circuit nQA0 nQA[0:1], nQB0 QA0 QA[0:1], QB0 nQA1 tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles QA1 tsk(b) Cycle-to-Cycle Jitter Bank Skew nQx nQA[0:1], nQB0 Qx QA[0:1], QB0 nQy Qy Output Duty Cycle/Pulse Width/Period Output Skew ICS874003DG-02 REVISION A MARCH 11, 2016 6 ©2016 Integrated Device Technology, Inc. ICS874003D-02 Data Sheet JITTER ATTENUATOR Parameter Measurement Information, continued nQA[0:1], nQB0 80% 80% VOD QA[0:1], QB0 20% 20% tR tF Output Rise/Fall Time Offset Voltage Setup Differential Output Voltage Setup ICS874003DG-02 REVISION A MARCH 11, 2016 7 ©2016 Integrated Device Technology, Inc. ICS874003D-02 Data Sheet JITTER ATTENUATOR Applications Information Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage V1= VCC/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set V1 at 1.25V. The values below are for when both the single ended swing and VCC are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS874003DG-02 REVISION A MARCH 11, 2016 8 ©2016 Integrated Device Technology, Inc. ICS874003D-02 Data Sheet JITTER ATTENUATOR Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, HCSL and other differential signals. The differential signal must meet the VPP and VCMR input requirements. Figures 2A to 2D show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. Figure 2A. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 2B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V *R3 CLK nCLK HCSL *R4 Differential Input Figure 2D. CLK/nCLK Input Driven by a 3.3V LVDS Driver Figure 2C. CLK/nCLK Input Driven by a 3.3V HCSL Driver ICS874003DG-02 REVISION A MARCH 11, 2016 9 ©2016 Integrated Device Technology, Inc. ICS874003D-02 Data Sheet JITTER ATTENUATOR Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins LVDS Outputs All control pins have internal pullup or pulldown resistors; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached. LVDS Driver Termination For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The LVDS Driver standard termination schematic as shown in Figure 3A can be used with either type of output structure. Figure 3B, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output. ZO  ZT ZT LVDS Receiver Figure 3A. Standard Termination LVDS Driver ZO  ZT C ZT 2 LVDS ZT Receiver 2 Figure 3B. Optional Termination LVDS Termination ICS874003DG-02 REVISION A MARCH 11, 2016 10 ©2016 Integrated Device Technology, Inc. ICS874003D-02 Data Sheet JITTER ATTENUATOR Schematic Layout Figure 4 shows an example of ICS874003D-02 application schematic. This example focuses on functional connections and is not configuration specific. In this example, the device is operated at VDD = VDDO = 3.3V. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. For the LVDS output drivers, two termination examples are shown in the schematic. possible.This is represented by the placement of these capacitors in the schematic. If space is limited, the ferrite beads, 10µF and 0.1µF capacitor connected to the board supplies can be placed on the opposite side of the PCB. If space permits, place all filter components on the device side of the board. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10 kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS874003D-02 provides separate VDD, VDDA and VDDO power supplies to isolate any high switching noise from coupling into the internal oscillator. In order to achieve the best possible filtering, it is highly recommended that the 0.1uF capacitors on the device side of the ferrite beads be placed on the device side of the PCB as close to the power pins as QA0 Logic Contr ol Input Exam ples Zo = 50 Ohm V DD Set Logic Input to '1' RU1 1K + Set Logic Input to '0' VD D R1 1 00 - R U2 N ot In s ta ll nQA 0 Zo = 50 Ohm To Logic Input pins VD D O To Logic Input pins RD1 N ot I n st a ll QA1 nQA1 VD D O R D2 1K U1 MR F_S EL 0 R2 V DD A F_S EL 1 10 C1 0. 1u F C2 1 0uF QA1 VD D O QA0 nQA 0 MR F_ SEL0 nc VD D A F_ SEL1 VD D n Q A1 V DD O QB0 n Q B0 F_ SE L2 OE B GN D n C LK C LK OE A 20 19 18 17 16 15 14 13 12 11 1 3.3 V B LM1 8BB2 21SN 1 C5 0. 1u F C4 0.1uF 1 2 3 4 5 6 7 8 9 10 FB 1 2 C9 10u F C8 0 . 1uF V DD O QB0 n QB0 F _S EL2 OEB GN D OEA Zo = 5 0 Oh m C7 0 . 1uF V DD R4 50 3.3 V 1 FB2 2 C LK BLM18 BB 22 1SN 1 C1 0 0 .1 uF + Zo = 50 Ohm C6 1 0uf Zo = 50 Ohm C3 0.1u F R5 50 - nCLK LVPE C L D ri v er R6 50 R7 50 R8 50 Zo = 5 0 Oh m Alternate LVDS Termination Figure 4. ICS874003D-02 Schematic Layout ICS874003DG-02 REVISION A MARCH 11, 2016 11 ©2016 Integrated Device Technology, Inc. ICS874003D-02 Data Sheet JITTER ATTENUATOR Power Considerations This section provides information on power dissipation and junction temperature for the ICS874003D-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS74003D-02 is the sum of the core power plus the analog power plus the power dissipated due to the load. The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (80mA + 15mA) = 329.175mW • Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 75mA = 259.87mW Total Power_MAX = 329.175mW + 259.87mW = 589.045mW • 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 86.7°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.589W * 86.7°C/W = 121.1°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 20-Lead TSSOP, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS874003DG-02 REVISION A MARCH 11, 2016 0 1 2.5 86.7°C/W 82.4°C/W 80.2°C/W 12 ©2016 Integrated Device Technology, Inc. ICS874003D-02 Data Sheet JITTER ATTENUATOR Reliability Information Table 7. JA vs. Air Flow Table for a 20-Lead TSSOP JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 86.7°C/W 82.4°C/W 80.2°C/W Transistor Count The transistor count for ICS874003D-02 is: 1408 Package Outline and Package Dimensions Package Outline - G Suffix for 20-Lead TSSOP Table 8. Package Dimensions Symbol N A A1 A2 b c D E E1 e L  aaa All Dimensions in Millimeters Minimum Maximum 20 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 6.40 6.60 6.40 Basic 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS874003DG-02 REVISION A MARCH 11, 2016 13 ©2016 Integrated Device Technology, Inc. ICS874003D-02 Data Sheet JITTER ATTENUATOR Ordering Information Table 9. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 874003DG-02LF ICS74003D02L “Lead-Free” 20-Lead TSSOP Tube 0C to 70C 874003DG-02LFT ICS74003D02L “Lead-Free” 20-Lead TSSOP Tape & Reel 0C to 70C Revision History 3/11/16 Product Discontinuation Notice - Last time buy expires September 7, 2016. PDN N-16-02 ICS874003DG-02 REVISION A MARCH 11, 2016 14 ©2016 Integrated Device Technology, Inc. ICS874003D-04 Data Sheet JITTER ATTENUATOR We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support Sales clocks@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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