8INT31H800ANLGI8

8-Output Very Low Phase Jitter HCSL Fanout Buffer 8INT31H800A DATA SHEET General Description Features/Benefits The 8INT31H800A is an 8-output very high performance HCSL fanout buffer for High Performance Interconnect applications. It can also be used at speeds up to 350MHz. There are four OE pins on the device, each controlling two outputs. • Extremely low additive phase jitter; supports DB800H requirements • 3.3V operation; standard industry power supply • Four OE pins each controlling two outputs; easy control of clocks to CPU sockets Recommended Application DB800H • Universal differential input; can be driven by HCSL or LVPECL clock sources Output Features • 1MHz to 350MHz operating frequency; covers all popular Ethernet frequencies • Eight HCSL differential pairs • Space saving 32-pin 5x5mm VFQFN; minimal board space Key Specifications • Qx output-to-output skew within a pair: 22ps (typical) • Qx output-to-output skew across all outputs: 32ps (typical) • RMS additive phase jitter: 65fs (typical) Q(2:3) nCLK_IN CLK_IN vOE_23# vOE_01# IREF GNDO VDDO3.3 vOE_23# vOE_45# Q(0:1) GNDO vOE_01# VDDO3.3 Pin Assignment Block Diagram 32 31 30 29 28 27 26 25 Q0 1 24 Q4 nQ0 2 23 nQ4 Q1 3 22 Q5 nQ1 4 21 nQ5 Q2 5 20 Q6 nQ2 6 19 nQ6 Q3 7 18 Q7 nQ3 8 17 nQ7 Q(4:5) 12 13 14 15 16 VDD3.3 GNDO VDDO3.3 11 GND 10 nCLK_IN 9 CLK_IN vOE_67# vOE_67# Q(6:7) 8INT31H800A VDDO3.3 vOE_45# 32-pin, 5mm x 5mm VFQFN Package v prefix indicates internal 50kΩ pull-down resistor 8INT31H800A REVISION 2 12/09/14 1 ©2014 Integrated Device Technology, Inc. 8INT31H800A DATA SHEET Pin Descriptions and Characteristics Table 1. Pin Descriptions Pin# Name Type 1 Q0 Output Non-inverting output of Differential Pair 0. 2 nQ0 Output Inverting output of Differential Pair 0. 3 Q1 Output Non-inverting output of Differential Pair 1. 4 nQ1 Output Inverting output of Differential Pair 1. 5 Q2 Output Non-inverting output of Differential Pair 2. 6 nQ2 Output Inverting output of Differential Pair 2. 7 Q3 Output Non-inverting output of Differential Pair 3. 8 nQ3 Output Inverting output of Differential Pair 3. 9 VDDO3.3 Power Power supply for outputs, nominal 3.3V. 10 vOE_67# Input 11 CLK_IN Input 12 nCLK_IN Input Complementary Input for differential reference clock. 13 GND GND Ground pin. 14 VDD3.3 Power Power supply, nominal 3.3V. 15 GNDO GND Ground pin for outputs. 16 VDDO3.3 Power Power supply for outputs, nominal 3.3V. 17 nQ7 Output Inverting output of Differential Pair 7. 18 Q7 Output Non-inverting output of Differential Pair 7. 19 nQ6 Output Inverting output of Differential Pair 6. Pulldown Pin Description Active Low input for enabling outputs 6 and 7.  0 = enable outputs, 1 = disable outputs True Input for differential reference clock. 20 Q6 Output Non-inverting output of Differential Pair 6. 21 nQ5 Output Inverting output of Differential Pair 5. 22 Q5 Output Non-inverting output of Differential Pair 5. 23 nQ4 Output Inverting output of Differential Pair 4. 24 Q4 Output Non-inverting output of Differential Pair 4. 25 VDDO3.3 Power Power supply for outputs, nominal 3.3V. 26 GNDO GND Ground pin for outputs. 27 IREF Output 28 vOE_01# Input Pulldown 29 vOE_23# Input Pulldown 30 vOE_45# Input Pulldown This pin establishes the reference for the differential current-mode output pairs. It requires a fixed precision resistor to ground. 475 is the standard value for 100 differential impedance. Other impedances require different values. See data sheet. Active Low input for enabling outputs 0 and 1.  0 = enable outputs, 1 = disable outputs Active Low input for enabling outputs 2 and 3 0 = enable outputs, 1 = disable outputs Active Low input for enabling outputs 4 and 5. 0 = enable outputs, 1 = disable outputs 31 GNDO GND Ground pin for outputs. 32 VDDO3.3 Power Power supply for outputs, nominal 3.3V. 8-OUTPUT VERY LOW PHASE JITTER HCSL FANOUT BUFFER 2 REVISION 2 12/09/14 8INT31H800A DATA SHEET Table 2A. Output Enable (OE) Functionality Table1 CLK_IN vOE_x# Pin Qx Table 2B. Power Connections1 nQx 2 Running 1 Low Low Running 0 Running Not Running X X Pin Number 2 VDDx GND Running 14 13 X 9, 16, 25, 32 15, 26, 31 NOTE 1: vOE_X# denotes: vOE_01#, vOE_23#, vOE_45#, vOE67#. NOTE 2: The outputs are tristated and the termination networks pulls them low. REVISION 2 12/09/14 Description Core Power Supply Output Power Supply NOTE 1: VDDx denotes either VDD3.3 or VDDO3.3. 3 8-OUTPUT VERY LOW PHASE JITTER HCSL FANOUT BUFFER 8INT31H800A DATA SHEET Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 8INT31H800A. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Symbol Parameter Test Conditions Minimum Typical 1 VDDx 3.3V Supply Voltage VIL Input Low Voltage VIH Input High Voltage Storage Temperature TJ Junction Temperature ESD (HBM) ESD (CDM) Units 3.6 V GND - 0.5 V Outputs (VO) TS Maximum -65 ESD protection2 3.6 V 3.6 V 150 °C 125 °C Human Body Model 2000 V Charged Device Model 1000 V NOTE 1: VDDx denotes either VDD3.3 or VDDO3.3. NOTE 2: According to JEDEC/JS-001-2012/JESD22-C101E. Electrical Characteristics Table 3A. Input/Supply/Common Parameters,  Supply Voltage VDDx1 = 3.3 V ±5%, TA = TIND2 Symbol Parameter Test Conditions Minimum Typical Maximum Units TIND Ambient Operating Temperature Industrial Range -40 25 85 °C VIH Input High Voltage vOE_01#, vOE_23# vOE_45#, vOE_67# 2.2 VDD3.3 + 0.3 V VIL Input Low Voltage vOE_01#, vOE_23# vOE_45#, vOE_67# GND - 0.3 0.8 V IIH Input High Current vOE_01#, vOE_23# vOE_45#, vOE_67# VDD3.3 = VIN = 3.465V 150 A IIL Input Low Current vOE_01#, vOE_23# vOE_45#, vOE_67# VDD3.3 = 3.465V, VIN = 0V Fmax Maximum Input Frequency3 Lpin Pin Inductance 1 350 MHz 7 nH vOE_01#, vOE_23# vOE_45#, vOE_67# 5 pF CLK_IN, nCLK_IN 3 pF Output Pin Capacitance 6 pF 12 clocks CIN CINDIF_IN Capacitance COUT tLATOE OE# Latency 4 A -5 Input Clock must be running 4 NOTE 1: VDDx denotes either VDD3.3 or VDDO3.3. NOTE 2: Guaranteed by design and characterization, not 100% tested in production. NOTE 3: Signal edge is required to be monotonic when transitioning through this region. NOTE 4: Time from de-assertion until outputs are stopped or time from assertion until outputs are running. 8-OUTPUT VERY LOW PHASE JITTER HCSL FANOUT BUFFER 4 REVISION 2 12/09/14 8INT31H800A DATA SHEET Table 3B. Clock Input Parameters, Supply Voltage VDDx1 = 3.3 V ±5%, TA = TIND, Symbol Parameter Test Conditions VPP Peak-to-Peak Voltage CLK_IN, nCLK_IN VCMR Common Mode  Input Voltage2, 3 CLK_IN, nCLK_IN dv/dt Input Slew Rate4 IIN Input Leakage Current dtin Input Duty Cycle Minimum Typical Maximum Units 0.3 1.0 V GND + 0.3 VDD3.3 - 1 V Measured Differentially 0.4 8 V/ns VIN = VDD3.3 , VIN = GND -5 5 A Measurement from Differential Waveform 40 60  NOTE 1: VDDx denotes either VDD3.3 or VDDO3.3. NOTE 2: Common mode voltage is defined as the crosspoint. NOTE 3: Input voltage cannot be less than GND - 300mV or more than VDD3.3. NOTE 4: Slew rate measured through ±75mV window centered around differential zero. Table 3C. Qx HCSL Differential Outputs, Supply Voltage VDDx1= 3.3 V ±5%, TA = TIND Symbol Parameter Test Conditions Slew Rate ΔTrf Rise/Fall Time Matching4 VHIGH Voltage High5 VLow Voltage Low5 Vmin Max. Voltage5 Min. Voltage5 Crossing Voltage Units 4 V/ns 20 % 650 875 mV -150 150 mV Rise/Fall Time Matching Statistical Measurement on Single-ended Signal using Oscilloscope Math Function Measurement on Single-ended Signal using Absolute Value Vcross_abs Crossing Voltage (abs)6 Δ-Vcross Maximum 0.6 dv/dt Vmax Minimum 2, 3 1150 -300 240 (var)5, 7 Typical mV 550 mV 140 mV NOTE 1: VDDx denotes either VDD3.3 or VDDO3.3. NOTE 2: Measured from differential waveform. NOTE 3: Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a ±150mV window  around differential 0V. NOTE 4: Rise/Fall matching derived using the following, 2*(TRISE - TFALL) / (TRISE + TFALL) NOTE 5: Measured from single-ended waveform. NOTE 6: Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). NOTE 7: The total variation of all Vcross measurements in any system. Note that this is a subset of V_cross_min/max (V_cross absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute. NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500ppm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Guaranteed by design and characterization, not 100% tested in production. REVISION 2 12/09/14 5 8-OUTPUT VERY LOW PHASE JITTER HCSL FANOUT BUFFER 8INT31H800A DATA SHEET Table 3D. Current Consumption, Supply Voltage VDDx1 = 3.3V ±5%, TA = TIND Test Conditions Minimum Typical Maximum Units All outputs running @ 350MHz 191 225 mA 2 outputs running @ 350MHz other outputs disabled. 84 100 mA All outputs stopped, input clock running @ 350MHz or stopped. 34 40 mA NOTE 1: VDDx denotes either VDD3.3 or VDDO3.3. Table 3E. Qx Output Duty Cycle, Jitter, and Skew Characteristics, Supply Voltage VDDx1, 2 = 3.3 V ±5%, TA = TIND Symbol Parameter Test Conditions Minimum tOCD Output Duty Cycle3 Measured Differentially tPD Skew, Input to Output VT = 50% tSKEWpair Skew, Output to Output Between Two Output Pairs Controlled by Same OE Pin, VT = 50% tsk3 Skew, Output to Output Across all Outputs, VT = 50% tjcyc-cycadd Jitter, Cycle to Cycle Additive4 Across all Outputs, VT = 50% fOUT = 156.25MHz Typical Maximum Units 45 55 % 1 1.6 ns 38 ps 80 ps 50 ps Typical Maximum Units 65 75 fs (RMS) 32 NOTE 1: VDDx denotes either VDD3.3 or VDDO3.3. NOTE 2: Guaranteed by design and characterization, not 100% tested in production. NOTE 3: Input duty cycle = 50% NOTE 4: Measured from differential waveform. Table 3F. Additive Phase Jitter, Supply Voltage VDDx = 3.3 V ±5%, TA = TIND1 2 3 Symbol Parameter tjph Additive Phase Jitter Test Conditions fOUT = 156.25MHz, All Outputs Running, Integration Range: 12kHz to 20MHz Minimum NOTE 1: Applies to all output NOTE 2: Signal Source Wenzel Oscillator. NOTE 3: For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)2 – (input jitter)2] 8-OUTPUT VERY LOW PHASE JITTER HCSL FANOUT BUFFER 6 REVISION 2 12/09/14 8INT31H800A DATA SHEET HCSL Test Loads Table 3G. Differential Output Termination Table1 DIF Zo (Ω) IREF (Ω) Rs (Ω) Rp (Ω) 100 475 33 50 85 412 27 42.2 or 43.2 NOTE 1: It is recommended to use the components for differential output impedance of 85 for optimal performance. 10 inches Rs Differential Zo 2pF Rs Rp 2pF Rp HCSL Output Buffer Figure 1. HCSL Test Load REVISION 2 12/09/14 7 8-OUTPUT VERY LOW PHASE JITTER HCSL FANOUT BUFFER 8INT31H800A DATA SHEET Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio SSB Phase Noise dBc/Hz of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Additive Phase Jitter @ 156.25MHz 12kHz to 20MHz = 65fs (typical) Offset from Carrier Frequency (Hz) As with most timing specifications, phase noise measurements have issues relating to the limitations of the measurement equipment. The noise floor of the equipment can be higher or lower than the noise floor of the device. Additive phase noise is dependent on both the noise floor of the input source and measurement equipment. 8-OUTPUT VERY LOW PHASE JITTER HCSL FANOUT BUFFER The source generator used is, low noise Wenzel Oscillator at 156.25MHz, and the additive phase jitter for this device was measured using an Agilent E5052 Phase Noise Analyzer. 8 REVISION 2 12/09/14 8INT31H800A DATA SHEET Parameter Measurement Information SCOPE VDD3.3, VDDO3.3 42.5Ω Qx VDD3.3, VDDO3.3 2pF 42.5Ω IREF HCSL nQx IREF GND GND 2pF 0V 0V 0V This load condition is used for tjit(cc), tjit and tsk(o), tsk(pp) and tPD measurements. This load condition is used for IDD, VMAX, VMIN, VRB, tSTABLE, VCROSS, VCROSS and Rise/Fall Edge Rate measurements. 3.3V Core/3.3V HCSL Output Load AC Test Circuit 3.3VCore/3.3V HCSL Output Load AC Test Circuit VDD nCLK_IN CLK_IN GND Differential Input Level Differential Measurement Points for Duty Cycle/Period Single-ended Measurement Points for Absolute Cross Point/Swing Single-ended Measurement Points for Delta Cross Point REVISION 2 12/09/14 9 8-OUTPUT VERY LOW PHASE JITTER HCSL FANOUT BUFFER 8INT31H800A DATA SHEET Parameter Measurement Continued... Differential Measurement Points for Rise/Fall Time Edge Rate 8-OUTPUT VERY LOW PHASE JITTER HCSL FANOUT BUFFER Differential Measurement Points for Ringback 10 REVISION 2 12/09/14 8INT31H800A DATA SHEET Applications Information Differential Clock Input Interface The 8INT31H800A differential clock input CLK_IN/nCLK_IN accepts HCSL, LVPECL, LVHSTL and other types of differential signal. The differential input signal must meet both Vswing (amplitude) and Vcom (DC offset) input requirement. The CLK_IN and nCLK_IN of this part is high input impedance without internal built-in termination. The termination requirement will depend on the driver type. Please consult with the vendor of the driver component to confirm the driver termination requirement. Figure 2A to Figure 2E show interface examples for the CLK_IN/nCLK_IN input driven by the most common driver types. 3.3V 3.3V 3.3V 3.3V R3 33 R4 Zo = 50 CLK_IN Zo = 50 nCLK_IN 33 Zo = 50 CLK_IN Zo = 50 nCLK_IN LVPECL Driv er R1 50 R2 50 8INT31H800 HCSL Driv er R1 50 R2 50 8INT31H800 R3 50 Figure 2A. 8INT31H800A Clock Input Driven by a HCSL Driver Example 1 Figure 2D. 8INT31H800A Clock Input M Driven by an LVPECL Driver Example 1 3.3V 3.3V 3.3V 3.3V 3.3V R3 R3 133 33 Zo = 50 R4 R1 133 CLK_IN Zo = 50 CLK_IN 33 Zo = 50 nCLK_IN Zo = 50 nCLK_IN HCSL Driv er R1 50 R2 50 LVPECL Driv er 8INT31H800 Figure 2B. 8INT31H800A Clock Input Driven by a HCSL Driver Example 2 R2 82.5 R4 82.5 8INT31H800 Figure 2E. 8INT31H800A Clock Input Driven by an LVPECL Driver Example 2 3.3V 1.8V to 3.3V Zo = 50 CLK_IN Zo = 50 nCLK_IN Open source LVHSTL Driv er R1 50 R2 50 8INT31H800 Figure 2C. 8INT31H800A Clock Input Driven by an Open Source LVHSTL Driver REVISION 2 12/09/14 11 8-OUTPUT VERY LOW PHASE JITTER HCSL FANOUT BUFFER 8INT31H800A DATA SHEET Power Considerations This section provides information on power dissipation and junction temperature for the 8INT31H800A.  Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 8INT31H800A is the sum of the core power plus the power dissipation in the load(s).  The following is the power dissipation for VDD3.3 = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. The maximum current at 85°C is as follows: IDD3.3_MAX = 195mA IDDO3.3_MAX = 30mA Power (core)MAX = VDD3.3_MAX * (IDD3.3_MAX + IDDO3.3_MAX) = 3.465V * 225mA = 779.625mW • Power (Output)MAX = 38.82mW/Loaded Output pair  If all outputs are loaded, the total power is 8 * 38.82mW = 310.56mW Total Power = 779.625mW + 310.56mW = 1090.18mW 2. Junction Temperature. Junction temperature, TJ, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, TJ, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for TJ is as follows: TJ = JA * Pd_total + TA TJ = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 33.1°C/W per Table 4 below. Therefore, TJ for an ambient temperature of 85°C with all outputs switching is: 85°C + 1.09W * 33.1°C/W = 121.1°C. This is below the limit of 125°C. This calculation is only an example. TJ will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 4. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 8-OUTPUT VERY LOW PHASE JITTER HCSL FANOUT BUFFER 0 1 2.5 33.1°C/W 28.1°C/W 25.4°C/W 12 REVISION 2 12/09/14 8INT31H800A DATA SHEET 3. Calculations and Equations The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 3. VDDO3. 3V 17mA RS 27 Vout Q IREF Rref 412 RL IC 42.2   Figure 3. HSCL Driver Circuit and Termination HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation, use the following equations which assume a 42.5 load to ground. The highest power dissipation occurs when VDDO3.3_MAX. Power = (VDDO3.3_MAX - VOUT) * IOUT since VOUT - IOUT * RL. = (VDDO3.3_MAX - IOUT * RL) * IOUT = (3.465V - 17mA * (42.5+ 27)) * 17mA Total Per Dissipation per output pair = 38.82mW REVISION 2 12/09/14 13 8-OUTPUT VERY LOW PHASE JITTER HCSL FANOUT BUFFER 8INT31H800A DATA SHEET Package Outline and Package Dimensions (32-pin VFQFPN, 0.50mm pitch)  Package dimensions are kept current with JEDEC Publication No. 95 Thermal Base EP – exposed thermal pad should be externally connected to GND 8-OUTPUT VERY LOW PHASE JITTER HCSL FANOUT BUFFER 14 REVISION 2 12/09/14 8INT31H800A DATA SHEET Ordering Information Table 5. Ordering Information Part/Order Number Marking 8INT31H800ANLGI 8INT31H800ANLGI8 REVISION 2 12/09/14 Package Shipping Packaging Temperature IDT8INT31H800ANLGI 32-pin VFQFN, Lead-Free Tray -40C to 85C IDT8INT31H800ANLGI 32-pin VFQFN, Lead-Free Tape & Reel -40C to 85C 15 8-OUTPUT VERY LOW PHASE JITTER HCSL FANOUT BUFFER 8INT31H800A DATA SHEET Revision History Sheet Rev 2 Table Page Description of Change Date Deleted Confidential label from footer of datasheet. 8-OUTPUT VERY LOW PHASE JITTER HCSL FANOUT BUFFER 16 12/9/14 REVISION 2 12/09/14 Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. 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