Datasheet
LVDS Interface LSI
67bit LVDS Receiver
BU90R102
Key Specifications
General Description
The BU90R102 receiver operates from 8MHz to 160MHz
wide clock range.
The BU90R102 converts the 10 Lane (2Channel) LVDS
serial data streams back into 67bit of LVCMOS parallel
data.
Data is transmitted seven times (7X) stream and reduce
the cable number by 3(1/3) or less.
I/O Voltage range is 2.3 to 3.6V, so it is available for
many products.
Flexible Input /Output mode is suitable for a variety of
application Interface.
Features
■The maximum data rate is 1120Mbps/Lane
■It enables to receive the 60bit of RGB data,
7bit of Timing and Control data
■Support clock frequency from 8MHz up to 160MHz
■Flexible Input /Output mode
1. Single-in / Single-out
2. Single-in / Dual-out
3. Dual-in / Single-out
4. Dual-in / Dual-out
■Supply Voltage Range
■Operating Frequency
■Operating Temperature Range
Package
2.30 to 3.60 V
8 to 160 MHz
-40 to +85 ℃
W(Typ) x D(Typ) x H(Max)
HQFP144VM
20.0mm × 20.0mm × 1.6mm
Applications
■Security camera, Digital camera
■Tablet
■Flat panel display
■Power down mode
■Clock edge selectable
■Support spread spectrum clock generator input
Block Diagram
Figure 1. Block Diagram
〇Product structure : Silicon monolithic integrated circuit
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Datasheet
BU90R102
Contents
General Description ....................................................................................................................................................1
Key Specifications ......................................................................................................................................................1
Package .......................................................................................................................................................................1
Applications ................................................................................................................................................................1
Features .....................................................................................................................................................................1
Block Diagram .............................................................................................................................................................1
Figure 1. Block Diagram .........................................................................................................................................1
Pin Configuration ........................................................................................................................................................3
Figure 2. Pin Configuration ....................................................................................................................................3
Pin Descriptions .........................................................................................................................................................4
Absolute Maximum Ratings .....................................................................................................................................6
Recommended Operating Conditions ......................................................................................................................6
Figure 3. Differential input CLK .............................................................................................................................6
DC Characteristic ........................................................................................................................................................7
Figure 4. LVDS Receiver DC Specifications .........................................................................................................7
AC Characteristic ........................................................................................................................................................8
Supply Current ............................................................................................................................................................9
Figure 5. Test Pattern ............................................................................................................................................9
AC Timing Diagrams.................................................................................................................................................10
Figure 6. LVCMOS Output Load and Transition Time ......................................................................................10
Figure 7. CLKOUT Period and High/Low Time .................................................................................................10
Figure 8. CLKOUT Position and Setup/Hold Timing ........................................................................................10
Figure 9. CLKOUT Position and Setup/Hold Timing for Double Edge Output Mode
.................................. 11
Figure 10. LVDS Input Data Position ................................................................................................................. 11
Figure 11. Phase Locked Loop Set Time ..........................................................................................................12
Figure 12. RCLK+/- to CLKOUT Delay ...............................................................................................................12
Figure 13. RC1 (DE) Input Timing (Single-in / Dual-out mode) .......................................................................13
Output Data Mapping................................................................................................................................................14
LVDS Input Data Mapping ........................................................................................................................................16
Figure 14. LVDS Input Data Mapping MODE1=H (Single-in Mode) .................................................................16
Figure 15. LVDS Input Data Mapping MODE1=L (Dual-in Mode) ....................................................................16
Typical Application Circuit .......................................................................................................................................21
Figure 16. Typical Application Circuit (24bit Dual-in/Dual-out mode) ............................................................21
Operational Notes .....................................................................................................................................................22
Ordering Information ................................................................................................................................................24
Marking Diagram .......................................................................................................................................................24
Physical Dimension, Tray Information ...................................................................................................................25
Revision History .......................................................................................................................................................26
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Datasheet
BU90R102
Pin Configuration
Figure 2. Pin Configuration (Top View)
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Datasheet
BU90R102
Pin Descriptions
Pin name
Pin No.
I/O
RA1+, RA1-
111,110
LVDS Input
RB1+, RB1-
113,112
LVDS Input
RC1+, RC1-
117,116
LVDS Input
RD1+, RD1-
123,122
LVDS Input
RE1+, RE1-
125,124
LVDS Input
RCLK+, RCLK-
119,118
LVDS Input
RA2+,RA2-
129,128
LVDS Input
RB2+,RB2-
131,130
LVDS Input
RC2+,RC2-
135,134
LVDS Input
RD2+,RD2-
141,140
LVDS Input
RE2+,RE2-
143,142
LVDS Input
R19～R10
74-72,69-63
Output
G19～G10
86-82,79-75
Output
B19～B10
100,99,96-90,87
Output
R29～R20
25-23,20-14
Output
G29～G20
40,37-31,
27,26
Output
B29～B20
52-48,45-41
Output
CONT11,CONT12
104,105
Output
CONT21,CONT22
55,56
Output
DE
103
Output
Data Enable Output
VSYNC
102
Output
VSYNC Output
HSYNC
101
Output
HSYNC Output
CLKOUT
60
Output
LVCMOS CLK Output
PDWN
4
Input
MODE1,MODE0
6,5
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Descriptions
LVDS Data input (Channel1)
+: positive input of differential pair
-: negative input of differential pair
LVDS CLK input
LVDS Data input (Channel2)
+: positive input of differential pair
-: negative input of differential pair
（These pins are disabled when Single Link mode）
LVCMOS Data Output
LVCMOS Data Output
LVCMOS Data Output
Power Down
H: Normal operation
L: Power down
Input
4/26
MODE1
MODE0
Mode
H
H
Single Link(Single-in/Single-out)
H
L
Single Link(Single-in/Dual-out)
L
H
Dual Link(Dual-in/Single-out)
L
L
Dual Link(Dual-in/Dual-out)
TSZ02201-0L2L0H500280-1-2
02.Oct.2014 Rev.001
Datasheet
BU90R102
Pin Descriptions (Continued)
Pin name
Pin No.
I/O
Descriptions
Output Clock Delay Timing Select.
tDOUT=Output Data Rate
DK
7
MODE〔1:0〕
DK
LL
HH
HL
L
M
H
L
M
H
Input
LH
R/F
8
Input
OE
9
Input
MODE2
10
Input
OFFSET
〔nsec〕
0
-(6/28)tDOUT
+(6/28)tDOUT
0
-(7/28)tDOUT
+(7/28)tDOUT
Output Clock Triggering Edge Select.
H:Rising edge
L:Falling edge
Output Enable.
H: Output Enable.
L: Output Disable.
DDR function enable
This function depends on the setting of MODE.
MODE=LH (Dual-in/Single-out MODE)
H:DDR (Double Edge Output)function ON
L:DDR (Double Edge Output) function OFF
MODE=other
Must be tied to GND.
MAP
Reserved
11
Input
LVDS mapping table select (Refer the Table 9～12)
H:Mapping Mode1
L:Mapping Mode2
3
Input
Must be tied to VDD.
12,21,28,29,38,
46,53,57,61,70,80,
88,97,106
13,22,30,39,47,
54,58,59,62,71,81,
89,98,145
114,120,126,
132,138
109,115,121,127,
133,136,137,139,
144
VDD
GND
LVDD
LGND
Power
Power Supply for Internal digital core and Output Driver.
Ground
Ground for Internal digital core and Output Driver.
Power
Power Supply for LVDS core.
Ground
Ground for LVDS core.
PVDD
2,107
Power
Power Supply for PLL core.
PGND
1,108
Ground
Ground for PLL core.
Table 1. Output Settings
PDWN
OE
Data Outputs
CLKOUT
L
L
Hi-Z
Hi-Z
L
H
All Low
H
L
Hi-Z
Hi-Z
H
H
Data Out
CLK Out
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Datasheet
BU90R102
Absolute Maximum Ratings
Rating
Parameter
Symbol
Units
Min
Max
Supply Voltage
VDD
-0.3
+4.0
V
Input Voltage
VIN
-0.3
VDD+0.3
V
Output Voltage
VOUT
-0.3
VDD+0.3
V
Storage Temperature Range
Tstg
-55
+125
℃
Junction Temperature
Tj
Power
Pd
(Note1)
Dissipation
℃
+125
4.16
(Note1)
W
Package Power when IC mounting on the PCB board.
3
The size of PCB board：114.3 × 76.2 × 1.6 (mm )
The material of PCB board：The FR4 glass epoxy board (3% or less copper foil area)
Recommended Operating Conditions
Parameter
Units
Conditions
3.6
V
VDD,LVDD,
PVDD
+25
+85
℃
-
8
-
160
MHz
-
Output
8
-
160
MHz
-
Single Edge Output
(MODE2=L)
LVDS Input
20
-
80
MHz
-
Output
40
-
160
MHz
-
Double Edge Output
(MODE2=H)
LVDS Input
20
-
80
MHz
-
Output
20
-
80
MHz
-
MODE=HL
Single-in/Dual-out
LVDS Input
8
-
160
MHz
-
Output
4
-
80
MHz
-
MODE=HH
Single-in/Single-out
LVDS Input
8
-
160
MHz
-
Output
8
-
160
MHz
-
ns
-
ns
-
Supply Voltage
Operating Temperature Range
MODE=LL
Dual-in/Dual-out
CLK
frequency
Rating
Symbol
MODE=LH
Dual-in/Single-out
Min
Typ
Max
VDD
2.3
3.3
Ta
-40
LVDS Input
tRCIP
7
tRCIP
2
7
2
Differential input CLK High Time (tRCIH) (Figure 3)
Differential input CLK Low Time (tRCIL) (Figure 3)
tRCIH
Vdiff = 0V
RCLK+
(Differential)
-
tRCIP
7
tRCIP
5
7
5
tRCIL
Vdiff = 0V
Vdiff = 0V
tRCIP
Figure 3. Differential input CLK
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Datasheet
BU90R102
DC Characteristics
Table 2. LVCMOS DC Specifications ( VDD=2.3~3.6V, Ta=-40~+85℃ )
Limits
Symbol
Parameter
Min
Typ
Max
Units
VIH
High Level Input Voltage
VDDx0.7
-
VDD
V
VIL
Low Level Input Voltage
GND
-
VDDx0.3
V
Conditions
PDWN, MODE[2:0]
R/F, OE, MAP PIN
VIH3
High Level Input Voltage 3
VDDx0.8
-
VDD
V
VIM3
Middle Level Input Voltage 3
VDDx0.4
-
VDDx0.6
V
VIL3
Low Level Input Voltage 3
GND
VDDx0.2
V
VOH
High Level Output Voltage
VDD -0.5
-
VDD
V
IO = -8mA
VOL
Low Level Output Voltage
GND
-
0.4
V
IO = 8mA
-10
-
+10
uA
0 ≤VIN ≤VDD
IIL
Input Leakage Current
3-Level Inputs
(DK Pin)
Table 3. LVDS Receiver DC Specifications ( VDD=2.3~3.6V, Ta=-40~+85℃ )
Symbol
VTH
VTL
IINL
Parameter
Differential Input
High Threshold
Differential Input
Low Threshold
Differential Input
Leakage Current
Limits
Units
Conditions
Min
Typ
Max
-
-
+100
mV
VOC（
Note2）
=1.2V
-100
-
-
mV
VOC（
Note2）
=1.2V
-30
-
+30
µA
VIN=2.4V / 0V
VDD=3.6V
VOC
Common mode Voltage
0.8
1.2
1.6
V
VID =200mV
|VID|
Differential Input Voltage
100
-
600
mV
-
(Note2) Common mode Voltage
Figure 4. LVDS Receiver DC Specifications
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Datasheet
BU90R102
AC characteristics
Table 4. Switching Characteristics ( VDD=2.3~3.6V, Ta=-40~+85℃ )
Limits
Parameter
Symbol
Units
Min
Typ
Max
6.25
-
250
ns
tRCP
CLKOUT Period (Figure 7)
tRCH
CLKOUT High Time (Figure 7)
-
0.5tRCP
-
ns
tRCL
CLKOUT Low Time (Figure 7)
-
0.5tRCP
-
ns
tDOUT
LVCMOS Data Out Period (Figure 8,9)
6.25
-
250
ns
tRS
LVCMOS Data Setup to CLKOUT (Figure 8,9)
0.45tRCP-0.45
-
-
ns
tRH
LVCMOS Data Hold to CLKOUT (Figure 8,9)
0.45tRCP-0.45
-
-
ns
tTLH
LVCMOS Low to High Transition Time (Figure 6)
-
0.7
1.0
ns
tTHL
LVCMOS High to Low Transition Time (Figure 6)
-
0.7
1.0
ns
tRCIP=65MHz
0
-
650
ps
tRCIP=85MHz
0
-
450
ps
tRCIP=108MHz
0
-
250
ps
tRCIP=135MHz
0
-
170
ps
tRCIP=160MHz
0
-
150
ps
- tsk
0.0
+ tsk
ns
tRCIP
- tsk
7
tRCIP
2
- tsk
7
tRCIP
3
- tsk
7
tRCIP
4
- tsk
7
tRCIP
5
- tsk
7
tRCIP
6
- tsk
7
tRCIP
7
tRCIP
2
7
tRCIP
3
7
tRCIP
4
7
tRCIP
5
7
tRCIP
6
7
tRCIP
+ tsk
7
tRCIP
2
+ tsk
7
tRCIP
3
+ tsk
7
tRCIP
4
+ tsk
7
tRCIP
5
+ tsk
7
tRCIP
6
+ tsk
7
-
-
10.0
ms
82
-
180
ns
6.25
-
125.0
ns
DE input period
(Figure 13)
4tRCIP
tRCIP*(2n)
n=integer
-
ns
DE input High time
(Figure 13)
2tRCIP
-
-
ns
DE input Low time
(Figure 13)
2tRCIP
-
-
ns
tsk
Receiver
Skew Margin
(Figure 10)
tRIP1
Input Data Position 0 (Figure 10)
tRIP0
Input Data Position 1 (Figure 10)
tRIP6
Input Data Position 2 (Figure 10)
tRIP5
Input Data Position 3 (Figure 10)
tRIP4
Input Data Position 4 (Figure 10)
tRIP3
Input Data Position 5 (Figure 10)
tRIP2
Input Data Position 6 (Figure 10)
tRPLL
Phase Locked Loop Set Time (Figure 11)
tRCD
RCLK+/- to CLKOUT Delay (Figure 12)
MODE=LL DK=L, 75MHz
tRCIP
Input CLK Period (Figure 10)
tDEINT
tDEH
MODE=HL
(Single-in/Dual-out Mode)
tDEL
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ns
ns
ns
ns
ns
ns
TSZ02201-0L2L0H500280-1-2
02.Oct.2014 Rev.001
Datasheet
BU90R102
Supply Current
Limits
Symbol
Parameter
Conditions
Units
CLKOUT=65MHz
MODE=HH
Single-in/Single-out
CLKOUT=85MHz
CLKOUT=135MHz
MODE2=L
CLKOUT=160MHz
CLKOUT=32.5MHz
MODE=HL
Single-in/Dual-out
CLKOUT=42.5MHz
CLKOUT=67.5MHz
MODE2=L
CLKOUT=80MHz
CLKOUT=65MHz
IRCCW
Receiver
Supply Current
( Worst Case
Pattern )
Figure 5
MODE=LH
Dual-in/ Single out
CLKOUT=85MHz
CLKOUT=135MHz
CLKOUT=150MHz
CL=8pF
MODE2=L
DDR Output Off
CLKOUT=160MHz
CLKOUT=32.5MHz
MODE=LH
Dual-in/ Single out
CLKOUT=42.5MHz
CLKOUT=67.5MHz
MODE2=H
DDR Output On
CLKOUT=75MHz
CLKOUT=80MHz
CLKOUT=65MHz
MODE=LL
Dual-in/ Dual-out
CLKOUT=85MHz
CLKOUT=135MHz
MODE2=L
CLKOUT=160MHz
Typ
Max
-
134
mA
-
165
mA
-
244
mA
-
284
mA
-
110
mA
-
134
mA
-
190
mA
-
230
mA
-
113
mA
-
137
mA
-
190
mA
-
221
mA
-
230
mA
-
110
mA
-
134
mA
-
187
mA
-
217
mA
-
228
mA
-
218
mA
-
272
mA
-
408
mA
-
460
mA
Figure 5. Test Pattern
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Datasheet
BU90R102
AC Timing Diagrams
LVCMOS Output
CL =8pF
LVCMOS Output Load
Figure 6. LVCMOS Output Load and Transition Time
Figure 7. CLKOUT Period and High/Low Time
ｔ
6 DOUT
28
ｔ
7 DOUT
28
ｔ
6 DOUT
28
ｔ
7 DOUT
28
Figure 8. CLKOUT Position and Setup/Hold Timing
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Datasheet
BU90R102
AC Timing Diagrams (Continued)
ｔ
7 DOUT
28
ｔ
7 DOUT
28
ｔ
7 DOUT
28
ｔ
7 DOUT
28
Figure 9. CLKOUT Position and Setup/Hold Timing for
Double Edge Output Mode
Figure 10. LVDS Input Data Position
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Datasheet
BU90R102
AC Timing Diagrams (Continued)
Figure 11. Phase Locked Loop Set Time
Figure 12. RCLK+/- to CLKOUT Delay
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Datasheet
BU90R102
Table 5. Input DE signal of all Input/Output modes
In
Out
MODE1
MODE0
Input DE Signal
Single
Single
H
H
Optional
Single
Dual
H
L
Require (Figure 13)
Dual
Single
L
H
Optional
Dual
Dual
L
L
Optional
Figure 13. RC1 (DE) Input Timing (Single-in / Dual-out mode)
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Datasheet
BU90R102
Output Data Mapping
Table 6. Output Color Data naming rule
X
Y
Z
Description
X=R
-
-
Red Color Data
X=G
-
-
Green Color Data
X=B
-
-
Blue Color Data
-
Y=None
-
Single Pixel
-
Y=O
-
1st Pixel Data
Dual Pixel
-
Y=E
-
-
-
Z=0-9
2nd Pixel Data
0: LSB(Least Significant Bit)
9: MSB(Most Significant Bit)
Bit number
Table 7. LVCMOS Output Data Mapping (Single-out mode, MODE0=H)
Data Signals
Receiver Output Pin Names
30-bit
24-bit
18-bit
30-bit
24-bit
18-bit
R0
-
-
R10
-
-
R1
-
-
R11
-
-
R2
R0
-
R12
R12
-
R3
R1
-
R13
R13
-
R4
R2
R0
R14
R14
R14
R5
R3
R1
R15
R15
R15
R6
R4
R2
R16
R16
R16
R7
R5
R3
R17
R17
R17
R8
R6
R4
R18
R18
R18
R9
R7
R5
R19
R19
R19
G0
-
-
G10
-
-
G1
-
-
G11
-
-
G2
G0
-
G12
G12
-
G3
G1
-
G13
G13
-
G4
G2
G0
G14
G14
G14
G5
G3
G1
G15
G15
G15
G6
G4
G2
G16
G16
G16
G7
G5
G3
G17
G17
G17
G8
G6
G4
G18
G18
G18
G9
G7
G5
G19
G19
G19
B0
-
-
B10
-
-
B1
-
-
B11
-
-
B2
B0
-
B12
B12
-
B3
B1
-
B13
B13
-
B4
B2
B0
B14
B14
B14
B5
B3
B1
B15
B15
B15
B6
B4
B2
B16
B16
B16
B7
B5
B3
B17
B17
B17
B8
B6
B4
B18
B18
B18
B9
B7
B5
B19
B19
B19
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Datasheet
BU90R102
Output Data Mapping (Continued)
Table 8. LVCMOS Output Data Mapping (Dual-Out mode, MODE0=L)
1st Pixel Data
2nd Pixel Data
Receiver output Pin
Names
Data Signals
Receiver output Pin
Names
Data Signals
30-bit
24bit
18-bit
30-bit
24bit
18-bit
30-bit
24bit
18-bit
30-bit
24bit
18-bit
RE0
-
-
R10
-
-
RO0
-
-
R20
-
-
RE1
-
-
R11
-
-
RO1
-
-
R21
-
-
RE2
RE0
-
R12
R12
-
RO2
RO0
-
R22
R22
-
RE3
RE1
-
R13
R13
-
RO3
RO1
-
R23
R23
-
RE4
RE2
RE0
R14
R14
R14
RO4
RO2
RO0
R24
R24
R24
RE5
RE3
RE1
R15
R15
R15
RO5
RO3
RO1
R25
R25
R25
RE6
RE4
RE2
R16
R16
R16
RO6
RO4
RO2
R26
R26
R26
RE7
RE5
RE3
R17
R17
R17
RO7
RO5
RO3
R27
R27
R27
RE8
RE6
RE4
R18
R18
R18
RO8
RO6
RO4
R28
R28
R28
RE9
RE7
RE5
R19
R19
R19
RO9
RO7
RO5
R29
R29
R29
GE0
-
-
G10
-
-
GO0
-
-
G20
-
-
GE1
-
-
G11
-
-
GO1
-
-
G21
-
-
GE2
GE0
-
G12
G12
-
GO2
GO0
-
G22
G22
-
GE3
GE1
-
G13
G13
-
GO3
GO1
-
G23
G23
-
GE4
GE2
GE0
G14
G14
G14
GO4
GO2
GO0
G24
G24
G24
GE5
GE3
GE1
G15
G15
G15
GO5
GO3
GO1
G25
G25
G25
GE6
GE4
GE2
G16
G16
G16
GO6
GO4
GO2
G26
G26
G26
GE7
GE5
GE3
G17
G17
G17
GO7
GO5
GO3
G27
G27
G27
GE8
GE6
GE4
G18
G18
G18
GO8
GO6
GO4
G28
G28
G28
GE9
GE7
GE5
G19
G19
G19
GO9
GO7
GO5
G29
G29
G29
BE0
-
-
B10
-
-
BO0
-
-
B20
-
-
BE1
-
-
B11
-
-
BO1
-
-
B21
-
-
BE2
BE0
-
B12
B12
-
BO2
BO0
-
B22
B22
-
BE3
BE1
-
B13
B13
-
BO3
BO1
-
B23
B23
-
BE4
BE2
BE0
B14
B14
B14
BO4
BO2
BO0
B24
B24
B24
BE5
BE3
BE1
B15
B15
B15
BO5
BO3
BO1
B25
B25
B25
BE6
BE4
BE2
B16
B16
B16
BO6
BO4
BO2
B26
B26
B26
BE7
BE5
BE3
B17
B17
B17
BO7
BO5
BO3
B27
B27
B27
BE8
BE6
BE4
B18
B18
B18
BO8
BO6
BO4
B28
B28
B28
BE9
BE7
BE5
B19
B19
B19
BO9
BO7
BO5
B29
B29
B29
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Datasheet
BU90R102
LVDS Input Data Mapping
Previous Cycle
(2nd Pixel Data)
Current Cycle
(1st Pixel Data)
RCLK+
RCLK +
Rx1
Rx 1 +/+/ x = A , B ,C ,D , E
Rx11(n-1) Rx10(n-1)
Rx16(n)
Rx15(n)
Current Cycle
(1st Pixel Data)
Rx14(n)
Rx13(n)
Rx12 (n)
Rx11 (n)
Rx10(n)
Rx6 (n+1)
Next Cycle
(2nd Pixel Data)
RCLK+
RCLK +
Rx1
Rx 1 +/+/ x = A , B ,C ,D , E
Rx11(n)
Rx10(n)
Rx16(n+1)
Rx15(n+1) Rx14(n+1) Rx13(n+1) Rx12 (n+1) Rx11 (n+1) Rx10(n+1)
Rx6 (n+2)
Figure 14. LVDS Input Data Mapping
MODE1=H (Single-in Mode)
Previous C ycle
C urrent C ycle
RCLK+
R x 1 +/ x = A , B ,C , D , E
R x2
x 2 +/ x = A , B ,C ,D ,E
Rx11(n-1) Rx10(n-1)
Rx16(n)
Rx15(n)
Rx14(n)
Rx13(n)
R x12 (n)
Rx11 (n)
Rx10(n)
R x16 (n+1)
Rx21(n-1) Rx20(n-1)
Rx26(n)
Rx25(n)
Rx24(n)
Rx23(n)
R x22 (n)
Rx21 (n)
Rx20(n)
R x26 (n+1)
Figure 15. LVDS Input Data Mapping
MODE1=L (Dual-in Mode)
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Datasheet
BU90R102
LVDS Input Data Mapping (Continued)
Table 9. LVDS Input Data Mapping (Single-in/Single-out mode, MODE=HH)
LVDS
Input Data
Mapping Mode1
(Output Pin Name)
Mapping Mode2
(Output Pin Name)
RA10
R14
R12
RA11
R15
R13
RA12
R16
R14
RA13
R17
R15
RA14
R18
R16
RA15
R19
R17
RA16
G14
G12
RB10
G15
G13
RB11
G16
G14
RB12
G17
G15
RB13
G18
G16
RB14
G19
G17
RB15
B14
B12
RB16
B15
B13
RC10
B16
B14
RC11
B17
B15
RC12
B18
B16
RC13
B19
B17
RC14
HSYNC
HSYNC
RC15
VSYNC
VSYNC
RC16
DE
DE
RD10
R12
R18
RD11
R13
R19
RD12
G12
G18
RD13
G13
G19
RD14
B12
B18
RD15
B13
B19
RD16
CONT11
CONT11
RE10
R10
R10
RE11
R11
R11
RE12
G10
G10
RE13
G11
G11
RE14
B10
B10
RE15
B11
B11
RE16
CONT12
CONT12
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Datasheet
BU90R102
LVDS Input Data Mapping (Continued)
Table 10. LVDS Input Data Mapping (Single-in/Dual-out mode, MODE=HL)
1st Pixel Data
2nd Pixel Data
LVDS
Input Data
(1st Pixel Data)
Mapping Mode1
(Output Pin Name)
Mapping Mode2
(Input Pin Name)
LVDS
Input Data
(1st Pixel Data)
Mapping Mode1
(Output Pin Name)
Mapping Mode2
(Input Pin Name)
RA10(n)
R14
R12
RA10(n+1)
R24
R22
RA11(n)
R15
R13
RA11(n+1)
R25
R23
RA12(n)
R16
R14
RA12(n+1)
R26
R24
RA13(n)
R17
R15
RA13(n+1)
R27
R25
RA14(n)
R18
R16
RA14(n+1)
R28
R26
RA15(n)
R19
R17
RA15(n+1)
R29
R27
RA16(n)
G14
G12
RA16(n+1)
G24
G22
RB10(n)
G15
G13
RB10(n+1)
G25
G23
RB11(n)
G16
G14
RB11(n+1)
G26
G24
RB12(n)
G17
G15
RB12(n+1)
G27
G25
RB13(n)
G18
G16
RB13(n+1)
G28
G26
RB14(n)
G19
G17
RB14(n+1)
G29
G27
RB15(n)
B14
B12
RB15(n+1)
B24
B22
RB16(n)
B15
B13
RB16(n+1)
B25
B23
RC10(n)
B16
B14
RC10(n+1)
B26
B24
RC11(n)
B17
B15
RC11(n+1)
B27
B25
RC12(n)
B18
B16
RC12(n+1)
B28
B26
RC13(n)
B19
B17
RC13(n+1)
B29
B27
RC14(n)
HSYNC
HSYNC
RC14(n+1)
HSYNC
HSYNC
RC15(n)
VSYNC
VSYNC
RC15(n+1)
VSYNC
VSYNC
RC16(n)
DE
DE
RC16(n+1)
DE
DE
RD10(n)
R12
R18
RD10(n+1)
R22
R28
RD11(n)
R13
R19
RD11(n+1)
R23
R29
RD12(n)
G12
G18
RD12(n+1)
G22
G28
RD13(n)
G13
G19
RD13(n+1)
G23
G29
RD14(n)
B12
B18
RD14(n+1)
B22
B28
RD15(n)
B13
B19
RD15(n+1)
B23
B29
RD16(n)
CONT11
CONT11
RD16(n+1)
CONT21
CONT21
RE10(n)
R10
R10
RE10(n+1)
R20
R20
RE11(n)
R11
R11
RE11(n+1)
R21
R21
RE12(n)
G10
G10
RE12(n+1)
G20
G20
RE13(n)
G11
G11
RE13(n+1)
G21
G21
RE14(n)
B10
B10
RE14(n+1)
B20
B20
RE15(n)
B11
B11
RE15(n+1)
B21
B21
RE16(n)
CONT12
CONT12
RE16(n+1)
CONT22
CONT22
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Datasheet
BU90R102
LVDS Input Data Mapping (Continued)
Table 11. LVDS Input Data Mapping (Dual-in/Single-out mode DDR On or Off, MODE = LH, MODE2 = H or L)
1st Pixel Data
2nd Pixel Data
LVDS
Input Data
(1st Pixel Data)
Mapping Mode1
(Output Pin
Name)
Mapping Mode2
(Output Pin
Name)
LVDS
Input Data
(1st Pixel Data)
Mapping Mode1
(Output Pin
Name)
Mapping Mode2
(Output Pin
Name)
RA10
R14(n)
R12(n)
RA20
R14(n+1)
R12(n+1)
RA11
R15(n)
R13(n)
RA21
R15(n+1)
R13(n+1)
RA12
R16(n)
R14(n)
RA22
R16(n+1)
R14(n+1)
RA13
R17(n)
R15(n)
RA23
R17(n+1)
R15(n+1)
RA14
R18(n)
R16(n)
RA24
R18(n+1)
R16(n+1)
RA15
R19(n)
R17(n)
RA25
R19(n+1)
R17(n+1)
RA16
G14(n)
G12(n)
RA26
G14(n+1)
G12(n+1)
RB10
G15(n)
G13(n)
RB20
G15(n+1)
G13(n+1)
RB11
G16(n)
G14(n)
RB21
G16(n+1)
G14(n+1)
RB12
G17(n)
G15(n)
RB22
G17(n+1)
G15(n+1)
RB13
G18(n)
G16(n)
RB23
G18(n+1)
G16(n+1)
RB14
G19(n)
G17(n)
RB24
G19(n+1)
G17(n+1)
RB15
B14(n)
B12(n)
RB25
B14(n+1)
B12(n+1)
RB16
B15(n)
B13(n)
RB26
B15(n+1)
B13(n+1)
RC10
B16(n)
B14(n)
RC20
B16(n+1)
B14(n+1)
RC11
B17(n)
B15(n)
RC21
B17(n+1)
B15(n+1)
RC12
B18(n)
B16(n)
RC22
B18(n+1)
B16(n+1)
RC13
B19(n)
B17(n)
RC23
B19(n+1)
B17(n+1)
RC14
HSYNC(n)
HSYNC(n)
RC24
HSYNC(n+1)
HSYNC(n+1)
RC15
VSYNC(n)
VSYNC(n)
RC25
VSYNC(n+1)
VSYNC(n+1)
RC16
DE(n)
DE(n)
RC26
DE(n+1)
DE(n+1)
RD10
R12(n)
R18(n)
RD20
R12(n+1)
R18(n+1)
RD11
R13(n)
R19(n)
RD21
R13(n+1)
R19(n+1)
RD12
G12(n)
G18(n)
RD22
G12(n+1)
G18(n+1)
RD13
G13(n)
G19(n)
RD23
G13(n+1)
G19(n+1)
RD14
B12(n)
B18(n)
RD24
B12(n+1)
B18(n+1)
RD15
B13(n)
B19(n)
RD25
B13(n+1)
B19(n+1)
RD16
CONT11(n)
CONT11(n)
RD26
CONT11(n+1)
CONT11(n+1)
RE10
R10(n)
R10(n)
RE20
R10(n+1)
R10(n+1)
RE11
R11(n)
R11(n)
RE21
R11(n+1)
R11(n+1)
RE12
G10(n)
G10(n)
RE22
G10(n+1)
G10(n+1)
RE13
G11(n)
G11(n)
RE23
G11(n+1)
G11(n+1)
RE14
B10(n)
B10(n)
RE24
B10(n+1)
B10(n+1)
RE15
B11(n)
B11(n)
RE25
B11(n+1)
B11(n+1)
RE16
CONT12(n)
CONT12(n)
RE26
CONT12(n+1)
CONT12(n+1)
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Datasheet
BU90R102
LVDS Input Data Mapping (Continued)
Table 12. LVDS Input Data Mapping (Dual-in/Dual-out mode, MODE = LL)
1st Pixel Data
2nd Pixel Data
LVDS
Input Data
(1st Pixel Data)
Mapping Mode1
(Output Pin
Name)
Mapping Mode2
(Output Pin
Name)
LVDS
Input Data
(1st Pixel Data)
Mapping Mode1
(Output Pin
Name)
Mapping Mode2
(Output Pin
Name)
RA10
R14
R12
RA20
R24
R22
RA11
R15
R13
RA21
R25
R23
RA12
R16
R14
RA22
R26
R24
RA13
R17
R15
RA23
R27
R25
RA14
R18
R16
RA24
R28
R26
RA15
R19
R17
RA25
R29
R27
RA16
G14
G12
RA26
G24
G22
RB10
G15
G13
RB20
G25
G23
RB11
G16
G14
RB21
G26
G24
RB12
G17
G15
RB22
G27
G25
RB13
G18
G16
RB23
G28
G26
RB14
G19
G17
RB24
G29
G27
RB15
B14
B12
RB25
B24
B22
RB16
B15
B13
RB26
B25
B23
RC10
B16
B14
RC20
B26
B24
RC11
B17
B15
RC21
B27
B25
RC12
B18
B16
RC22
B28
B26
RC13
B19
B17
RC23
B29
B27
RC14
HSYNC
HSYNC
RC24
RC15
VSYNC
VSYNC
RC25
RC16
DE
DE
RC26
RD10
R12
R18
RD20
R22
R28
RD11
R13
R19
RD21
R23
R29
RD12
G12
G18
RD22
G22
G28
RD13
G13
G19
RD23
G23
G29
RD14
B12
B18
RD24
B22
B28
RD15
B13
B19
RD25
B23
B29
RD16
CONT11
CONT11
RD26
CONT21
CONT21
RE10
R10
R10
RE20
R20
R20
RE11
R11
R11
RE21
R21
R21
RE12
G10
G10
RE22
G20
G20
RE13
G11
G11
RE23
G21
G21
RE14
B10
B10
RE24
B20
B20
RE15
B11
B11
RE25
B21
B21
RE16
CONT12
CONT12
RE26
CONT22
CONT22
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Datasheet
BU90R102
Typical Application Circuit (24bit・
・Dual-in/Dual-out mode)
[Example]
BU90T82:
LVCMOS Data Input (24bit) / rising edge
LVDS 350mV swing output / VESA mapping / Dual-out
BU90R102: LVDS 350mV swing input / VESA mapping / Dual-in
LVCMOS Data Input (48bit) / Dual-out / falling edge
＊ 100Ω resistance
FPC
Cable
R10
TA1-
RA1-
R10
R[1]
R11
TA1+
RA1+
R11
R[2]
R12
R[3]
R13
TB1-
RB1-
R13
R[4]
R14
TB1+
RB1+
R14
R[5]
R15
R[6]
R16
TC1-
R[7]
R17
TC1+
R12
100Ω
R15
100Ω
R16
RC1-
R17
RC1+
R18
G[0]
G10
G[1]
G11
TD1-
G[2]
G12
TD1+
G[3]
G13
G[4]
G14
TCLK1-
G[5]
G15
TCLK1+
G[6]
G16
G[7]
G17
B[0]
B10
B[1]
B11
B[2]
B12
100Ω
RD 1-
R19
RD 1+
G10
G11
100Ω
RCLK1-
G12
RCLK1+
G13
G14
FPC cable connector
BU 90T
90 T 82
G15
BU 90R
90 R 102
RE1-
G16
RE1+
G17
G18
G19
B[3]
B13
B[4]
B14
TA2-
B[5]
B15
TA2+
100Ω
B10
RA2-
B11
RA2+
B12
B[6]
B16
B[7]
B17
TB2-
VSYNC
VSYNC
TB2+
HSYNC
HSYNC
DE
100Ω
FPC cable connector
24Bit
24 Bit GPU
R[0]
100Ω
RB2-
B13
RB2+
B14
B15
TC2-
DE
100Ω
B16
RC2-
B17
TC2+
RC2+
TD2-
RD 2-
B19
RD 2+
CONT11
B18
100Ω
TD2+
TCLK2-
RE2-
R20
TCLK2+
RE2+
R21
PWDN
RF
RS
OE
DDRN
MODE
6B8B
MAP
FLIP
CONT12
R22
R23
R24
VDDIO
R25
4.7k
4.7k
4.7k
4.7k
4.7k
4.7k
4.7k
4.7k
2.5V
R26
R27
10k
0.1μ F
0.1μ F
R28
0.01μ F
R29
G20
VDD
G21
G22
1.8V
G23
G24
PCB
(Transmitter)
0.1μ F
0.01μ F
G25
G26
G27
G28
G29
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
CONT11
CONT12
VSYNC
DE
MAP
MODE2
OE
R/F
DK
MODE1
MODE0
PDWN
HSYNC
VDD
4.7k
3.3V
4.7k
4.7k
4.7k
4.7k
4.7k 4.7k
10k
0.1μF
0.01μ F
0.1μ F
PCB
(Receiver)
Figure 16. Typical Application Circuit (24bit Dual-in/Dual-out mode)
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Datasheet
BU90R102
Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Thermal Consideration
Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in
deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, increase the board size
and copper area to prevent exceeding the Pd rating.
6.
Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately
obtained. The electrical characteristics are guaranteed under the conditions of each parameter.
7.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush
current may flow instantaneously due to the internal powering sequence and delays, especially if the IC
has more than one power supply. Therefore, give special consideration to power coupling capacitance,
power wiring, width of ground wiring, and routing of connections.
8.
Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
9.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
10. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment)
and unintentional solder bridge deposited in between pins during assembly to name a few.
11. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
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BU90R102
Operational Notes – continued
12. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
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Datasheet
BU90R102
Ordering Information
B U 9 0 R 1 0 2
-
Part No.
Marking Diagrams
HQFP144VM (TOP VIEW)
Part Number Marking
BU90R102
LOT Number
1PIN MARK
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Datasheet
BU90R102
Physical Dimension, Tray Information
Package Name
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Datasheet
BU90R102
Revision History
Date
Revision
02.Oct.2014
001
Changes
New Release
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Datasheet
Notice
Precaution on using ROHM Products
1.
Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
(Note 1)
, transport
intend to use our Products in devices requiring extremely high reliability (such as medical equipment
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PGA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
Datasheet
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
QR code printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PGA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3.
The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Notice – WE
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