MR45V256AMAZAAT-L

PEDR45V256A-05 Issue Date: Oct. 17, 2011 MR45V256A 256k(32,768-Word  8-Bit) FeRAM (Ferroelectric Random Access Memory) SPI GENERAL DESCRIPTION The MR45V256A is a nonvolatile 32,768-word x 8-bit ferroelectric random access memory (FeRAM) developed in the ferroelectric process and silicon-gate CMOS technology. The MR45V256A is accessed using Serial Peripheral Interface.Unlike SRAMs, this device, whose cells are nonvolatile, eliminates battery backup required to hold data. This device has no mechanisms of erasing and programming memory cells and blocks, such as those used for various EEPROMs. Therefore, the write cycle time can be equal to the read cycle time and the power consumption during a write can be reduced significantly. The MR45V256A can be used in various applications, because the device is guaranteed for the write/read tolerance of 1012 cycles per bit and the rewrite count can be extended significantly. FEATURES • • • • • • • 32,768-word  8-bit configuration (Serial Peripheral Interface : SPI) A single 3.3 V  0.3 V power supply Operating frequency: 15MHz Read/write tolerance 1012 cycles/bit Data retention 10 years Guaranteed operating temperature range 40 to 85C (Extended temperature version) Package options: 8-pin plastic SOP (P-SOP8-200-1.27-T2K ) 1/20 PEDR45V256A-05 MR45V256A PIN CONFIGURATION 8-pin plastic SOP 1 SO 2 WP# 3 VSS 4 MR45V256A CS# 8 VCC 7 HOLD# 6 SCK 5 SI Note: Signal names that end with # indicate that the signals are negative-true logic. 2/20 PEDR45V256A-05 MR45V256A PIN DESCRIPTIONS Pin Name CS# Description Chip Select (input, negative logic) Latches an address by low input, activates the FeRAM, and enables a read or write operation. Write Protect( input , negative logic ) WP# Write Protect pin controls write-operation to the status-register(BP0,BP1). This pin should be fixed low or high in write-operations. HOLD( input , negative logic ) HOLD# Hold pin is used when the serial-communication suspended without disable the chip select. When HOLD# is low ,the serial-output is in High-Z status and serial-input/serial-clock are “Don’t Care” . CS# should be low in hold operation. Serial Clock SCK SI SO VCC, VSS Serial Clock is the clock input pin for setting for serial data timing. Inputs are latched on the rising edge and output occur on the falling edge. Serial input SI pins are serial input pins for Operation-code , addresses ,and data-inputs . Serial output SO pins are serial output pins. Power supply Apply the specified voltage to VCC. Connect VSS to ground. 3/20 PEDR45V256A-05 MR45V256A SPI mode0（CPOL=0, CPHA=0） CS# SCK SI MSB LSB SPI mode3（CPOL=1, CPHA=1） CS# SCK SI MSB LSB Status Register b7 b0 SRWD 0 0 0 BP1 BP0 WEL WIP Status Register Write Disable Block Protect Bits Write Enable Latch Write In Progress (Always 0) Name Function WIP WEL BP0,BP1 Fixed to 0. Write Enable Latch. This indicates internal WEL condition. Block Protect :These bits can be changed protect area . This is the software protect. SRWD Status Register Write Disable （ SRWD ） : SRWD controls the effect of the hardware WP# pin. This device will be in hardware-protect by combination of SRWD and WP#. Fixed to 0. 0 Status Register data are volatile. Set Status Register data by WRSR(Write status register) command, after power on. 4/20 PEDR45V256A-05 MR45V256A Operation-Code Operation codes are listed in the table below.If the device receives invalid operation code,the device will be diselected. Instruction Description Instruction format WREN Write Enable 0000 0110 WRDI Write Disable 0000 0100 RDSR Read Status Register 0000 0101 WRSR Write Status Register 0000 0001 READ Read from Memory Array 0000 0011 WRITE Write to Memory Array 0000 0010 5/20 PEDR45V256A-05 MR45V256A Commands WREN(Write Enable) It is necessary to set Write Enable Latch（WEL）bit before write-operation (WRITE and WRSR). WREN command sets WEL bit. CS# WP# Fixed “H” 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 SCK SI SO High-Z WRDI(Write Disable) WRDI command resets WEL bit. CS# WP# Fixed “H” 0 SCK SI SO High-Z 6/20 PEDR45V256A-05 MR45V256A RDSR(READ Status Register) The RDSR command allows to read data of status register. CS# WP# Fixed “H” 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 6 5 4 3 2 1 0 SRWD 0 0 0 SCK SI SO High-Z BP1 BP0 WEL WIP SRWD WRSR(WRITE Status Register） WRSR command allows to write data to status register(SRWD,BP0,BP1). It is necessary to set Write Enable Latch（WEL）bit by WREN command before executing WRSR. CS# 0 1 2 3 4 5 6 7 8 9 10 11 7 6 5 4 SRWD X X X 12 13 14 15 3 2 1 0 X X SCK SI SO 7 BP1 BP0 High-Z Note: WP#=Fix ”H” 7/20 PEDR45V256A-05 MR45V256A READ(Read from Memory Array) READ command can be valid when CS# goes “L”,then the op-code and 16bit-adresses are inputted to serial input”SI”. The inputted adresses are loaded to internal register,then the data from corresponded address is output at serial-output “SO”.If CS# will keep “L”,the internal adress will be incresed automatically after 8 clocks and will output the data from new-address.When it reaches the most significant adress,the adress counter rolls over tostarting adress,and reading cycle can be continued infinitely. CS# 0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 15 14 13 12 3 2 1 0 X A14 A13 A12 A3 A2 A1 A0 SCK SI 16bit Address An SO High-Z CS# 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 m Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Qx SCK SI SO Data Out (An) Data Out (An+1) Note : WP# = fixed ”H” 8/20 PEDR45V256A-05 MR45V256A WRITE(Write to Memory Array） Write command can be valid when CS# goes “L”,then the op-code and 16bit-adresses are inputted to serial input”SI”. Writing is terminated when CS# goes high after data-input. If CS# will keep “L”,the internal adress will be incresed automatically.When it reaches the most significant adress,the adress counter rolls over to starting adress 0000h,and writing cycle(overwriting) can be continued infinitely. WRITE(1Byte) CS# 0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 15 14 13 12 3 2 1 0 X A14 A13 A12 A3 A2 A1 A0 SCK SI 16bit Address An CS# 24 25 26 27 28 29 30 31 D7 D6 D5 D4 D3 D2 D1 D0 SCK SI Data Byte 1 Note : WP# = Fixed ”H” , SO=High-Z WRITE(Page) CS# 0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 15 14 13 12 3 2 1 0 X A14 A13 A12 A3 A2 A1 A0 SCK SI 16bit Address An CS# 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 SCK SI Data Byte 1 Data Byte 2 CS# 40 41 42 43 44 45 46 47 D7 D6 D5 D4 D3 D2 D1 D0 SCK SI Data Byte 3 D7 D6 D5 D4 D0 Data Byte N Note : WP# = Fixed ”H” , SO=High-Z 9/20 PEDR45V256A-05 MR45V256A Write Protection Writing protection block is shown as follows: Protect Block size Block Protect BIT Protected Block BP1 BP0 0 0 None 0 1 Upper 1/4 block 1 0 Upper 1/2 block 1 1 All Protected Address Area None 6000h – 7FFFh 4000h – 7FFFh 0000h – 7FFFh Writing Protect WP# 1 SRWD mode 0 0 0 1 1 0 1 Writing protection status in status register Protection status in memory Unprotected Protected blocks blocks Software protection (SPM) Status register is unprotected when WEL-bit is set by WREN command. BP0 and BP1 are unprotected. Protected Unprotected Hardware protection (HPM) Status register is protected. BP0 and BP1 are protected. Protected Unprotected 10/20 PEDR45V256A-05 MR45V256A HOLD Hold status is used for suspending serial comunication without disable the chip. SO becomes “High-Z” and SI is “Don’t care” during the hold status. It is necessary to keep CS#=L in hold status. Hold status Hold status SCK HOLD# 11/20 PEDR45V256A-05 MR45V256A ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings The application of stress (voltage, current, or temperature) that exceeds the absolute maximum rating may damage the device. Therefore, do not allow actual characteristics to exceed any one parameter ratings Pin voltages Parameter Rating Symbol Min. Max. Unit Pin Voltage (Input Signal) VIN –0.5 VCC + 0.5 V Pin Voltage (Input/Output Voltage) VINQ, VOUTQ –0.5 VCC + 0.5 V Power Supply Voltage VCC –0.5 4.0 V Temperature Range Parameter Rating Symbol Unit Min. Max. Storage Temperature (Extended Temperature Version) Tstg –55 125 °C Operating Temperature (Extended Temperature Version) Topr –40 85 °C Note Others Symbol Rating Power Dissipation PD 1,000mW Allowable Input Current IIN +/- 20mA Ta=25°C IOUT +/- 20mA Ta=25°C Parameter Allowable Output Current Unit 12/20 PEDR45V256A-05 MR45V256A Recommended Operating Conditions Power Supply Voltage [V] Symbol Min. Typ. Max. Power Supply Voltage VCC 3.0 3.3 3.6 Ground Voltage VSS 0 0 0 Parameter Note DC Input Voltage [V] Symbol Min. Max. Input High Voltage VIH VCC x 0.8 VCC＋0.3 Input Low Voltage VIL –0.3 VCC x 0.2 Parameter Note Overshoot/Undershoot tolerance Parameter Symbol Pulse Width Peak “H” input VIH OVERSHOOT  20ns VCC+1.0V “L” input VIL UNDERSHOOT  20ns – 1.0V 13/20 PEDR45V256A-05 MR45V256A DC Characteristics DC Input/Output Characteristics Symbol Condition Min. Max. Unit Output High Voltage VOH IOH =－2mA VCC  0.85 ― V Output Low Voltage VOL IOL =2mA ― VCC  0.15 V Input Leakage Current ILI ― –10 10 µA Output Leakage Current ILO ― –10 10 µA Parameter Note Power Supply Current VCC=Max.to Min, Ta=Topr Parameter Power Supply Current (Standby) Power Supply Current (Operating) Symbol Condition Max. Unit ICCS VIN=0.2V or VCC－0.2V 400 µA ICCA VIN=0.2V or VCC－0.2V, SCK=15MHz, IOUT=0mA 10 mA 14/20 Note PEDR45V256A-05 MR45V256A AC Characteristics (Read Cycle) VCC=Max. to Min., Ta=Topr. MR45V256A Parameter Unit Symbol Note Min. Max. fC D.C. 15 MHz CS# Active setup time tSLCH 10 ― ns CS# In-active setup-time tSHCH 10 ― ns CS# De-select time tSHSL 10 ― ns CS# Active hold time tCHSH 10 ― ns CS# In-active hold-time tCHSL 10 ― ns SCK High time tCH 30 ― ns 1 SCK Low time tCL 30 ― ns 1 SCK Rise time tCLCH ― 1 ns 2 SCK Fall time tCHCL ― 1 ns 2 Data Setup time tDVCH 5 ― ns Data Hold time tCHDX 5 ― ns SCK Low Hold time after HOLD# inactive tHHCH 10 ― ns SCK Low Hold time after HOLD# active tHLCH 10 ― ns SCK High Setup time before HOLD# active SCK High Setup time before HOLD# inactive tCHHL 10 ― ns tCHHH 10 ― ns Output disable time tSHQZ ― 20 ns SCK Low to Output Valid time tCLQV ― 35 ns Output Hold time tCLQX 0 ― ns Output Rise time tQLQH ― 50 ns 2 Output Fall time tQHQL ― 50 ns 2 tHHQX ― 20 ns 2 tHLQZ ― 20 ns 2 Clock frequency HOLD# High to Output Low impedance time HOLD# High to Output High impedance time Note: 1. tCH＋tCL≧1/fC 2. sample value 2 15/20 PEDR45V256A-05 MR45V256A Timing Diagrams Serial Input Timing tSHSL CS# tCHSL tSLCH tSHCH tCHSH SCK tCHCL tDVCH tCHDX SI tCLCH MSB IN LSB IN High Impedance SO Hold Timing CS# tCHHL tHLCH tHHCH SCK tCHHH tHLQZ tHHQX SO SI HOLD# Output Timing CS# tCH SCK tCLQV tCLQX tCLQV tCL tSHQZ tCLQX SO LSB OUT Address, LSB IN tQLQH tQHQL SI 16/20 PEDR45V256A-05 MR45V256A Power-On and Power-Off Characteristics (Under recommended operating conditions) Parameter Power-On CS# High Hold Time Power-Off CS# High Hold Time Power-On Interval Time Symbol tVHEL tEHVL tVLVH Min. 50 100 1 Max.    Unit s ns s Note 1, 2 1 2 Notes: 1. To prevent an erroneous operation, be sure to maintain CS#="H", and set the FeRAM in an inactive state (standby mode) before and after power-on and power-off. 2. Powering on at the intermediate voltage level will cause an erroneous operation; thus, be sure to power up from 0 V. 3. Enter all signals at the same time as power-on or enter all signals after power-on. Power-On and Power-Off Sequences tEHVL tVHEL VCC VCC VCC Min. VCC Min. VIH Min. VIH Min. tVLVH VIL Max. CS# 0V VIL Max. CS# 0V 17/20 PEDR45V256A-05 MR45V256A Read/Write Cycles and Data Retention (Under recommended operating conditions) Parameter Min. 1012 10 Read/Write Cycle Data Retention Max.   Unit Cycle Year Note Unit pF pF Note 1 1 Capacitance Signal Input Capacitance Input/Output Capacitance Symbol CIN COUT Min.   Max. 10 10 Note: Sampling value. Measurement conditions are VIN = VOUT = GND, f = 1MHz, and Ta = 25°C 18/20 PEDR45V256A-05 MR45V256A REVISION HISTORY Page Document No. PEDR45V256A-01 PEDR45V256A-02 Date Previous Edition Current Edition Jun. 03, 2010 – – 1,13 1,13 Input Voltage 7,8,9 7,8,9 fixed CS# waveform 14 14 Sep. 10, 2010 PEDR45V256A-03 Mar. 04, 2011 1,12 1,12 PEDR45V256A-04 Sep. 05, 2011 4 17 4 17 PEDR45V256A-05 Oct. 17, 2011 1-20 1-20 Description Preliminary edition 1 from PJDR45V256A-03 ICCS ICCA temperature version ⇒ Extended version Status Register Input signal state in power-on Changed corporate name and logo to LAPIS Semiconductor. 19/20 PEDR45V256A-05 MR45V256A NOTES No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter "Products"). 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