LV5256GP

Ordering number : ENA1277 Bi-CMOS LSI LV5256GP Overview Operating Mode Switching Type Step-Up/Down Converter The LV5256GP is an operating mode switching type step-up/step-down converter that can switch the operating mode by using the external signal. Functions • Built-in Pch gate drive power supply • Output short-circuit detection by monitoring the input side of the error amplifier • OCP timer function • Software start function • Support for tracking function • Built-in thermal protection circuit • Built-in UVLO • ON/OFF function: Off-time input current smaller than 1µA • Oscillation frequency : 300kHz to 1.5MHz Oscillation frequency can be set by an external resistor Specifications Parameter Maximum input voltage Maximum Ratings at Ta = 25°C Symbol VIN max VDD max Maximum output voltage Maximum output current Allowable input pin voltage Allowable power dissipation Operating temperature Storage temperature VO max IO max VCONT max Pd max Topr Tstg Between OUT and SW RT, FB, IN, OCP, SS, ONOFF, TRAC_IN, DU_SEL, OPC_SEL pins Mounted on a specified board * 0.8 -20 to +85 -40 to +125 W °C °C Conditions Ratings 12 3.6 16 650 VDD Unit V V V mA V * Specified board : 50mm × 40mm × 0.8mm, glass epoxy 4-layer circuit board (2S2P). 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To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 21209 MS PC 20080722-S00003 No.A1277-1/9 LV5256GP Recommended Operating Conditions at Ta = 25°C Parameter Input voltage range Symbol VIN VDD Output voltage range Step-down V1 V2 Step-up VOUT1 VOUT2 Output current IO When in normal operation mode When in tracking operation mode When in normal operation mode When in tracking operation mode Conditions Ratings 4.5 to 10 2.9 to 3.1 1.0 to VIN 0 to VIN 5.3 to 14 VIN to 600 Unit V V V V V V mA Electrical Characteristics at Ta = 25°C, VDD = 3.0V, VIN = 6.0V Parameter Reference voltage Reference voltage for comparison Error amplifier Input voltage range Open loop voltage gain Unity-gain bandwidth Output source current Output sink current IN pin source current FB pin output range TRAC_IN pin source current TRAC_IN pin input operation range Logic input pin block 1 (ONOFF) Input voltage H level Input voltage L level Input current H level Input current L level Logic input pin block 2 (DU_SEL) Input voltage H level Input voltage L level Input pull-down resistance Logic input pin block 3 (OCP_SEL) Input voltage H level Input voltage L level Input pull-down resistance Soft start Soft start source current Soft start sink current Short-circuit protection, SCP Short-circuit protection detection voltage 1 Short-circuit protection detection voltage 2 SCP comparator offset voltage OCP pin source current OCP pin sink current OCP timer latch voltage SCPosf IocpH IocpL Vocp TRAC_IN = 0.7V, operation starts from 0.9V. When in short-circuit protection detection mode When in normal operation mode, OCP = 1.0V 0.3 1.1 -40 10 1 1.2 3 1.3 40 mV µA mA V Vsc2 OCP_SEL=REG_0 *1 × 0.4 V Vsc1 OCP_SEL=GND/OPEN *1 × 0.8 V IssH IssL SS = 0V When reset, SS = 1.0V 7 10 1 13 µA mA VocpiH VocpiL Rocp 100 2.8 0.5 V V kΩ VduiH VduiL Rdu 200 2.8 0.5 V V kΩ VoniH VoniL IoniH IoniL ONOFF = 3.3V ONOFF = 0V 0 0 2.8 0.5 V V µA µA Vrange Av Ft IfboL IfboH IiniL R_fb ItracL R_trac IN = 0 to Vref 0.1 IN = 2.0V, FB = 1.0V IN = 0V, FB = 0V IN = 0V 0.1 100 300 Vref-0.1 0 60 2 2 100 100 300 110 8 1.5 V dB MHz mA µA nA V nA V Vref -1% 1.0 -1% V Symbol Conditions min Ratings typ max Unit Continued on next page. No.A1277-2/9 LV5256GP Continued from preceding page. Ratings Parameter Therml protection, UVLO Thermal protection operating temperature Thermal protection hysteresis UVLO lock release voltage 1 UVLO lock voltage 1 UVLO lock release voltage 2 UVLO lock voltage 2 Oscillator Oscillation frequency Oscillation frequency range Triangular wave lower-side threshold value Triangular wave upper-side threshold value Power supply pin block Current drain Ivin1 Ivin2 Ivdd1 Vout-5V Regulator Output voltage Drooping current Internal 3.3V Regulator Output voltage Drooping current Output characteristics Main switch on resistance (Pch) Main switch on resistance (Nch) Through current prevention dead time Maximum on-duty (step-down) Maximum on-duty (step-up) Converter characteristics Efficiency Step-down Step-up Line regulation Step-down Step-up Load regulation Step-down Step-up η1 η2 ∆V1/VIN ∆VOUT1/VIN ∆V1/IO ∆VOUT1/IO VIN = 5.0V, V = 4.6V, IO = 200mA VIN = 5.0V, VOUT1 = 6.6V, IO = 200mA VIN = 4.5 to 8.6V, V1 = 4.6V, IO = 200mA VIN = 4.5 to 5.5V, VOUT1 = 6.6V, IO = 200mA VIN = 8.4V, V1 = 4.6V, IO = 0 to 200mA VIN = 5.0, VOUT1 = 6.6V, IO = 200mA 0 0 0 0 93 93 % % % % DMAX1 DMAX2 RT = 100kΩ RT = 100kΩ 100 85 % % RonH RonL Tdead VIN = 5V VIN = 5V 0.7 0.7 25 Ω Ω ns Vreg_o Ireg_o Ireg_o = 2.0mA Vreg_o = 2V, VIN = 5V 3.0 3.3 10 3.6 V mA Voutm5 Ivoutm5 Vout-5V regulator, VOUT = 10.0V Vout-5V regulator VOUT-4.5 VOUT-5 20 VOUT-5.5 V mA VIN pin, when converter is in 1MHz operation mode. VIN pin, when in ONOFF stop mode. VDD pin, when in ONOFF stop mode. 2 4 1.0 1.0 mA µA µA VtriH RT = 100kΩ 1.0 V F R_F VtriL RT = 100kΩ RT = 100kΩ 0.8 0.3 0.5 1 1.2 1.5 MHz MHz V Dot VuvloH VuvloL VuvloH2 VuvloL2 Design guarantee value *2 REG_O monitored REG_O monitored VIN pin voltage VIN pin voltage 20 2.8 2.5 3.8 3.5 °C V V V V Tot Design guarantee value *2 175 °C Symbol Conditions min typ max Unit *1 IN pin voltage is the detection point. The lowest voltage among Vref, TRAC_IN, and SS is used. *2 Design guarantee value, and no measurement is performed. No.A1277-3/9 LV5256GP Package Dimensions unit : mm (typ) 3368 1.0 Pd max -- Ta Mounted on a specified board : 50×40×0.8mm3 Glass epoxy 4-layer circuit board (2S2P) TOP VIEW 3.0 SIDE VIEW BOTTOM VIEW (0.125) (0.13) Allowable power dissipation, Pd max – W 0.8 (C0.17) 3.0 0.6 0.4 0.4 0.32 0.2 20 2 0.25 0.5 (0.5) 1 SIDE VIEW 0.8 0 – 20 0 20 40 60 80 100 (0.035) Ambient temperature, Ta – °C SANYO : VCT20(3.0X3.0) Pin Assignment TRAC_IN REG_O 12 15 IN 16 OCP_SEL 17 RT 18 VDD 19 LGND 20 1 14 13 11 10 VOUT-5 9 VOUT LV5256GP Top view OCP 8 SW 7 PGND 6 NC 5 2 SS 3 FB 4 ONOFF VIN DU_SEL NC NC No.A1277-4/9 LV5256GP Block Diagrams and Sample Application Circuit 1 (Step-down) 100kΩ at 1MHz 0.1µF REG_O disable BIAS disable FB V1 or V2 VREF TSD ot Vref1R2 Vref (1.2V) (1.0V±1%) 1.0V 0.5V disable ot uvlo tout RT VIN VIN=4.5 to 10V 1µF VOUT LDO with OPC VOUT-5 Vout-5 L/S Vout-5 VREG 0.022µF V1 (Normal operation) =1.0V to VIN V2 (Tracking operaton) =0V to VIN 4.7µF VREG 3.3V UVLO 2.8V/2.5V uvlo OSC IN + + du_sel disable uvlo R tout SQ + ×0.8 ×0.4 + + + pwm Control Logic 22µH SW SBD PGND LGND 0.01µF at 1.25ms OCP GND/ OPEN DU_SEL L/S du_sel vdd VDD VDD=2.9 to 3.1V 0.1µF VrefR2 disable disable uvlo + Vref Vref1R2 + + + OPC_SEL GND/OPEN: ×0.8 REG_O: ×0.4 TRAC_IN SS ONOFF pin heap 17 pin 0.033µF at 3.3ms Sample Application Circuit 2 (Step-up) 100kΩ at 1MHz 0.1µF REG_O disable BIAS disable FB VOUT1 or VOUT2 VREF TSD ot Vref1R2 Vref (1.2V) (1.0V±1%) 1.0V 0.5V disable ot uvlo tout RT VIN VIN=4.5~10V 1µF VOUT VREG 3.3V UVLO 2.8V/2.5V uvlo OSC 0.022µF LDO with OPC Vout-5 L/S Vout-5 VREG VOUT-5 VOUT1 (Normal operation) =5.3V to 14V VOUT2 (Tracking operaton) =VIN or more 4.7µF IN + + du_sel disable uvlo R tout SQ + ×0.8 ×0.4 + + + pwm Control Logic 10µH SW 0.01µF at 1.25ms OCP PGND LGND REG_O DU_SEL L/S du_sel vdd VDD VDD=2.9~3.1V 0.1µF VrefR2 disable disable uvlo + Vref Vref1R2 + + + OPC_SEL GND/OPEN: ×0.8 REG_O: ×0.4 TRAC_IN SS ONOFF pin heap 17 pin 0.033µF at 3.3ms No.A1277-5/9 LV5256GP Pin Functions Pin No. 1 2 6 3 ONOFF ON/OFF signal input pin. Threshold level is TTL level. Maximum withstand voltage is VDD. VDD Pin Name NC Description No connection. Must be kept open. Equivalent Circuit 3 4 5 VIN DU_SLE Power supply pin of the IC. Apply the input voltage. Step-up/down switching pin. The IC goes in step-up mode by connecting this pin to REG_O pin, and in step-down mode by connecting this pin to GND or leaving this pin open. An internal pull-down resistor (200kΩ) is provided between DU_SEL and GND pins. VDD 5 200kΩ 7 8 PGND SW Power ground pin. The source of the output transistor (Nch-MOSFET) is connected. Switching element. A 0.7Ω (typ) Nch switch is inserted between this pin and PGND, and a 0.7Ω (typ) Pch switch is connected between this pin and VOUT. In step-down mode, insert an inductor between the switching node and power supply output, and in step-up mode insert an inductor between this pin and power supply input. VOUT 8 9 VOUT Source potential of the internal Pch-MOSFET. In step-down mode, apply the input voltage. In step-up mode, apply the power supply voltage. 10 VOUT-5 Internal Pch-MOSFET gate suplly voltage generation pin. Used to generate a voltage with a level equal to VOUT pin voltage-5V by the internal LDO with OCP. 11 OCP Overcurrent detection timer setup pin. Connect a capacitor between this pin and ground to define the time interval between the beginning of the overcurrent state and the IC latches off. The capacitor is charged by the 10µA internal constant current source. If the OCP_SEL pin is kept open or connected to GND, the IC identifies a short-circuit and starts the timer counter when the voltage at the IN pin falls below 0.8 times the voltage of Vref, TRAC_IN or SS, whichever is lower. If the OCP_SEL pin is connected to REG_O, the IC compares the voltage at the IN pin with 0.4 times the voltage. When the voltage at this pin goes beyond 1.25V, the IC latches off. The latch-off state is reset by the off signal at the ON/OFF pin or the UVLO lock. VIN REG_O 10µA 10kΩ 11 500Ω 1kΩ 12 REG_O 3.3V regulator output pin. VIN 12 50Ω 32kΩ 20kΩ Continued on next page. No.A1277-6/9 LV5256GP Continued from preceding page. Pin No. 13 SS Pin Name Description Capacitor connection pin for soft start. The capacitor connected to this pin is charged by the internal 10µA constant current. The interval during which this voltage reaches Vref is called the soft start period. The voltage is clipped to approx. 2V after the soft start. This pin is pulled down to the ground level when ONOFF/UVLO lock mode. REG_O 1.25V VIN Equivalent Circuit REG_O 10µA 10kΩ 13 500Ω 14 TRAC_IN Reference voltage input pin for tracking power supply operating. A voltage from 0V up to Vref applied to this pin serves as the reference voltage for determining the output voltage. This pin must be connected to the SS pin when it is not to be used. VIN REG_O 14 1kΩ REG_O 15 FB Error amplifier output pin. Connect a phase compensation component between this pin and IN pin. REG_O 100µA VIN 400Ω 15 1.25V 1kΩ 16 IN Output voltage input pin. Apply the resistor divided output voltage to this pin. VIN REG_O SS TRAC_IN Vref 1kΩ 16 REG_O 17 OCP_SEL OCP detection voltage switching pin, A 100kΩ pull-down resistor is provided between OCP_SEL and GND. The IC enters the 0.8 times detection mode when this pin is connected to GND or kept open and enters the 0.4 times detection mode when the pin is connected to the REG_O pin. VDD 17 100kΩ Continued on next page. No.A1277-7/9 LV5256GP Continued from preceding page. Pin No. 18 RT Pin Name Description Oscillation frequency setting pin. Connect a resistor between this pin and GND. A 100kΩ resistor causes the oscillator to oscillate at 1MHz (typ.). VDD 500Ω Equivalent Circuit 18 10kΩ 19 20 VDD LGND Logic system power supply. Apply 3.0V±0.1V to this pin from an external source. Logic system ground pin. All voltages are measured with respect to this voltage level. Startup Sequence VDD ONOFF VIN ONOFF:H REG_O startup REG_O UVLO release VOUT-5 startup VOUT-5 VOUT-5 normal judgment SS start SS SW Power supply operation beginning * Be sure to set the ONOFF to 0V when starts or stops VDD. And apply voltage to VIN after VDD started up. No.A1277-8/9 LV5256GP Output Voltage Setting Method The LV5256GP can produce any arbitrary output voltage. The output voltage is set by the resistor inserted between the IN pin (pin 16) and GND, and IN pin and output voltage. The calculating formula for setting the output voltage by using the output voltage setup lower-side resistor R1 and the output voltage setup upper-side resistor R2 is as follows: Output voltage (Step-down) V1 or V2 (Step-up) VOUT1 or VOUT2 R2 R1 IN R2  R2  Q Vref = 1.00 (typ ) (Output voltage) = 1 +  × Vref = 1 + R1  R1  SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of February, 2009. Specifications and information herein are subject to change without notice. PS No.A1277-9/9