74ACT16374TTR

74ACT16374 16-BIT D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS (NON INVERTED) ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 120MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), VIL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V IMPROVED LATCH-UP IMMUNITY TSSOP ORDER CODES PACKAGE PIN CONNECTION e t le ) s t( T&R c u d TSSOP DESCRIPTION The 74ACT16374 is an advanced high-speed CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. This 16 bit D-Type Flip-Flop is controlled by two clock inputs (CK) and two output enable inputs (OE). The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs. While the (OE) input is low, the outputs will be in a normal logic state (high or low logic level); while OE is high, the outputs will be in a high impedance state. The output control does not affect the internal operation of flip-flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. ) s ( ct TUBE 74ACT16374TTR o r P o s b O - u d o r P e t e l o s b O February 2003 1/10 74ACT16374 INPUT AND OUTPUT EQUIVALENT CIRCUIT *IEC LOGIC SYMBOLS PIN DESCRIPTION PIN No SYMBOL 1 1OE 2, 3, 5, 6, 8, 9, 11, 12 13, 14, 16, 17, 19, 20, 22, 23 24 1Q0 to 1Q7 2Q0 to 2Q7 2OE 3 State Output Enable Input (Active LOW) 3-State Outputs ) s ( ct o s b O - u d o r P e t e l o TRUTH TABLE O INPUTS 2/10 OUTPUT OE CK D H X Q X Z L X NO CHANGE* L L L L H H X : Don‘t Care Z : High Impedance e t le 3-State Outputs 3 State Output Enable Input (Active LOW) 25 2CK Clock Input (LOW-to-HIGH Edge Trigger) 36, 35, 33, 32, 2D0 to 2D7 Data Inputs 30, 29, 27, 26 47, 46, 44, 43, 1D0 to 1D7 Data Inputs 41, 40, 38, 37 48 1CK Clock Input (LOW-to-HIGH Edge Trigger) 4, 10, 15, 21, GND Ground (0V) 28, 34, 39, 45 7, 18, 31, 42 VCC Positive Supply Voltage bs c u d NAME AND FUNCTION o r P ) s t( 74ACT16374 LOGIC DIAGRAM This logic diagram has not to be used to estimate propagation delays c u d ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Current e t le ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) ct (s) u d o o r P Value Supply Voltage o s b O - ) s t( Unit -0.5 to +7 V -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V ± 20 mA ± 20 mA ± 50 mA V ± 400 mA -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. r P e t e l o s b O 3/10 74ACT16374 RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Value Unit Supply Voltage 4.5 to 5.5 V VI Input Voltage 0 to VCC V VO Output Voltage 0 to VCC V Top Operating Temperature -55 to 125 °C 8 ns/V dt/dv Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1) 1) VIN from 0.8V to 2.0V DC SPECIFICATIONS Test Condition Symbol Parameter VIH High Level Input Voltage VIL Low Level Input Voltage VOH High Level Output Voltage Low Level Output Voltage VOL Input Leakage Current High Impedance Output Leakege Current Max ICC/Input II IOZ ICCT t e l o IOLD IOHD Dynamic Output Current (note 1, 2) TA = 25°C VCC (V) 4.5 5.5 4.5 5.5 VO = 0.1 V or VCC-0.1V Min. Typ. 2.0 2.0 1.5 1.5 VO = 0.1 V or VCC-0.1V 1.5 1.5 IO=-50 µA 4.4 4.49 5.5 5.4 5.49 4.5 IO=-24 mA 3.86 5.5 IO=-24 mA 4.86 4.5 IO=50 µA 5.5 IO=50 µA 4.5 IO=24 mA 5.5 IO=24 mA 5.5 VI = VCC or GND 4/10 Min. Max. 2.0 2.0 c u d 0.8 0.8 ro 4.4 P e let 5.4 3.76 4.76 so Max. ) s t( V 0.8 0.8 4.4 V 5.4 3.7 4.7 0.1 0.1 0.1 0.001 0.1 0.1 0.1 0.36 0.44 0.5 0.36 0.44 0.5 ± 0.1 ±1 ±1 µA ± 0.5 ±5 ± 10 µA 1.5 1.6 mA 80 80 µA VOLD = 1.65 V max 75 50 mA VOHD = 3.85 V min -75 -50 mA (s) b O - VI = VIH or VIL VO = VCC or GND 5.5 VI = VCC - 2.1V 5.5 VI = VCC or GND 0.6 8 1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω s b O Min. Unit 0.001 t c u 5.5 -55 to 125°C 0.8 0.8 IO=-50 µA 5.5 Max. -40 to 85°C 2.0 2.0 4.5 d o r P e Quiescent Supply Current ICC Value V 74ACT16374 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) Test Condition Symbol Parameter tPLH Propagation Delay Time CK to Q 5.0(*) Output Enable Time 5.0(*) Output Disable Time 5.0(*) tPHL tPZL tPZH tPLZ tPHZ tW ts th fMAX CLOCK Pulse Width HIGH or LOW Setup Time D to CK, HIGH or LOW Hold Time D to CK, HIGH or LOW Maximum Clock Frequency Value TA = 25°C VCC (V) Min. 5.0(*) Input Capacitance COUT CPD Output Capacitance Power Dissipation Capacitance (note 1) o r P e Min. Max. 4.3 6.3 12.4 13.2 4.5 6.7 12.2 13.1 5.7 8.5 13.4 14.3 4.8 7.2 11.9 12.7 5.5 8.0 9.8 10.2 4.7 6.7 10.4 10.9 Unit Max. ns ns ns 2.5 1.9 2.9 2.9 ns 5.0(*) 1.6