AN1762
APPLICATION NOTE
L6205, L6206, L6207 DUAL FULL BRIDGE DRIVERS
by Vincenzo Marano
Modern motion control applications need more flexibility that can be addressed only with specialized IC
products. The L6205, L6206, L6207 are dual full bridge drivers ICs specifically developed to drive a wide
range of motors. These ICs are one-chip cost effective solutions that include several unique circuit design
features. These features allow the devices to be used in many applications including DC and stepper motor
driving. The principal aim of this development project was to produce easy to use, fully protected power ICs.
In addition several key functions such as protection circuit and PWM current control drastically reduce external components count to meet requirements for many different applications.
1
INTRODUCTION
The L6205, L6206, L6207 are highly integrated, mixed-signal power ICs that allow the user to easily design a
control system for two-phase bipolar stepper motors, multiple DC motors and a wide range of inductive loads.
Figure 1 to Figure 3 show the L6205, L6206, L6207 block diagrams. Each IC integrates eight Power DMOS plus
other added features for safe operation and flexibility. The L6207 also features a constant tOFF PWM current
control technique (Synchronous mode ) for each of the two full bridges.
Figure 1. L6205 block diagram.
VBOOT
VBOOT
VBOOT
VCP
VSA
VBOOT
CHARGE
PUMP
OCDA
OVER
CURRENT
DETECTION
10V
THERMAL
PROTECTION
ENA
OUT1A
OUT2A
10V
GATE
LOGIC
IN1A
SENSEA
IN2A
VOLTAGE
REGULATOR
10V
5V
BRIDGE A
OCDB
OVER
CURRENT
DETECTION
VSB
OUT1B
ENB
OUT2B
GATE
LOGIC
SENSEB
IN1B
IN2B
BRIDGE B
D99IN1091A
December 2003
1/53
AN1762 APPLICATION NOTE
Figure 2. L6206 block diagram.
VBOOT
VBOOT
VBOOT
VCP
VSA
VBOOT
CHARGE
PUMP
PROGCLA
OCDA
OCDA
OVER
CURRENT
DETECTION
OUT1A
10V
THERMAL
PROTECTION
OUT2A
10V
GATE
LOGIC
ENA
IN1A
SENSEA
IN2A
VOLTAGE
REGULATOR
10V
5V
BRIDGE A
OCDB
OCDB
OVER
CURRENT
DETECTION
VSB
PROGCLB
OUT1B
OUT2B
GATE
LOGIC
ENB
SENSEB
IN1B
IN2B
BRIDGE B
D99IN1088A
Figure 3. L6207 block diagram.
VBOOT
VBOOT
VBOOT
VCP
VSA
VBOOT
CHARGE
PUMP
OCDA
OVER
CURRENT
DETECTION
OUT1A
10V
THERMAL
PROTECTION
OUT2A
10V
GATE
LOGIC
ENA
IN1A
SENSEA
IN2A
PWM
VOLTAGE
REGULATOR
10V
ONE SHOT
MONOSTABLE
MASKING
TIME
+
SENSE
COMPARATOR
-
5V
VREFA
RCA
BRIDGE A
OCDB
VSB
OVER
CURRENT
DETECTION
OUT1B
OUT2B
SENSEB
ENB
GATE
LOGIC
VREFB
RCB
IN1B
IN2B
BRIDGE B
D99IN1085A
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AN1762 APPLICATION NOTE
Table of Contents
1
2
3
4
5
6
INTRODUCTION ................................................................................................................................1
MAIN DIFFERENCES BETWEEN L6205, L6206, L6207 ..................................................................4
DESIGNING AN APPLICATION WITH L6205, L6206, L6207 ...........................................................4
3.1 Current Ratings ........................................................................................................................4
3.2 Voltage Ratings and Operating Range ....................................................................................4
3.3 Choosing the Bulk Capacitor....................................................................................................6
3.4 Layout Considerations .............................................................................................................7
3.5 Sensing Resistors ....................................................................................................................9
3.6 Charge pump external components .......................................................................................10
3.7 Sharing the Charge Pump Circuitry .......................................................................................11
3.8 Reference Voltage for PWM Current Control (L6207 ONLY).................................................12
3.9 Input Logic pins ......................................................................................................................13
3.10 EN pins...................................................................................................................................13
3.11 Programmable off-time Monostable (L6207 ONLY)..............................................................14
3.11.1 Off-time Selection and minimum on-time (L6207 ONLY) ................................................16
3.11.2 Slow Decay Mode (L6207 ONLY) ...................................................................................17
3.12 Over Current Protection ........................................................................................................18
3.13 Adjusting the Over Current Detection trip point (L6206 ONLY) ............................................21
3.14 Paralleling two Full Bridges...................................................................................................23
3.14.1 Paralleling two Full Bridges to get a single Full Bridge ....................................................23
3.14.2 Paralleling the four Half Bridges to get a single Half Bridge.............................................26
3.15 Power Management ..............................................................................................................27
3.15.1 Maximum output current vs. selectable devices..............................................................27
3.15.2 Power Dissipation Formulae for different sequences ......................................................28
APPLICATION EXAMPLE (L6207) ..................................................................................................32
4.1 Decay mode, sensing resistors and reference voltage. .........................................................32
APPENDIX - EVALUATION BOARDS .............................................................................................33
5.1 PractiSPIN..............................................................................................................................33
5.2 EVAL6205N ...........................................................................................................................34
5.2.1 Important Notes ................................................................................................................35
5.3 EVAL6206N ...........................................................................................................................39
5.3.1 Important Notes ................................................................................................................40
5.4 EVAL6206PD .........................................................................................................................44
5.4.1 Important Notes ................................................................................................................45
5.5 EVAL6207N ...........................................................................................................................49
5.5.1 Important Notes ................................................................................................................50
REFERENCES.................................................................................................................................53
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AN1762 APPLICATION NOTE
2
MAIN DIFFERENCES BETWEEN L6205, L6206, L6207
L6205, L6206 and L6207 are DMOS Dual Full Bridge ICs.
L6205 (see Figure 1) includes logic for CMOS/TTL interface, a charge pump that provide auxiliary voltage to
drive the high-side DMOS, non dissipative over current protection circuitry on the high-side DMOS, with fixed
trip point set at 5.6 A (see Over Current Protection Section), over temperature protection, Under Voltage LockOut for reliable start-up.
In addition, L6206 gives the possibility of adjusting the trip point of the over current protection for each of the
two full-bridges (through two external resistors), and its internal open-drain mosfets (see Over Current Protection Section) are not internally connected to EN pins but to separate OCD pins, allowing easier external diagnostics and overcurrent management.
L6207 has Over Current protection function with fixed trip point set at 5.6 A and internal open-drain mosfets
connected to EN pins, as the L6205, but it also integrates two PWM current controller for each of the two fullbridges (see Programmable off-time Monostable section).
3
DESIGNING AN APPLICATION WITH L6205, L6206, L6207
3.1 Current Ratings
With MOSFET (DMOS) devices, unlike bipolar transistors, current under short circuit conditions is, at first approximation, limited by the RDS(ON) of the DMOS themselves and could reach very high values. L6205, L6206,
L6207 Out pins and the two VSA and VSB pins are rated for a maximum of 2.8A r.m.s. and 5.6A peak (typical
values), corresponding to a total (for the whole IC) 5.6A rms (11.2A peak). These values are meant to avoid
damaging metal structures, including the metallization on the die and bond wires. In practical applications,
though, maximum allowable current is less than these values, due to power dissipation limits (see Power
Management section). The devices have a built-in Over Current Detection (OCD) that provides protection
against short circuits between the outputs and between an output and ground (see Over Current Protection
section).
3.2 Voltage Ratings and Operating Range
The L6205, L6206, L6207 requires a single supply voltage (VS), for the motor supply. Internal voltage regulators
provide the 5V and 10V required for the internal circuitry. The operating range for VS is 8 to 52V. To prevent
working into undesirable low supply voltage an Under Voltage Lock Out (UVLO) circuit shuts down the device
when supply voltage falls below 6V; to resume normal operating conditions, VS must then exceed 7V. The hysteresis is provided to avoid false intervention of the UVLO function during fast VS ringings. It should be noted,
however, that DMOS's RDS(ON) is a function of the VS supply voltage. Actually, when VS is less than 10V,
RDS(ON) is adversely affected, and this is particularly true for the High Side DMOS that are driven from VBOOT
supply. This supply is obtained through a charge pump from the internal 10V supply, which will tend to reduce
its output voltage when VS goes below 10V. Figure 4 shows the supply voltage of the high side gate drivers
(VBOOT - VS) versus the supply voltage (VS).
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AN1762 APPLICATION NOTE
Figure 4. High side gate drivers supply voltage versus supply voltage.
8
7 .6
VBOOT - VS
[V]
7 .2
6 .8
6 .4
6
8
8 .5
9
9 .5
10
1 0 .5
VS [V]
Note that VS must be connected to both VSA and VSB since the bootstrap voltage (at VBOOT pin) is the same for
the two H-bridges. The integrated DMOS have a rated Drain-Source breakdown voltage of 60V. However VS
should be kept below 52V, since in normal working conditions the DMOS see a Vds voltage that will exceed VS
supply. In particular, during a phase change (when each output of the same H-bridge switches from VS to GND
or vice versa, for example to reverse the current in the load) at the beginning of the dead-time (when all the
DMOS are off) the SENSE pin sees a negative spike due to a not negligible parasitic inductance of the PCB
path from the pin to GND. This spike is followed by a stable negative voltage due to the drop on RSENSE. One
of the two OUT pins of the bridge sees a similar behavior, but with a slightly larger voltage due to the forward
recovery time of the integrated freewheeling diode and the forward voltage drop across it (see Figure 5). Typical
duration of this spike is 30ns. At the same time, the other OUT pin of the same bridge sees a voltage above VS,
due to the PCB inductance and voltage drop across the high-side (integrated) freewheeling diode, as the current
reverses direction and flows into the bulk capacitor. It turns out that the highest differential voltage can be observed between the two OUT pins of the same bridge, during the dead-time at a phase change, and this must
always be kept below 60V [3].
Figure 5. Currents and voltages during the dead time at a phase change.
ESR
VS
PCB Parasitic
Inductance
ESL
Bulk Capacitor
Equivalent Circuit
OUT2
OUT1
RSENSE*I+VF(Diode)
Dangerous
High Differential Voltage
RSENSE*I
VS+VF(Diode)
SENSE
RSENSE
PCB Parasitic
Inductance
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AN1762 APPLICATION NOTE
Figure 6 shows the voltage waveforms at the two OUT pins referring to a possible practical situation, with a peak
output current of 2.8A, VS = 52V, RSENSE = 0.33Ω, TJ = 25°C (approximately) and a good PCB layout. Below
ground spike amplitude is -2.65V for one output; the other OUT pin is at about 57V. In these conditions, total
differential voltage reaches almost 60V, which is the absolute maximum rating for the DMOS. Keeping differential voltage between two Output pins belonging to the same Full Bridge within rated values is a must that can
be accomplished with proper selection of Bulk capacitor value and equivalent series resistance (ESR), according to current peaks and chopping style and adopting good layout practices to minimize PCB parasitic inductances (see below) [3].
Figure 6. Voltage at the two outputs during the dead time at a phase change.
Out 1
Out 2
3.3 Choosing the Bulk Capacitor
Since the bulk capacitor, placed between VS and GND pins, is charged and discharged during IC operation, its
AC current capability must be greater than the r.m.s. value of the charge/discharge current. In the case of a
PWM current regulation, the current flows from the capacitor to the IC during the on-time (tON) and from the IC
(implementing a fast decay current recirculation technique) or from the power supply (implementing a slow decay current recirculation technique) to the capacitor during the off-time (tOFF). The r.m.s. value of the current
flowing into the bulk capacitor depends on peak output current, output current ripple, switching frequency, dutycycle and chopping style. It also depends on power supply characteristics. A power supply with poor high frequency performances (or long, inductive connections to the IC) will cause the bulk capacitor to be recharged
slowly: the higher the current control switching frequency, the higher the current ripple in the capacitor; r.m.s.
current in the capacitor, however, does not exceed the r.m.s. output current. Bulk capacitor value (C) and the
ESR determine the amount of voltage ripple on the capacitor itself and on the IC. In slow decay, neglecting the
dead-time and output current ripple, and assuming that during the on-time the capacitor is not recharged by the
power supply, the voltage at the end of the on-time is:
t O N
- ,
V S – I OUT ⋅ ESR + -------
C
so the supply voltage ripple is:
t O N
I OUT ⋅ ESR + -------- ,
C
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AN1762 APPLICATION NOTE
where IOUT is the output current. With fast decay, instead, recirculating current recharges the capacitor, causing
the supply voltage to exceed the nominal voltage. This can be very dangerous if the nominal supply voltage is
close to the maximum recommended supply voltage (52V). In fast decay the supply voltage ripple is about:
t ON + t O FF
I OUT ⋅ 2 ⋅ ESR + --------------------------- ,
C
always assuming that the power supply does not recharge the capacitor, and neglecting the output current ripple
and the dead-time. Usually (if C > 100 µF) the capacitance role is much less than the ESR, then supply voltage
ripple can be estimated as:
IOUT · ESR in slow decay
2 · IOUT · ESR in fast decay
For Example, if a maximum ripple of 500mV is allowed and IOUT = 2A, the capacitor ESR should be lower than:
0.5 V
ESR < ------------ = 250mΩ in slow decay, and
2A
1 0.5 V
ESR < --- ⋅ ------------ = 1 25mΩ in fast decay.
2 2A
Actually, current sunk by VSA and VSB pins of the device is subject to higher peaks due to reverse recovery
charge of internal freewheeling diodes. Duration of these peaks is, tough, very short, and can be filtered using
a small value (100÷200 nF), good quality ceramic capacitor, connected as close as possible to the VSA, VSB
and GND pins of the IC. Bulk capacitor will be chosen with maximum operating voltage 25% greater than the
maximum supply voltage, considering also power supply tolerances. For example, with a 48V nominal power
supply, with 5% tolerance, maximum voltage is 50.4V, then operating voltage for the capacitor should be at least
63V.
3.4 Layout Considerations
Working with devices that combine high power switches and control logic in the same IC, careful attention has
to be paid to the PCB layout. In extreme cases, Power DMOS commutation can induce noises that could cause
improper operation in the logic section of the device. Noise can be radiated by high dv/dt nodes or high di/dt
paths, or conducted through GND or Supply connections. Logic connections, especially high-impedance nodes
(actually all logic inputs, see further), must be kept far from switching nodes and paths. With the L6205, L6206,
L6207, in particular, external components for the charge pump circuitry should be connected together through
short paths, since these components are subject to voltage and current switching at relatively high frequency
(600kHz). Primary mean in minimizing conducted noise is working on a good GND layout (see Figure 7).
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AN1762 APPLICATION NOTE
Figure 7. Typical Application and Layout suggestions.
Motors or
other loads
D1
D2
C4
C1
R1
OUT1A OUT2A
OUT1B OUT2B
VBOOT
CP
VSA
VSB
SENSEA
SENSEB
L6205, L6206, L6207
RS1
+
RS2
C2
C3
VS = 8 ÷ 52 V
GND GND GND GND
Logic
GND
High current GND tracks (i.e. the tracks connected to the sensing resistors) must be connected directly to the
negative terminal of the bulk capacitor. A good quality, high-frequency bypass capacitor is also required (typically a 100nF÷200nF ceramic would suffice), since electrolytic capacitors show a poor high frequency performance. Both bulk electrolytic and high frequency bypass capacitors have to be connected with short tracks to
VSA, VSB and GND. On the L6205, L6206, L6207 GND pins are the Logic GND, since only the quiescent current
flows through them. Logic GND and Power GND should be connected together in a single point, the bulk capacitor, to keep noise in the Power GND from affecting Logic GND. Specific care should be paid layouting the
path from the SENSE pins through the sensing resistors to the negative terminal of the bulk capacitor (Power
Ground). These tracks must be as short as possible in order to minimize parasitic inductances that can cause
dangerous voltage spikes on SENSE and OUT pins (see the Voltage Ratings and Operating Range section);
for the same reason the capacitors on VSA, VSB and GND should be very close to the GND and supply pins.
Refer to the Sensing Resistors section for information on selecting the sense resistors. Traces that connect to
VSA, VSB, SENSEA, SENSEB, and the four OUT pins must be designed with adequate width, since high currents
are flowing through these traces, and layer changes should be avoided. Should a layer change prove necessary, multiple and large via holes have to be used. A wide GND copper area can be used to improve power
dissipation for the device.
Figure 8 shows two typical situations that must be avoided. An important consideration about the location of the
bulk capacitors is the ability to absorb the inductive energy from the load, without allowing the supply voltage to
exceed the maximum rating. The diode shown in Figure 8 prevents the recirculation current from reaching the
capacitors and will result in a high voltage on the IC pins that can destroy the device. Having a switch or a power
connection that can disconnect the capacitors from the IC, while there is still current in the motor, will also result
in a high voltage transient since there is no capacitance to absorb the recirculation current.
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AN1762 APPLICATION NOTE
Figure 8. Two situations that must be avoided.
VSA
DON’T put a diode here!
Recirculating current cannot flow into the
bulk capacitor and causes a high voltage
spike that can destroy the IC.
VSB
SENSE A
SENSE B
L6205, L6206, L6207
+
R5
C6
GND GND GND GND
C7
VS = 8 ÷ 52 V
-
DON’T connect the Logic GND here
Voltage drop due to current in sense
path can disturb logic GND.
3.5 Sensing Resistors
Each motor winding current is flowing through the corresponding sensing resistor, causing a voltage drop that
can be used, by the logic (integrated in the L6207; an external logic can be used with L6205 and L6206), to
control the peak value of the load current. Two issues must be taken into account when choosing the RSENSE
value:
– The sensing resistor dissipates energy and provides dangerous negative voltages on the SENSE pin
during the current recirculation. For this reason the resistance of this component should be kept low.
– The voltage drop across RSENSE is compared with a reference voltage (on Vref pin) by the internal comparator (L6207 only). The lower is the RSENSE value, the higher is the peak current error due to noise
on Vref pin and to the input offset of the current sense comparator: too small values of RSENSE must be
avoided.
A good compromise is calculating the sensing resistor value so that the voltage drop, corresponding to the peak
current in the load (Ipeak), is about 0.5 V: RSENSE = 0.5 V / Ipeak.
It should be clear that sensing resistor must absolutely be non-inductive type in order to avoid dangerous negative spikes on SENSE pins. Wire-wounded resistors cannot be used here, while Metallic film resistors are recommended for their high peak current capability and low inductance. For the same reason the connections
between the SENSE pins, C6, C7, VSA, VSB and GND pins (see Figure 7) must be taken as short as possible
(see also the Layout Considerations section).
The average power dissipated by the sensing resistor is:
Fast Decay Recirculation: PR ≈ Irms2 · RSENSE
Slow Decay Recirculation: PR ≈ Irms2 · RSENSE · D,
D is the duty-cycle of the PWM current control, Irms is the r.m.s. value of the load current.
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AN1762 APPLICATION NOTE
Nevertheless, sensing resistor power rating should be chosen taking into account the peak value of the dissipated power:
2
P R ≈ Ipk ⋅ R S ENSE
,
where Ipk is the peak value of the load current.
Using multiple resistors in parallel will help obtaining the required power rating with standard resistors, and reduce the inductance.
RSENSE tolerance reflects on the peak current error: 1% resistors should be preferred.
The following table shows RSENSE recommended values (to have 0.5V drop on it) and power ratings for typical
examples of current peak values.
Ipk
RSENSE Value [Ω]
RSENSE Power Rating [W]
0.5
1
0.25
Alternatives
1
0.5
0.5
2 X 1Ω, 0.25W paralleled
1.5
0.33
0.75
3 X 1Ω, 0.25W paralleled
2
0.25
1
4 X 1Ω, 0.25W paralleled
3.6 Charge pump external components
An internal oscillator, with its output at CP pin, switches from GND to 10V with a typical frequency of 600kHz
(see Figure 9).
Figure 9. Charge Pump.
VS + 10 V - VD1
VS + 10 V - VD1 - VD2
f = 600 kHz
VS - VD1
C8
D1
D2
C5
R4
VBOOT
To High-Side
Gate Drivers
VSA
CP
VSB
10 V
RDS(ON) = 70Ω
Charge Pump
Oscillator
10 V
5V
10 V
RDS(ON) = 70Ω
f = 600 kHz
L6205, L6206, L6207
When the oscillator output is at ground, C5 is charged by VS through D2. When it rises to 10V, D2 is reverse
biased and the charge flows from C5 to C8 through D1, so the VBOOT pin, after a few cycles, reaches the maximum voltage of VS + 10V - VD1 - VD2, which supplies the high-side gate drivers.
With a differential voltage between VS and VBOOT of about 9V and both the bridges switching at 50kHz, the typical current drawn by the VBOOT pin is 1.85 mA.
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AN1762 APPLICATION NOTE
Resistor R4 is added to reduce the maximum current in the external components and to reduce the slew rate of
the rising and falling edges of the voltage at the CP pin, in order to minimize interferences with the rest of the
circuit. For the same reason care must be taken in realizing the PCB layout of R4, C5, D1, D2 connections (see
also the Layout Considerations section). Recommended values for the charge pump circuitry are:
D1, D2 : 1N4148
R4
: 100 Ω
C5
: 10nF 100V ceramic
C8
: 220nF 25V ceramic
(1/8 W)
Due to the high charge pump frequency, fast diodes are required. Connecting the cold side of the bulk capacitor
(C8) to VS instead of GND the average current in the external diodes during operation is less than 10 mA (with
R4 = 100 Ω); at startup (when VS is provided to the IC) is less than 200 mA while the reverse voltage is about
10 V in all conditions. 1N4148 diodes withstand about 200 mA DC (1 A peak), and the maximum reverse voltage
is 75 V, so they should fit for the majority of applications.
3.7 Sharing the Charge Pump Circuitry
If more than one device is used in the application, it's possible to use the charge pump from one L6205, L6206
or L6207 to supply the VBOOT pins of several ICs. The unused CP pins on the slaved devices are left unconnected, as shown in Figure 10. A 100nF capacitor (C8) should be connected to the VBOOT pin of each device.
Supply voltage pins (VS) of the devices sharing the charge pump must be connected together.
The higher the number of devices sharing the same charge pump, the lower will be the differential voltage available for gate drive (VBOOT - VS), causing a higher RDS(ON) for the high side DMOS, so higher dissipating power.
In this case it's recommended to omit the resistor on the CP pin, obtaining a higher current capability of the
charge pump circuitry.
Better performance can also be obtained using a 33nF capacitor for C5 and using schottky diodes (for example
BAT47 are recommended).
Sharing the same charge pump circuitry for more than 3÷4 devices is not recommended, since it will reduce the
VBOOT voltage increasing the high-side MOS on-resistance and thus power dissipation.
Figure 10. Sharing the charge pump circuitry.
To other Devices
D1 = BAT47
D2 = BAT47
C8 = 100nF
C18 = 100 nF
C5 = 33nF
VBOOT
CP
VSA
VSB
To High-Side
Gate Drivers
L6205, L6206, L6207
VBOOT
CP
VSA
VSB
To High-Side
Gate Drivers
L6205, L6206, L6207
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AN1762 APPLICATION NOTE
3.8 Reference Voltage for PWM Current Control (L6207 ONLY)
The L6207 has two analog inputs, VrefA and VrefB, connected to the internal sense comparators, to control the
peak value of the motor current through the integrated PWM circuitry. In typical applications these pins are connected together, in order to obtain the same current in the two motor windings. A fixed reference voltage can be
easily obtained through a resistive divider from an available 5 V voltage rail (maybe the one supplying the µC
or the rest of the application) and GND.
A very simple way to obtain a variable voltage without using a DAC is to low-pass filter a PWM output of a µC
(see Figure 11).
Assuming that the PWM output swings from 0 to 5V, the resulting voltage will be:
5V ⋅ D µC ⋅ R DIV
V re f = ---------------------------------------R LP + R DIV
where DµC is the duty-cycle of the PWM output of the µC.
Assuming that the µC output impedance is lower than 1kΩ, with RLP = 56kΩ, RDIV = 15kΩ, CLP = 10nF and a
µC PWM switching from 0 to 5V at 100kHz, the low pass filter time constant is about 0.12 ms and the remaining
ripple on the Vref voltage will be about 20 mV. Using higher values for RLP, RDIV and CLP will reduce the ripple,
but the reference voltage will take more time to vary after changing the duty-cycle of the µC PWM, and too high
values of RLP will also increase the impedance of the Vref net at low frequencies, causing a poor noise immunity.
As sensing resistor values are typically kept small, a small noise on Vref input pins might cause a considerable
error in the output current. It's then recommended to decouple these pins with ceramic capacitors of some tens
of nF, placed very close to Vref and GND pins. Note that Vref pins cannot be left unconnected, while, if connected
to GND, zero current is not guaranteed due to voltage offset in the sense comparator. The best way to cut down
(IC) power consumption and clear the load current is pulling down the EN pins. With very small reference voltage, PWM integrated circuitry can loose control of the current due to the minimum allowed duration of tON (see
the Programmable off-time Monostable section).
Figure 11. Obtaining a variable voltage through a PWM output of a µC.
PWM Output
of a µC
RLP
V ref
RDIV
CLP
GND
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AN1762 APPLICATION NOTE
3.9 Input Logic pins
IN1A, IN2A, IN1B, IN2B are CMOS/TTL compatible logic input pins. The input comparator has been realized with hysteresis to ensure the required noise immunity. Typical values for turn-on and turn-off thresholds are Vth,ON = 1.8V and
Vth,OFF = 1.3V. Pins are ESD protected (see Figure 12) (2kV human-body electro-static discharge), and can be directly
connected to the logic outputs of a µC; a series resistor is generally not recommended, as it could help inducted noise
to disturb the inputs. All logic pins enforce a specific behavior and cannot be left unconnected.
Figure 12. Logic input pins.
5V
ESD
PROTECTION
D01IN1329
3.10 EN pins
The ENA, ENB pins are, actually, bi-directional: as an input, with a comparator similar to the other logic input pins (TTL/
CMOS with hysteresis), they control the state of the PowerDMOS. When each of the two pins is at a low logic level,
all the PowerDMOS of the corresponding H-bridge (A or B) are turned off. In L6205 and L6207 the EN pins are also
connected to the two corresponding open drain outputs of the protection circuits that will pull the pins to GND if over
current in the corresponding H-bridge or over temperature conditions exist. In L6206 the open drain outputs are on
separate pins, OCDA and OCDB, allowing easier external diagnostics and overcurrent management. For this reason,
with L6205 and L6207 (and L6206 if EN pins are connected to DIAG pins) EN pins must be driven through a series
resistor of 2.2kΩ minimum (for 5V logic), to allow the voltage at the pin to be pulled below the turn-off threshold.
A capacitor (CEN in Figure 13) connected between each EN pin and GND is also recommended, to reduce the r.m.s.
value of the output current when overcurrent conditions persist (see Over Current Protection section). EN pin must
not be left unconnected.
Figure 13. ENA and ENB input pins.
L6205, L6207
PUSH-PULL
OUTPUT
REN
L6206
OCDA or OCDB
5V
ENA or ENB
5V
PUSH-PULL
OUTPUT
REN
CEN
ENA or ENB
CEN
13/53
AN1762 APPLICATION NOTE
3.11 Programmable off-time Monostable (L6207 ONLY)
The L6207 includes a constant off time PWM current controller for each of the two bridges. The current control
circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the two lower power MOS transistors and ground, as shown in Figure 14. As the current in
the load builds up the voltage across the sense resistor increases proportionally. When the voltage drop across
the sense resistor becomes greater than the voltage at the reference input (VREFA or VREFB) the sense comparator triggers the monostable switching the low-side MOS off. The low-side MOS remain off for the time set
by the monostable and the motor current recirculates in the upper path. When the monostable times out the
bridge will again turn on. Since the internal dead time, used to prevent cross conduction in the bridge, delays
the turn on of the power MOS, the effective off time is the sum of the monostable time plus the dead time.
Figure 14. PWM Current Control Circuitry (L6207 ONLY).
VSA (or B)
TO GATE LOGIC
BLANKING TIME
MONOSTABLE
1µs
FROM THE
LOW-SIDE
GATE DRIVERS
5mA
2H
S
Q
(0)
(1)
MONOSTABLE
RESET
1H
BLANKER
IOUT
R
OUT2A(or B)
DRIVERS
+
DEAD TIME
-
DRIVERS
+
DEAD TIME
OUT1A(or B)
+
5V
LOADA
(or B)
2.5V
SENSE
COMPARATOR
2L
1L
+
COMPARATOR
OUTPUT
RCA(or B)
COFF
ROFF
-
SENSEA(or B)
VREFA(or B)
RSENSE
D02IN1352
Figure 15 shows the typical operating waveforms of the output current, the voltage drop across the sensing resistor, the RC pin voltage and the status of the bridge. Immediately after the low-side Power MOS turns on, a
high peak current flows through the sensing resistor due to the reverse recovery of the freewheeling diodes. The
L6207 provides a 1µs Blanking Time tBLANK that inhibits the comparator output so that this current spike cannot
prematurely re-trigger the monostable.
14/53
AN1762 APPLICATION NOTE
Figure 15. PWM Output Current Regulation Waveforms (L6207 ONLY).
IOUT
VREF
RSENSE
tON
tOFF
tOFF
1µs tBLANK
VSENSE
1µs tBLANK
VREF
Slow Decay
0
Slow Decay
tRCRISE
VRC
tRCRISE
5V
2.5V
tRCFALL
tRCFALL
1µs tDT
1µs tDT
ON
OFF
SYNCHRONOUS RECTIFICATION
D02IN1351
B
C
D
A
B
C
D
Figure 16 shows the magnitude of the Off Time tOFF versus COFF and ROFF values. It can be approximately
calculated from the equations:
tRCFALL = 0.6 · ROFF · COFF
tOFF = tRCFALL + tDT = 0.6 · ROFF · COFF + tDT
where ROFF and COFF are the external component values and tDT is the internally generated Dead Time with:
20KΩ ≤ ROFF ≤ 100KΩ
0.47nF ≤ COFF ≤ 100nF
tDT = 1µs (typical value)
Therefore:
tOFF(MIN) = 6.6µs
tOFF(MAX) = 6ms
These values allow a sufficient range of tOFF to implement the drive circuit for most motors.
The capacitor value chosen for COFF also affects the Rise Time tRCRISE of the voltage at the pin RCA (or RCB).
The Rise Time tRCRISE will only be an issue if the capacitor is not completely charged before the next time the
monostable is triggered. Therefore, the on time tON, which depends by motors and supply parameters, has to
15/53
AN1762 APPLICATION NOTE
be bigger than tRCRISE for allowing a good current regulation by the PWM stage. Furthermore, the on time tON
can not be smaller than the minimum on time tON(MIN).
t O N > t O N ( MIN ) = 1.5µ s (typ. value)
t O N > t RCRISE – t DT
tRCRISE = 600 · COFF
3.11.1 Off-time Selection and minimum on-time (L6207 ONLY)
Figure 16 also shows the lower limit for the on time tON for having a good PWM current regulation capacity. It
has to be said that tON is always bigger than tON(MIN) because the device imposes this condition, but it can be
smaller than tRCRISE - tDT. In this last case the device continues to work but the off time tOFF is not more constant.
So, small COFF value gives more flexibility for the applications (allows smaller on time and, therefore, higher
switching frequency), but, the smaller is the value for COFF, the more influential will be the noises on the circuit
performance.
Figure 16. Off-time selection and minimum on-time (L6207 ONLY).
4
1 . 10
R = 100 kΩ
R = 47 kΩ
R = 20 kΩ
to f f [ u s]
3
1 . 10
100
10
1
0.1
1
10
100
10
100
Coff [nF]
to n ( m in ) [ u s ]
100
10
1
0.1
1
Coff [nF]
16/53
AN1762 APPLICATION NOTE
3.11.2 Slow Decay Mode (L6207 ONLY)
Figure 17 shows the operation of the bridge in the Slow Decay mode. At the start of the off time, the lower power
MOS is switched off and the current recirculates around the upper half of the bridge. Since the voltage across
the coil is low, the current decays slowly. After the dead time the upper power MOS is operated in the synchronous rectification mode. When the monostable times out, the lower power MOS is turned on again after some
delay set by the dead time to prevent cross conduction.
Figure 17. Slow Decay Mode Output Stage Configurations
A) ON TIME
B) 1µs DEAD TIME
D01IN1336
C) SYNCHRONOUS
RECTIFICATION
D) 1µs DEAD TIME
In some conditions (short off-time, very low regulated current, high motor winding L / R) the system may need
an on-time shorter than 1.5µs. In these cases the PWM current controller can loose the regulation.
Figure 18 shows the operation of the circuit in this condition. When the current first reaches the threshold, the
bridge is turned off for a fixed time and the current decays. During the following on-time current increases above
the threshold, but the bridge cannot be turned off until the minimum 1.5µs on-time expires. Since current increases more in each on-time than it decays during the off-time, it keeps growing during each cycle, with steady
state asymptotic value set by duty-cycle and load DC resistance: the resulting peak current will be
Ipk = VS · D / RLOAD,
where D = tON / (tON + tOFF) is the duty-cycle and RLOAD is the load DC resistance.
Figure 18. Minimum on-time can cause the PWM controller to loose the regulation (L6207 ONLY).
m inim um t ON
is about 1.5 µs
V ref / R SENSE
needed t ON is less
than 1.5 µs
17/53
AN1762 APPLICATION NOTE
3.12 Over Current Protection
To implement an Over Current (i.e. short circuit) Protection, a dedicated Over Current Detection (OCD) circuitry
(see Figure 19 for a simplified schematic) senses the current in each high side. Power DMOS are actually made
up with thousands of individual identical cells, each carrying a fraction of the total current flowing. The current
sensing element, connected in parallel to the Power DMOS, is made only with few such cells, having a 1:N ratio
compared to the power DMOS. The total drain current is split between the output and the sense element according to the cell ratio. Sensed current is, then, a small fraction of the output current and will not contribute
significantly to power dissipation.
Figure 19. Over Current Detection simplified circuitry.
L6205, L6207
OUT1A VSA OUT2A
POWER SENSE
1 cell
HIGH SIDE DMOSs OF
THE BRIDGE A
I1A
POWER DMOS
n cells
TO GATE
LOGIC
µC or LOGIC
POWER DMOS
n cells
POWER SENSE
1 cell
+
I1A / n
OCD
COMPARATOR
+5V
I2A
I2A / n
(I1A+I2A) / n
REN
ENA
CEN
IREF
INTERNAL
OPEN-DRAIN
RDS(ON)
40Ω TYP.
OVER TEMPERATURE
L6206
OUT1A VSA OUT2A
POWER SENSE
1 cell
HIGH SIDE DMOSs OF
THE BRIDGE A
I1A
µC or LOGIC
POWER DMOS
n cells
TO GATE
LOGIC
+5V
RENA
I1A / n
I2A / n
(I1A+I2A) / n
CENA
IREF
INTERNAL
OPEN-DRAIN
OCDA
POWER DMOS
n cells
+
OCD
COMPARATOR
ENA
I2A
RDS(ON)
40Ω TYP.
+
OVER
TEMPERATURE
IREF
PROGCLA,
RCLA.
18/53
1.2V
POWER SENSE
1 cell
AN1762 APPLICATION NOTE
This sensed current is compared to an internally generated reference (adjustable through the external resistors
RCLA and RCLB for L6206) to detect an over current condition. An internal open drain mosfet turns on when the
sum of the currents in the bridges 1A and 2A or 1B and 2B reaches the threshold (5.6A typical value for L6205
and L6207; adjustable through the external resistors RCLA and RCLB for L6206); in L6205 and L6207 the open
drain are internally connected to the EN pins; with L6206 OCD pins should be connected to EN pins to allow the
protection working. To ensure an over current protection, connect these pins to an external RC network (see
Figure 19).
Figure 20 shows the device operating in overcurrent condition (short to ground). When an over current is detected the internal open drain mosfet pull the EN pin to GND switching off all 4 power DMOS of the interested
bridge and allowing the current to decay. Under a persistent over current condition, like a short to ground or a
short between two output pins, the external RC network on the EN pin (see Figure 19) reduces the r.m.s. value
of the output current by imposing a fixed disable-time after each over current occurrence. The values of REN
and CEN are selected to ensure proper operation of the device under a short circuit condition. When the current
flowing through the high side DMOS reaches the OCD threshold (5.6 A typ. for L6205 and L6207, adjustable for
L6206), after an internal propagation delay (tOCD(ON)) the open drain starts discharging CEN. When the EN pin
voltage falls below the turn-off threshold (VTH(OFF)) all the Power DMOS turn off after the internal propagation
delay (tD(OFF)EN). The current begins to decay as it circulates through the freewheeling diodes. Since the DMOS
are off, there is no current flowing through them and no current to sense so the OCD circuit, after a short delay
(tOCD(OFF)), switches the internal open drain device off, and REN can charge CEN. When the voltage at EN pin
reaches the turn-on threshold (VTH(ON)), after the tD(ON)EN delay, the DMOS turn on and the current restarts.
Even if the maximum output current can be very high, the external RC network provides a disable time (tDISABLE)
to ensure a safe r.m.s. value (see Figure 20).
Figure 20. Over Current Operation.
tDELAY
tDISABLE
tOCD(ON)
Output Current
Output Current
IS OVER
tEN(FALL)
tD(OFF)EN
VTH(OFF)
tOCD(OFF)
tD(ON)EN
tDISABLE
EN
VTH(ON)
VEN(LOW)
EN
tEN(RISE)
The maximum value reached by the current depends on its slew-rate, so on the short circuit nature and supply
voltage, and on the total intervention delay (tDELAY). It can be noticed that after the first current peak, the maximum value reached by the output current becomes lower, because the capacitor on EN pins is discharged starting from a lower voltage, resulting in a shorter tDELAY.
The following approximate relations estimate the disable time and the first OCD intervention delay after the short
circuit (worst case).
19/53
AN1762 APPLICATION NOTE
The time the device remains disabled is:
t DISABLE = tOCD (OFF ) + t EN ( RISE ) + t D (ON ) EN
where
t EN ( RISE ) = REN ⋅ C EN ⋅ ln
VDD − VEN ( LOW )
VDD − VTH (ON )
VEN(LOW) is the minimum voltage reached by the EN pin, and can be estimated with the relation:
VEN ( LOW ) = VTH ( OFF ) ⋅ e
−
t D ( OFF ) EN + tOCD ( OFF )
ROPDR ⋅C EN
The total intervention time is
t DELAY = tOCD ( ON ) + t EN ( FALL ) + t D ( OFF ) EN
where
t EN ( FALL ) = ROPDR ⋅ C EN ⋅ ln
VDD
VTH ( OFF )
tOCD(OFF), tOCD(ON), tD(ON)EN, tD(OFF)EN, and ROPDR are device intrinsic parameters, VDD is the pull-up voltage
applied to REN.
The external RC network, CEN in particular, must be chosen obtaining a reasonable fast OCD intervention (short
tDELAY) and a safe disable time (long tDISABLE). Figure 21 shows both tDISABLE and tDELAY as a function of CEN:
at least 100µs for tDISABLE are recommended, keeping the delay time below 1÷2µs at the same time.
The internal open drain can also be turned on if the device experiences an over temperature (OVT) condition.
The OVT will cause the device to shut down when the die temperature exceeds the OVT threshold
(TJ>165 °C typ.). Since the OVT is also connected directly to the gate drive circuits (see Figure 1 to Figure 3),
all the Power DMOS will shut down, even if EN pin voltage is still over Vth(OFF). When the junction temperature
falls below the OVT turn-off threshold (150 °C typ.), the open drain turn off, CEN is recharged up to VTH(ON) and
then the PowerDMOS are turned on back.
20/53
AN1762 APPLICATION NOTE
Figure 21. Typical disable and delay time as a function of C EN, for several values of REN.
R
3
1 .1 0
EN
= 220 kΩ
R
EN
= 100 kΩ
R
R
tDISABLE [µs]
R
EN
= 47 kΩ
= 33 kΩ
EN
= 10 kΩ
EN
100
10
1
1
10
C
EN
100
[n F ]
tDELAY [µs]
10
1
0 .1
1
10
C
EN
100
[n F ]
3.13 Adjusting the Over Current Detection trip point (L6206 ONLY)
The L6206 allows the user to set the Over Current Detection threshold separately for the two full bridges connecting two resistors (RCL) to pins PROGCLA and PROGCLB. The OCD threshold (ISOVER) follows the equations:
– ISOVER = 5.6A ±30% at -25 °C < Tj < 125 °C if RCL = 0 Ω (PROGCL connected to GND)
22100
– ISOVER = ---------------- ±10% at -25 °C < Tj < 125 °C if 5K Ω < RCL < 40k Ω
R CL
Figure 22 shows the OCD threshold versus RCL value in the range from 5kΩ to 40kΩ.
21/53
AN1762 APPLICATION NOTE
Figure 22. Output Current Detection Threshold versus RCL Value (L6206 ONLY)
5
4.5
4
3.5
3
I SO VER
[A]
2.5
2
1.5
1
0.5
0
5k
10k
15k
20k
25k
R C L [Ω ]
30k
35k
40k
The Over Current Detection threshold can also be adjusted through an external reference voltage, as shown in
Figure 23. The external reference voltage source should be able to sink current (about 300 µA maximum). Moreover, if supply voltage is provided to the L6206 before VEXT, and its EN pins are at a high logic level, the device
starts working with minimum OCD threshold (actually the capacitor placed at the bottom of RCL allows a short
start-up time with higher OCD threshold). VEXT can also be obtained through a PWM output of a µC, adding a
series resistor to obtain a low-pass filter.
The OCD threshold (ISOVER) follows the equation:
ISOVER =
18416.7
( 1.2V – Ve xt -)
---------------------------------------------------------±10%,
R CL
at -25 °C < Tj < 125 °C
if 0.5 A < ISOVER < 4.5 A
Figure 23. Adjusting the OCD Threshold through an external reference voltage (L6206 ONLY)
L6206
PROGCLA
RCL
Vext = 0 ÷ 1.2 V
22/53
AN1762 APPLICATION NOTE
3.14 Paralleling two Full Bridges
3.14.1Paralleling two Full Bridges to get a single Full Bridge
The outputs of L6205, L6206, L6207 can be paralleled to increase the output current capability or reduce the
power dissipation in the device at a given current level. It must be noted, however, that the internal wire bond
connections from the die to the power or sense pins of the package must carry current in both of the associated
half bridges (see Figure 24). When the two halves of one full bridge (for example OUT1A and OUT2A) are connected in parallel, the peak current rating is not increased since the total current must still flow through one bond
wire on the power supply or sense pin. In addition, the over current detection senses the sum of the current in
the upper devices of each bridge (A or B) so connecting the two halves of one bridge in parallel does not increase the over current detection threshold.
Figure 24. VS and SENSE pins maximum current handling
2.8A rms
5.6A peak
SOURCED Current
OCD Threshold:
IOUT1 + IOUT2 = 5.6A typ.
VSA
VSA
SINKED:
IOUT1 + IOUT2 = ISENSE < 2.8A rms, 5.6A pk.
OVER
CURRENT
DETECTION
OUT1A
OUT1A
OUT2A
OUT2A
SOURCED:
2.8A rms
5.6A peak
IOUT1 + IOUT2 = ISUPPLY < 2.8A rms, 5.6A pk.
BRIDGE A
SENSEA
BRIDGE A
SENSEA
2.8A rms
5.6A peak
SOURCED Current
OCD Threshold:
IOUT1 + IOUT2 = 5.6A typ.
VSB
VSB
SINKED:
IOUT1 + IOUT2 = ISENSE < 2.8A rms, 5.6A pk.
OVER
CURRENT
DETECTION
OUT1B
OUT1B
OUT2B
OUT2B
SOURCED:
2.8A rms
5.6A peak
IOUT1 + IOUT2 = ISUPPLY < 2.8A rms, 5.6A pk.
BRIDGE B
SENSEB
BRIDGE B
SENSEB
This configuration has to be used when two separate loads are driven, since the ICs has only two ENABLE inputs, one for the full bridge A and the other for the bridge B. In this case pulling to GND one of the two ENABLE
pins will disable only one load (see Figure 25).
This configuration can also be used if a 5.6A OCD threshold is desired (instead of 11.2A).
Half Bridge 1 and the Half Bridge 2 of the Bridge A are connected in parallel and the same done for the Bridge
B as shown in Figure 25. In this configuration, the peak current for each half bridge is still limited by the bond
wires for the supply and sense pins so the dissipation in the device will be reduced, but the peak current rating
is not increased. Using this configuration with L6206, two separate resistors connected to pins PROGCLA and
PROGCLB must be used. With L6207, two separate RC network should be used on RC pins. When two different
loads are driven (see Figure 25) by the two equivalent half bridges, two separate sensing resistors are needed,
while if the two equivalent half bridges drive two separate loads, they must be connected from the OUT pins to
VS (see Figure 25) to make the PWM current control working properly.
In this configuration, the resulting bridge has the following characteristics (typical values).
- Equivalent Device: FULL BRIDGE
- RDS(ON) 0.15Ω Typ. Value @ TJ = 25°C
- 2.8A max RMS Load Current
- 5.6A OCD Threshold
23/53
AN1762 APPLICATION NOTE
Figure 25. Parallel connection with lower Overcurrent Threshold (L6205, L6206, L6207)
+
VS
8-52VDC
VSA
VSB
C2
C1
POWER
GROUND
-
D1
CBOOT
SIGNAL
GROUND
RP
D2
VCP
VBOOT
SENSEB
OUT1A
OUT2A
OUT1B
LOAD
+
VS
8-52VDC
OUT2B
VSA
C1
VSB
C2
POWER
GROUND
-
SIGNAL
GROUND
RP
VCP
D2
VBOOT
SENSEB
OUT1A
OUT2A
LOAD
OUT1B
LOAD
OUT2B
GND
GND
GND
GND
VSA
VSB
C2
C1
11
19
12
1
3
2
8
9
4
10
18
16
7
13
15
L6205
D1
CBOOT
SIGNAL
GROUND
RP
D2
VCP
5
RSENSE
RSENSE
VS
LOAD
VBOOT
SENSEB
OUT1A
OUT2A
VS
OUT1B
LOAD
OUT2B
VREFA
VREF = 0 ÷ 1 V
ENB
REN
EN
VREFB
IN1A
IN2A
INA
IN1B
INB
IN2B
GND
GND
GND
GND
20
17
4
22
9
14
OCDA
ENA
OCDB
REN
ENB
EN
15
CEN
3
10
1
5
2
21
11
8
12
16
24
18
6
7
IN1A
INA
IN2A
IN1B
INB
IN2B
PROGCLA
RCLA
19
L6206
20
13
PROGCLB
RCLB
23
17
ENA
ENB
REN
EN
CEN
22
CP
SENSEA
1
15
2
3
11
10
12
5
16
21
15
6
8
5
IN1A
IN2A
INA
IN1B
INB
IN2B
GND
GND
GND
GND
16
CA
4
24
RCA
RA
CB
13
L6207
24/53
6
14
POWER
GROUND
-
ENA
CEN
CP
SENSEA
+
VS
8-52VDC
20
23
D1
CBOOT
14
CP
SENSEA
LOAD
17
9
RCB
RB
AN1762 APPLICATION NOTE
For some applications the recommended configuration is Half Bridge 1 of Bridge A paralleled with the Half
Bridge 1 of the Bridge B, and the same for the Half Bridges 2 as shown in Figure 26.
Figure 26. Parallel connection for higher current (L6205 and L6206 ONLY)
+
VS
8-52VDC
VSA
VSB
C2
C1
POWER
GROUND
-
CBOOT
RP
VCP
VBOOT
SENSEB
OUT1A
OUT2A
LOAD
OUT1B
OUT2B
VSA
C1
VSB
C2
D1
CBOOT
RP
D2
ENA
19
1
12
3
2
8
9
4
10
18
16
15
7
13
L6205
6
5
20
17
9
VCP
22
4
CP
VBOOT
SENSEA
SENSEB
OUT1A
OUT2A
LOAD
ENB
REN
EN
CEN
14
POWER
GROUND
-
SIGNAL
GROUND
11
CP
D2
SENSEA
+
VS
8-52VDC
14
20
D1
SIGNAL
GROUND
17
OUT1B
OUT2B
GND
GND
GND
GND
23
IN1A
IN1
IN2A
IN1B
IN2B
IN2
GND
GND
GND
GND
OCDB
ENB
OCDA
ENA
REN
EN
CEN
15
3
1
10
2
IN1A
IN1
IN2A
5
21
11
8
12
16
24
18
7
IN2B
IN2
PROGCLA
RCLA
19
6
IN1B
L6206
13
PROGCLB
RCLB
This configuration cannot be used with L6207, because of its internal PWM current controllers that work separately for bridge A and bridge B. Using this configuration with the L6207 may damage the device.
In this configuration the resulting Bridge has the following characteristics (typical values).
- Equivalent Device: FULL BRIDGE
- RDS(ON) 0.15Ω Typ. Value @ TJ = 25°C
- 5.6A max RMS Load Current
- 11.2A OCD Threshold
It should be noted that using two separate loads for the two equivalent half bridges the maximum current cannot
be sourced or sinked simultaneously by the two equivalent half bridges (for example to drive two separate
loads), due to the 5.6 A maximum current limit for VS and SENSE pins (see Figure 24). When a single load is
driven (see Figure 26) RCLA and RCLB resistors connected to PROGCL pins of L6206 should have the same
value.
25/53
AN1762 APPLICATION NOTE
3.14.2Paralleling the four Half Bridges to get a single Half Bridge
It is also possible to parallel the four Half Bridges to obtain a simple Half Bridge as shown in Figure 27.
This configuration cannot be used with L6207, because of its internal PWM current controllers that work separately for bridge A and bridge B. Using this configuration with the L6207 may damage the device.
The resulting half bridge has the following characteristics (typical values).
- Equivalent Device: HALF BRIDGE
- RDS(ON) 0.075Ω Typ. Value @ TJ = 25°C
- 5.6A max RMS Load Current
- 11.2A OCD Threshold
With L6206 RCLA and RCLB resistors connected to PROGCL pins must have the same value.
Figure 27. Paralleling the four Half Bridges (L6205 and L6206 ONLY)
+
VS
8-52VDC
VSA
C1
VSB
C2
POWER
GROUND
-
CBOOT
RP
D2
VCP
VBOOT
SENSEB
OUT1A
OUT2A
LOAD
OUT1B
OUT2B
VSA
C1
VSB
C2
POWER
GROUND
-
SIGNAL
GROUND
D1
CBOOT
RP
D2
VCP
VBOOT
SENSEB
OUT1A
OUT2A
LOAD
OUT1B
OUT2B
GND
GND
GND
GND
ENB
ENA
19
1
12
2
3
8
9
4
10
18
16
15
7
13
REN
EN
CEN
L6205
20
6
5
4
17
23
22
9
CP
SENSEA
26/53
11
CP
SENSEA
+
VS
8-52VDC
14
20
D1
SIGNAL
GROUND
17
14
IN1A
IN2A
IN
IN1B
IN2B
GND
GND
GND
GND
OCDA
ENA
OCDB
ENB
REN
EN
CEN
15
3
10
1
5
2
21
11
8
12
16
24
18
7
IN2A
IN
IN1B
IN2B
PROGCLA
RCLA
19
6
IN1A
L6206
13
PROGCLB
RCLB
AN1762 APPLICATION NOTE
3.15 Power Management
Even when operating at current levels well below the maximum ratings of the device, the operating junction temperature must be kept below 125 °C.
Figure 28 shows the IC dissipated power versus the r.m.s. load current, in the case of a single IC driving two
loads (for instance 2 DC motors or a two-phase stepper motor) or a single IC, with two full bridges paralleled
(see Paralleling two Full Bridges section) driving one load (for instance 1 DC motor or one phase of a twophase stepper motor) and assuming the supply voltage is 24V.
Figure 28. IC Dissipated Power versus Output Current.
10
8
2 Full Bridges
driving two loads
6
PD [W]
4
2
2 Full Bridges Paralleled
driving one load
0
0
0.5
1
1.5
IOUT [A]
2
2.5
3
No PWM
fSW = 30 kHz (synch. slow decay)
3.15.1 Maximum output current vs. selectable devices
Figure 29 reports a performance comparison between different devices of the PowerSPIN family, for different
packages and in paralleled configuration, with the following assumptions:
- Each equivalent full bridge drives a load.
- Supply voltage: 24 V; Switching frequency: 30 kHz.
- Tamb = 25 °C, TJ = 125 °C.
- Maximum RDS(ON) (taking into account process spread) has been considered, @ 125 °C.
- Maximum quiescent current IQ (taking into account process spread) has been considered.
- PCB is a FR4 with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 µm) for
SO and PowerDIP packages (D, N suffixes).
- PCB is a FR4 with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 µm), 16
via holes and a ground layer for the PowerSO package (PD suffix).
- For each device configuration (on the x axis) y axis reports the maximum output (load) current.
- 2 x ’device’ means that the two loads are driven by two equivalent full bridges obtained paralleling two full bridges for each of the two IC used. The current reported in Figure 29 is the maximum output current an equivalent
full bridge (a paralleled IC).
27/53
AN1762 APPLICATION NOTE
Figure 29. Maximum output current vs. selectable devices.
3 .0 0
2 .5 0
2 .0 0
Load Current 1 .5 0
[A]
1 .0 0
D
XN
2xL
622X
PD
2xL
620X
D
2xL
620 X
N
2xL
620X
PD
2xL
622
6 22X
2xL
X PD
L62 0
XN
L620
XD
L 620
XN
X PD
L6 22
L622
L622
XD
0 .5 0
3.15.2 Power Dissipation Formulae for different sequences
Figure 30 to Figure 33 are screenshots of a spreadsheet that helps calculating power dissipation in specified
conditions (application and motor data), and estimates the resulting junction temperature for a given package
and copper area available on the PCB [4].
The model assumes that the device is driving a two-phase bipolar stepper motor and that a PWM current control
with slow decay recirculation technique is implemented (L6207 integrates the PWM controller); it considers power dissipation during the on-time and the off-time, rise and fall time (when a phase change occurs) considering
the operating sequence (Normal, Wave or Half Step Mode), the switching losses and the quiescent current power dissipation.
28/53
AN1762 APPLICATION NOTE
Figure 30. Definition of parameters for the three different sequences. The current in only one phase
is shown.
NORMAL
I
WAVE
I
T
T/2
∆I
Ipk
∆I
Iload
Ipk
Iload
t
Tr
Tload
t
Tf
Tr
Tload
Tf
HALF STEP
I
T
∆I
Iload
Ipk
t
Tr
Tload
Tf
Figure 31. Input Data.
Input Data
Device Input Values
Maximum Drain-Source ON Resistance
Ron
=
5.60E-01
[Ohm]
Maximum diode voltage
Vd
=
1.20E+00
[V]
Iq
=
5.50E-03
[mA]
Quiescent Current
Average Value between High-Side and Low-Side
Motor Input Values
Maximum BEMF Voltage
Vb
=
1.50E+01
[V]
Motor Inductance
Lm
=
7.90E-03
[H]
Rm
=
6.60E+00
[Ohm]
Motor Resistance
Application Input Values
Supply Voltage
Vs
=
2.40E+01
[V]
Peak Current
Ipk
=
1.00E+00
[A]
Off-Time
tOFF
=
1.50E-05
[s]
Step Frequency
fCK
=
1.00E+03
[Hz]
Sensing Resistance
Rs
=
5.00E-01
[Ohm]
Decay Type
SLOW
-
"SLOW" = Synchronous Slow Decay
"FAST" = Quasi-Synchronous Fast decay
Stepping sequence
WAVE
-
"NORMAL", "HALF" or "WAVE"
29/53
AN1762 APPLICATION NOTE
Figure 32. Power Dissipation formulae and results.
Result
PowerDMOS
Commutation
Time
Rise Time
Tcom = 9.60E-08
[s]
Vs / (250V/µs)
Trise =
[s]
( – Ipk ⋅ Rm – 2 ⋅ Ipk ⋅ Ron – Ipk ⋅ Rs + Vs )
Lm
– ln --------------------------------------------------------------------------------------------------------------- ⋅ ---------------------------------------------Vs
Rm + Rs + 2Ron
4.03E-04
Vs
Lm
– ln ------------------------------------------------------------------------------------------------------------- ⋅ ------------------------------------------------------( Ipk ⋅ Rm + 2 ⋅ Ipk ⋅ Ron + Ipk ⋅ Rs + Vs ) ( Rm + 2 ⋅ Ron + Rs )
Fall Time
Tfall =
3.16E-04
NORMAL Mode
[s]
( Vs – 2 ⋅ Vd )
Lm
– ln ------------------------------------------------------------------------------------------- ⋅ ---------------------------( Ipk ⋅ Rm + Ipk ⋅ Rs + Vs – 2 ⋅ Vd ) ( Rm + Rs )
Vb / Vs
HALF or WAVE
Mode
Sync. Slow Decay
Duty Cycle
D=
6.25E-01
-
Switching
Frequency
fSW =
2.50E+04
[Hz]
(1-D) / tOFF
Current Ripple
∆I =
2.85E-02
[A]
(Vs - Vb)*D / (Lm* fSW)
Period
T=
2.00E-03
[s]
2 / fCK
4 / fCK
2 / fCK
NORMAL Mode
HALF Mode
WAVE Mode
Tload = 5.97E-04
[s]
T-Trise-Tfall
(3/4)T-rise
(T/2)-Trise
NORMAL Mode
HALF Mode
WAVE Mode
∆I
Ipk – ----2
Load Time
Average Current during
Load Time
I=
9.86E-01
[A]
r.m.s. Current
during Load
Time
Irms =
9.86E-01
[A]
Rise Time
Dissipating
Energy
Erise =
1.50E-04
[J]
2
∆I
Ipk ⋅ ( Ipk – ∆I ) + ------3
2 Trise
2Ron ⋅ Ipk ⋅ --------------3
2 Tfall
2Ron ⋅ Ipk ⋅ ------------3
MORMAL Mode
Fall Time
Dissipating
Energy
Efall = 3.62E-04
[J]
( – Vs + 2 ⋅ Vd )
2 ⋅ V d Tfall ⋅ -------------------------------------- +
( Rm + Rs )
– T f al l
1 – exp ---------------- ⋅ ( Rm + Rs )
Lm
m ⋅ ( Ipk ⋅ Rm + Ipk ⋅ Rs + V s – 2 ⋅ V d ) ⋅ -------------------------------------------------------------------------------2
( Rm + Rs )
Load Time
Diss. Energy
30/53
Eload = 6.50E-05
[J]
2Ron · Irms2 · Tload
HALF or WAVE
Mode
Sync. Slow Decay
AN1762 APPLICATION NOTE
Commutatiion
Time
Dissipating Pw
Ecom = 6.78E-05
[J]
2Vs · I · Tcom · Tload · fSW
Quiescent
Dissipating Pw
Pq = 1.32E-01
[W]
Vs · Iq
[W]
2
--- ·(Erise + Efall + Eload + Ecom) + Pq
T
Total Dissipating Power
P=
1.36E+00
Figure 33. Thermal Data inputs and results.
Input Data
Package
SO24
Copper Area
4.0
Copper Area is on
Ground Layer
Am bient Tem perature
1÷10 sq. cm
Sam e side of the device
N/A
50
-25 ÷ 100 ºC
Results
Therm al Resistance
Junction to Am bient
53.36
ºC / W
Therm al Resistance
Junction to Pins / Slug
14.00
ºC / W
Estim ated Junction
Tem perature
122.66
ºC
Estim ated
Pins / Slug Tem perature
103.60
31/53
AN1762 APPLICATION NOTE
4
APPLICATION EXAMPLE (L6207)
Application Data
Motor Data
Rotation Speed:
300 rpm (fCK = 1kHz)
Winding Resistance:
6.6Ω
Winding peak Current: 1A
Winding Inductance:
7.9mH
Maximum Ripple:
50mA
Step Angle:
1.8°/step
Supply Voltage:
24V ±5%
Maximum BEMF at 300rpm: 15V
Sequence:
Wave Mode
4.1 Decay mode, sensing resistors and reference voltage.
Referring to approximated formulae in Figure 32, it's possible to calculate the Duty-Cycle (D), the Switching Frequency (fSW), the Current Ripple (∆I). With a 15 µs off-time, we will have:
D ≅ 63%, fSW ≅ 25kHz, ∆I ≅ 29mA. The on-time is tON = D / fSW ≅ 25µs, which is far from the minimum allowed
(1.5µs), so slow decay can be used.
The bulk capacitor need to withstand at least 24V + 5% + 25% ≅ 32V. A 50V capacitor will be used. Allowing a
voltage ripple of 200mV, the capacitor ESR should be lower than 200mV / 1A = 200mΩ; the AC current capability should be about 1A.
Providing a reference voltage of 0.5V, 0.5Ω sensing resistor are needed. The resistors power rating is about PR
≅ Irms2 · RSENSE · D ≅ 0.32W. Two 1Ω - 0.25W - 1% resistors in parallel are used. The charge pump uses recommended components (1N4148 diodes, ceramic capacitors and a 100Ω resistor to reduce EMI).
R = 18kΩ, C = 1.2 nF are connected to the RC pins, obtaining tOFF ≅ 16µs. On the EN pins 5.6nF capacitors
have been placed, and the pins are driven by the µC through 100kΩ resistors. With these values, in case of
short circuit between two OUT pins or an OUT pin and GND, the PowerDMOS turns off after about 1µs, and
tDISABLE ≅ 240µs.
Figure 34. Application Example.
2-Phase
Stepper Motor
1N4148
1N4148
220nF 50V
Ceramic
10nF 50V
Ceramic
100Ω
0.25W
OUT 1A OUT 2A OUT 1B OUT2B
VBOO T
CP
VSA
100µF 50V
ESR
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