HCF4014BEY

HCF4014B SYNCHRONOUS PARALLEL OR SERIAL IN/SERIAL OUT 8 - STAGE STATIC SHIFT REGISTER ■ ■ ■ ■ ■ ■ ■ ■ MEDIUM SPEED OPERATION : 12 MHz (Typ.) At VDD = 10V FULLY STATIC OPERATION 8 MASTER-SLAVE FLIP-FLOPS PLUS OUTPUT BUFFERING AND CONTROL GATING QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DESCRIPTION The HCF4014B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. This device is an 8-stage parallel or serial input/ serial output register having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM" inputs to each register stage. Each register stage is a D-type, master-slave flip-flop in addition to an output from stage 8, "Q" outputs are also available ) (s t c u d o r P e t e l o ) s ( ct DIP SOP PACKAGE TUBE t e l o DIP SOP u d o r P e ORDER CODES HCF4014BEY HCF4014BM1 T&R HCF4014M013TR s b O from stages 6 and 7. Parallel as well as serial entry is made into the register synchronously with the positive clock line transition. In this device, entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of he clock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line. s b O PIN CONNECTION October 2002 1/10 HCF4014B IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 7, 6, 5, 4, 13, 14, 15, 1 11 PI1 to PI8 NAME AND FUNCTION 8 SERIAL IN PARALLEL/ SERIAL CONTROL CLOCK Q6, Q7, Q8 VSS 16 VDD 9 10 2, 3, 12 Parallel Input Serial Input Parallel/Serial Input Control Clock Input Buffered Outputs Negative Supply Voltage u d o TRUTH TABLE CLOCK SERIAL INPUT PARALLEL/ SERIAL CONTROL PI - 1 X 1 0 X 1 X 1 X 1 0 0 1 ct 0 du X LOGIC DIAGRAM e t e ol s b O 2/10 o r P X r P e Q1 (INTERNAL) Qn 0 0 0 1 0 1 0 1 1 1 1 1 X X 0 Qn - 1 X X 1 Qn - 1 X X Q1 Qn PI - n t e l o s b O 1 0 ) (s ) s ( ct Positive Supply Voltage 0 HCF4014B ABSOLUTE MAXIMUM RATINGS Symbol VDD Parameter Value Supply Voltage VI DC Input Voltage II DC Input Current Unit -0.5 to +22 V -0.5 to VDD + 0.5 ± 10 V mA 200 100 mW mW Top Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature -55 to +125 °C Tstg Storage Temperature -65 to +150 °C PD Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. ) s ( ct RECOMMENDED OPERATING CONDITIONS Symbol VDD u d o Parameter Supply Voltage VI Input Voltage Top Operating Temperature tr, tf Input Rise and Fall Time (PI-1 ... PI-8) e t e l VDD = 5V o s b Pr Value Unit 3 to 20 V 0 to VDD V -55 to 125 °C 0 to 1000 µs O ) s ( t c u d o r P e t e l o s b O 3/10 HCF4014B DC SPECIFICATIONS Test Condition Symbol IL Parameter Quiescent Current VOH 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 High Level Output Voltage VOL Low Level Output Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH Output Drive Current IOL Output Sink Current II CI Input Leakage Current Input Capacitance 0/5 0/5 0/10 0/15 0/5 0/10 0/15 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 0/18 |IO| VDD (µA) (V)