HCF4022B
OCTAL COUNTER WITH 8 DECODED OUTPUTS
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MEDIUM SPEED OPERATION :
10 MHz (Typ.) at VDD = 10V
FULLY STATIC OPERATION
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT SPECIFIED UP TO
20V
5V, 10V AND 15V PARAMETRIC RATINGS
INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
The HCF4022B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
The HCF4022B is 4-stage Johnson counter
having 8 decoded outputs. Inputs include a
CLOCK, a RESET, and a CLOCK INHIBIT signal.
Schmitt trigger action in the clock input circuit
provides pulse shaping that allows unlimited clock
input pulse rise and fall times. This counter is
advanced one count at the positive clock signal
transition if the CLOCK INHIBIT signal is low.
Counter advanced via the clock line is inhibited
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DIP
SOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
HCF4022BEY
HCF4022BM1
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HCF4022M013TR
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when the CLOCK INHIBIT signal is high. A high
RESET signal clears the counter to its zero count.
Use of the Johnson decade-counter configuration
permits high speed operation, 2-input decimal
decode gating and spike-free decoded outputs.
Anti-lock gating is provided, thus assuring proper
counting sequence. The decoded outputs are
normally low and go high only at their respective
decoded time slot. Each decoded output remains
high for one full clock cycle. A CARRY - OUT
signal completes one cycle every 8 clock input
cycles and is used to ripple-clock the succeeding
device in a multi-device counting chain.
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PIN CONNECTION
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September 2001
1/11
HCF4022B
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
2, 1, 3, 7, 11,
4, 5, 10
6, 9
14
13
15
12
8
SYMBOL
0 to 7
NC
CLOCK
CLOCK
INHIBIT
RESET
CARRY OUT
VSS
NAME AND FUNCTION
Decoded Output
Not Connected
Clock Input
Clock Inhibit Input
Reset Input
Carry Output
Negative Supply Voltage
TRUTH TABLE
FUNCTIONAL DIAGRAM
CLOCK
INHIBIT
RESET
X
X
H
L
X
L
X
H
L
CLOCK
L
L
H
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H
X : Don’t Care
Qn : No Change
LOGIC DIAGRAM
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This logic diagram has not be used to estimate propagation delays
2/11
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DECODED
OUTPUT
Qn
Qn
Qn+1
L
Qn
L
Qn
L
Qn+1
HCF4022B
TIMING CHART
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ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
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Supply Voltage
VI
DC Input Voltage
II
DC Input Current
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Parameter
Top
Power Dissipation per Package
Power Dissipation per Output Transistor
Operating Temperature
Tstg
Storage Temperature
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Value
Unit
-0.5 to +22
V
-0.5 to VDD + 0.5
± 10
V
mA
200
100
mW
mW
-55 to +125
°C
-65 to +150
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
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RECOMMENDED OPERATING CONDITIONS
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Symbol
VDD
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Top
Supply Voltage
Input Voltage
Operating Temperature
Parameter
Value
Unit
3 to 20
V
0 to VDD
V
-55 to 125
°C
3/11
HCF4022B
DC SPECIFICATIONS
Test Condition
Symbol
IL
Parameter
Quiescent Current
0/5
0/10
0/15
0/20
0/5
0/10
0/15
5/0
10/0
15/0
High Level Output
Voltage
VOH
Low Level Output
Voltage
VOL
High Level Input
Voltage
VIH
Low Level Input
Voltage
VIL
Output Drive
Current
IOH
0/5
0/5
0/10
0/15
0/5
0/10
0/15
Output Sink
Current
IOL
Input Leakage
Current
Input Capacitance
II
CI
VO
(V)
VI
(V)
0.5/4.5
1/9
1.5/13.5
4.5/0.5
9/1
13.5/1.5
2.5
4.6
9.5
13.5
0.4
0.5
1.5
|IO| VDD
(µA) (V)
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