L6226
DMOS dual full bridge driver
Datasheet - production data
Undervoltage lockout
Integrated fast free wheeling diodes
3
Applications
62
3RZHU62
Bipolar stepper motor
Dual or quad DC motor
Features
Description
Operating supply voltage from 8 to 52 V
2.8 A output peak current (1.4 A DC)
RDS(on) 0.73 typ. value at TJ = 25 °C
Operating frequency up to 100 kHz
Programmable high side overcurrent detection
and protection
Diagnostic output
Paralleled operation
Cross conduction protection
Thermal shutdown
The L6226 is a DMOS dual full bridge designed
for motor control applications, realized in
multipower-BCD technology, which combines
isolated DMOS power transistors with CMOS and
bipolar circuits on the same chip. Available in
PowerSO36 and SO24 (20+2+2) packages, the
L6226 features thermal shutdown and a nondissipative overcurrent detection on the high side
power MOSFETs plus a diagnostic output that
can be easily used to implement the overcurrent
protection.
Figure 1. Block diagram
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This is information on a product in full production.
DocID9452 Rev 5
1/29
www.st.com
Contents
L6226
Contents
11
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1
Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2
Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3
Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 12
4.4
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
Paralleled operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output current capability and IC power dissipation. . . . . . . . . . . . . . . . . . . . . . . . 21
7
Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.1
PowerSO36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.2
SO24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9
Ordering codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/29
DocID9452 Rev 5
L6226
Maximum ratings
1
Maximum ratings
1.1
Absolute maximum ratings
Table 1. Absolute maximum ratings
Symbol
VS
Parameter
Value
Unit
60
V
60
V
-
-0.3 to +10
V
-
-0.3 to +7
V
VS + 10
V
-0.3 to +7
V
-1 to +4
V
Pulsed supply current (for each
VS pin), internally limited by the VSA = VSB = VS; tPULSE < 1 ms
overcurrent protection
3.55
A
RMS supply current
(for each VS pin)
VSA = VSB = VS
1.4
A
Storage and operating
temperature range
-
-40 to 150
°C
Supply voltage
Test conditions
VSA = VSB = VS
Differential voltage between
VOD
OCDA,
OCDB
VSA, OUT1A, OUT2A, SENSEA VSA = VSB = VS = 60 V;
and VSB, OUT1B, OUT2B,
VSENSEA = VSENSEB = GND
SENSEB
OCD pins voltage range
PROGCLA,
PROGCL pins voltage range
PROGCLB
VBOOT
Bootstrap peak voltage
VIN,VEN
Input and enable voltage range -
VSENSEA,
VSENSEB
IS(peak)
IS
Tstg, TOP
1.2
Voltage range at pins SENSEA
and SENSEB
VSA = VSB = VS
-
Recommended operating conditions
Table 2. Recommended operating conditions
Symbol
VS
VOD
VSENSEA,
VSENSEB
Parameter
Supply voltage
Test conditions
Min.
Max.
Unit
8
52
V
-
52
V
(pulsed tW < trr)
(DC)
-6
-1
6
1
V
V
VSA = VSB = VS
Differential voltage between
VSA, OUT1A, OUT2A, SENSEA VSA = VSB = VS;
and VSB, OUT1B, OUT2B,
VSENSEA = VSENSEB
SENSEB
Voltage range at pins SENSEA
and SENSEB
IOUT
RMS output current
-
-
1.4
A
fsw
Switching frequency
-
-
100
kHz
DocID9452 Rev 5
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29
Maximum ratings
1.3
L6226
Thermal data
Table 3. Thermal data
Symbol
SO24
PowerSO36
Unit
15
-
°C/W
-
2
°C/W
Rth-j-amb1 Maximum thermal resistance junction-ambient 1
52
-
°C/W
Rth-j-amb1 Maximum thermal resistance junction-ambient 2
-
36
°C/W
Rth-j-amb1 Maximum thermal resistance junction-ambient 3
-
16
°C/W
Rth-j-amb2 Maximum thermal resistance junction-ambient 4
78
63
°C/W
Rth-j-pins
Description
Maximum thermal resistance junction-pins
Rth-j-case Maximum thermal resistance junction-case
4/29
DocID9452 Rev 5
L6226
2
Pin connections
Pin connections
Figure 2. Pin connections
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1. The slug is internally connected to pins 1,18,19 and 36 (GND pins).
Table 4. Pin description
Pin no.
Name
Type
Function
SO24
PowerSO36
1
10
IN1A
Logic input Bridge A logic input 1.
2
11
IN2A
Logic input Bridge A logic input 2.
3
12
SENSEA
Power
supply
Bridge A source pin. This pin must be
connected to power ground directly or
through a sensing power resistor.
Bridge A overcurrent detection and thermal
protection pin. An internal open drain
Open drain
transistor pulls to GND when overcurrent
output
on bridge A is detected or in case of
thermal protection.
4
13
OCDA
5
15
OUT1A
Power
output
6, 7, 18, 19
1, 18, 19, 36
GND
GND
8
22
OUT1B
Power
output
DocID9452 Rev 5
Bridge A output 1.
Signal ground terminals. In SO packages,
these pins are also used for heat
dissipation toward the PCB.
Bridge B output 1.
5/29
29
Pin connections
L6226
Table 4. Pin description (continued)
Pin no.
Name
SO24
Function
Bridge B overcurrent detection and thermal
protection pin.An internal open drain
Open drain
transistor pulls to GND when overcurrent
output
on bridge B is detected or in case of
thermal protection.
9
24
OCDB
10
25
SENSEB
11
26
IN1B
Logic input Bridge B input 1
12
27
IN2B
Logic input Bridge B input 2
Power
supply
Bridge B overcurrent level programming.
A resistor connected between this pin and
Ground sets the programmable current
limiting value for the bridge B. By
connecting this pin to Ground the
maximum current is set.This pin cannot be
left non-connected.
28
PROGCLB
14
29
ENB
15
30
VBOOT
Supply
voltage
Bootstrap voltage needed for driving the
upper power MOSFETs of both bridge A
and bridge B.
16
32
OUT2B
Power
output
Bridge B output 2.
17
33
VSB
Power
supply
Bridge B power supply voltage. it must be
connected to the supply voltage together
with pin VSA.
20
4
VSA
Power
supply
Bridge A power supply voltage. it must be
connected to the supply voltage together
with pin VSB.
21
5
OUT2A
Power
output
Bridge A output 2.
22
7
VCP
Output
Charge pump oscillator output.
23
8
ENA
9
PROGCLA
R pin
Bridge B source pin. This pin must be
connected to power ground directly or
through a sensing power resistor.
13
24
6/29
Type
PowerSO36
Bridge B enable. LOW logic level switches
Logic input OFF all power MOSFETs of bridge B. If not
used, it has to be connected to +5 V.
Bridge A enable. LOW logic level switches
Logic input OFF all power MOSFETs of bridge A. If not
used, it has to be connected to +5 V.
R pin
DocID9452 Rev 5
Bridge A overcurrent level programming.
A resistor connected between this pin and
Ground sets the programmable current
limiting value for the bridge A. By
connecting this pin to ground the maximum
current is set.This pin cannot be left nonconnected.
L6226
Electrical characteristics
3
Electrical characteristics
TA = 25 °C, VS = 48 V, unless otherwise specified
Table 5. Electrical characteristics
Symbol
VSth(ON)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Turn-on threshold
-
5.8
6.3
6.8
V
VSth(OFF) Turn-off threshold
-
5
5.5
6
V
Quiescent supply current
All bridges OFF;
TJ = -25 °C to 125 °C(1)
-
5
10
m
Thermal shutdown temperature
-
-
165
-
°C
TJ = 25 °C
-
1.47
1.69
TJ = 125 °C(1)
-
2.35
2.70
EN = Low; OUT = VS
-
-
2
mA
EN = Low; OUT = GND
-0.3
-
-
mA
Forward ON voltage
ISD = 2.8 A, EN = LOW
-
1.15
1.3
V
trr
Reverse recovery time
If = 1.4 A
-
300
-
ns
tfr
Forward recovery time
-
-
200
-
ns
IS
Tj(OFF)
Output DMOS transistors
RDS(ON)
IDSS
High-side + low-side switch ON
resistance
Leakage current
Source drain diodes
VSD
Logic input
VIL
Low level logic input voltage
-
-0.3
-
0.8
V
VIH
High level logic input voltage
-
2
-
7
V
IIL
Low level logic input current
GND logic input voltage
-10
-
-
µA
IIH
High level logic input current
7 V logic input voltage
-
-
10
µA
Vth(ON)
Turn-on input threshold
-
-
1.8
2.0
V
Vth(OFF)
Turn-off input threshold
-
0.8
1.3
-
V
Vth(HYS)
Input threshold hysteresis
-
0.25
0.5
-
V
Switching characteristics
tD(on)EN
Enable to out turn ON delay time(2)
ILOAD = 1.4 A, resistive load
500
-
800
ns
tD(on)IN
Input to out turn ON delay time
ILOAD = 1.4 A, resistive load
(dead time included)
-
1.9
-
µs
Output rise time(2)
ILOAD = 1.4 A, resistive load
40
250
ns
ILOAD = 1.4 A, resistive load
500
800
1000
ns
tRISE
time(2)
tD(off)EN
Enable to out turn OFF delay
tD(off)IN
Input to out turn OFF delay time
ILOAD = 1.4 A, resistive load
500
800
1000
ns
Output fall time(2)
ILOAD = 1.4 A, resistive load
40
-
250
ns
tFALL
DocID9452 Rev 5
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29
Electrical characteristics
L6226
Table 5. Electrical characteristics (continued)
Symbol
Parameter
Test conditions
tdt
Dead time protection
-
fCP
Charge pump frequency
-25 °C < Tj < 125 °C
Min.
Typ .
Max.
Unit
0.5
1
-
µs
-
0.6
1
MHz
Overcurrent detection
Is over
ROPDR
Input supply overcurrent detection
threshold
-25 °C V@
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NN:
5 (1
N
N:
5 (1
5 (1
N:
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N:
N
5 (1
N:
N
& ( 1 >Q)@
14/29
DocID9452 Rev 5
L6226
Circuit description
Figure 13. tDELAY versus CEN (VDD = 5 V)
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Thermal protection
In addition to the overcurrent detection, the L6226 integrates a thermal protection for
preventing the device destruction in case of junction overtemperature. It works sensing the
die temperature by means of a sensible element integrated in the die. The device switch-off
when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis (typ.
value).
DocID9452 Rev 5
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29
Application information
5
L6226
Application information
A typical application using L6226 is shown in Figure 14. Typical component values for the
application are shown in Figure 8. A high quality ceramic capacitor in the range of 100 to
200 nF should be placed between the power pins (VSA and VSB) and ground near the
L6226 to improve the high frequency filtering on the power supply and reduce high
frequency transients generated by the switching. The capacitors connected from the
ENA/OCDA and ENB/OCDB nodes to ground set the shut down time for the Bridge A and
Bridge B respectively when an over current is detected (see overcurrent protection). The
two current sources (SENSEA and SENSEB) should be connected to power ground with a
trace length as short as possible in the layout. To increase noise immunity, unused logic
pins are best connected to 5 V (high logic level) or GND (low logic level) (see pin
description).
It is recommended to keep power ground and signal ground separated on PCB.
Table 8. Component values for typical application
16/29
Component
Value
Component
Value
C1
100 F
D1
1N4148
C2
100 nF
D2
1N4148
CBOOT
220 nF
RCLA
5 k
CP
10 nF
RCLB
5 k
CENA
5.6 nF
RENA
100 k
CENB
5.6 nF
RENB
100 k
CREF
68 nF
-
-
DocID9452 Rev 5
L6226
Application information
Figure 14. Typical application
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Paralleled operation
6
L6226
Paralleled operation
The outputs of the L6226 can be paralleled to increase the output current capability or
reduce the power dissipation in the device at a given current level. It must be noted,
however, that the internal wire bond connections from the die to the power or sense pins of
the package must carry current in both of the associated half bridges. When the two halves
of one full bridge (for example OUT1A and OUT2A) are connected in parallel, the peak
current rating is not increased since the total current must still flow through one bond wire on
the power supply or sense pin. In addition the overcurrent detection senses the sum of the
current in the upper devices of each bridge (A or B) so connecting the two halves of one
bridge in parallel does not increase the over current detection threshold.
For most applications the recommended configuration is half bridge 1 of bridge A paralleled
with the half bridge 1 of the bridge B, and the same for the half bridges 2 as shown in
Figure 15. The current in the two devices connected in parallel will share very well since the
RDS(ON) of the devices on the same die is well matched.
When connected in this configuration the over current detection circuit, which senses the
current in each bridge (A and B), will sense the current in upper devices connected in
parallel independently and the sense circuit with the lowest threshold will trip first. With the
enables connected in parallel, the first detection of an over current in either upper DMOS
device will turn of both bridges. Assuming that the two DMOS devices share the current
equally, the resulting over current detection threshold will be twice the minimum threshold
set by the resistors RCLA or RCLB in Figure 15. It is recommended to use RCLA = RCLB.
In this configuration the resulting Bridge has the following characteristics.
18/29
Equivalent device: full bridge
RDS(ON) 0.37 typ. value at TJ = 25°C
2.8 A max. RMS load current
5.6 A max. OCD threshold
DocID9452 Rev 5
L6226
Paralleled operation
Figure 15. Parallel connection for higher current
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To operate the device in parallel and maintain a lower overcurrent threshold, half bridge 1
and the half bridge 2 of the bridge A can be connected in parallel and the same done for the
bridge B as shown in Figure 16. In this configuration, the peak current for each half bridge is
still limited by the bond wires for the supply and sense pins so the dissipation in the device
will be reduced, but the peak current rating is not increased.
When connected in this configuration the overcurrent detection circuit, senses the sum of
the current in upper devices connected in parallel. With the enables connected in parallel,
an over current will turn of both bridges.
Since the circuit senses the total current in the upper devices, the overcurrent threshold is
equal to the threshold set the resistor RCLA or RCLB in Figure 16. RCLA sets the threshold
when outputs OUT1A and OUT2A are high and resistor RCLB sets the threshold when
outputs OUT1B and OUT2B are high.
It is recommended to use RCLA = RCLB.
In this configuration, the resulting bridge has the following characteristics.
Equivalent device: full bridge
RDS(ON) 0.37 typ. value at TJ = 25 °C
1.4 A max. RMS load current
2.8 A max. OCD threshold
DocID9452 Rev 5
19/29
29
Paralleled operation
L6226
Figure 16. Parallel connection with lower overcurrent threshold
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It is also possible to parallel the four half bridges to obtain a simple half bridge as shown in
Figure 17. In this configuration the, the overcurrent threshold is equal to twice the minimum
threshold set by the resistors RCLA or RCLB in Figure 17. It is recommended to use
RCLA = RCLB.
The resulting half bridge has the following characteristics.
20/29
Equivalent device: half bridge
RDS(ON) 0.18 typ. value at TJ = 25 °C
2.8 A max RMS load current
5.6 A max OCD threshold
DocID9452 Rev 5
L6226
Paralleled operation
Figure 17. Paralleling the four half bridges
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Output current capability and IC power dissipation
In Figure 18 and Figure 19 are shown the approximate relation between the output current
and the IC power dissipation using PWM current control driving two loads, for two different
driving types:
One full bridge ON at a time (Figure 18) in which only one load at a time is energized.
Two full bridges ON at the same time (Figure 19) in which two loads at the same time
are energized.
For a given output current and driving type the power dissipated by the IC can be easily
evaluated, in order to establish which package should be used and how large must be the
on-board copper dissipating area to guarantee a safe operating junction temperature
(125 °C maximum).
DocID9452 Rev 5
21/29
29
Paralleled operation
L6226
Figure 18. IC power dissipation versus output current with one full bridge ON at a time
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Figure 19. IC power dissipation versus output current with two full bridges ON at the same time
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L6226
7
Thermal management
Thermal management
In most applications the power dissipation in the IC is the main factor that sets the maximum
current that can be deliver by the device in a safe operating condition. Therefore, it has to be
taken into account very carefully. Besides the available space on the PCB, the right package
should be chosen considering the power dissipation. Heat sinking can be achieved using
copper on the PCB with proper area and thickness. Figure 21 and 22 show the junction-toambient thermal resistance values for the PowerSO36 and SO24 packages.
For instance, using a PowerSO package with copper slug soldered on a 1.5 mm copper
thickness FR4 board with 6 cm2 dissipating footprint (copper thickness of 35 µm), the RthJA
is about 35 °C/W. Figure 20 shows mounting methods for this package. Using a multi-layer
board with vias to a ground plane, thermal impedance can be reduced down to 15 °C/W.
Figure 20. Mounting the PowerSO package
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Figure 21. PowerSO36 junction-amb. thermal resistance vs on-board copper area
& :
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: LWK *UR XQ G /D \HU
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+ R OH V
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Figure 22. SO24 junction-ambient thermal resistance versus on-board copper area
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V TFP
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Package information
8
L6226
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
8.1
PowerSO36 package information
Figure 23. PowerSO36 package outline
1
1
D
H
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L6226
Package information
Table 9. PowerSO36 package mechanical data
Dimensions (mm)
Symbol
Min.
Typ.
Max.
A
-
-
3.60
a1
0.10
-
0.30
a2
-
-
3.30
a3
0
-
0.10
b
0.22
-
0.38
c
0.23
-
0.32
D (1)
15.80
-
16.00
D1
9.40
-
9.80
E
13.90
-
14.50
e
-
0.65
-
e3
-
11.05
-
E1 (1)
10.90
-
11.10
E2
-
-
2.90
E3
5.80
-
6.20
E4
2.90
-
3.20
G
0
-
0.10
H
15.50
-
15.90
h
-
-
1.10
L
0.80
-
1.10
N
10°(max.)
-
-
S
8 °(max.)
-
-
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Package information
8.2
L6226
SO24 package information
Figure 24. SO24 package outline
&
Table 10. SO24 package mechanical data
Dimensions
Symbol
mm
Min.
Typ.
Max.
Min.
Typ.
Max.
A
2.35
-
2.65
0.093
-
0.104
A1
0.10
-
0.30
0.004
-
0.012
B
0.33
-
0.51
0.013
-
0.020
C
0.23
-
0.32
0.009
-
0.013
D
15.20
-
15.60
0.598
-
0.614
E
7.40
-
7.60
0.291
-
0.299
e
-
1.27
-
-
0.050
-
H
10.0
-
10.65
0.394
-
0.419
h
0.25
-
0.75
0.010
-
0.030
L
0.40
-
1.27
0.016
-
0.050
-
0.004
k
ddd
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inch
0° (min.), 8° (max.)
-
-
0.10
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L6226
9
Ordering codes
Ordering codes
Table 11. Ordering information
Order codes
Package
L6226PD
PowerSO36
L6226D
SO24
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Revision history
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Revision history
Table 12. Document revision history
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Date
Revision
Changes
Sep-2003
1
Initial release
04-Mar-2008
2
Minor revision due to revalidation process, no content change
29-Sep-2009
3
Updated Table 1 on page 3
21-Oct-2009
4
Updated Figure 4 on page 9
03-Oct-2018
5
Removed PowerDIP24 package from the whole document.
Removed “Tj“ from Table 2 on page 3.
Minor modifications throughout document.
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IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
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