L6569D

L6569 L6569A HIGH VOLTAGE HALF BRIDGE DRIVER WITH OSCILLATOR s s s s s HIGH VOLTAGE RAIL UP TO 600V BCD OFF LINE TECHNOLOGY INTERNAL BOOTSTRAP DIODE STRUCTURE 15.6V ZENER CLAMP ON VS DRIVER CURRENT CAPABILITY: - SINK CURRENT = 270mA - SOURCE CURRENT = 170mA VERY LOW START UP CURRENT: 150 A µ UNDER VOLTAGE LOCKOUT WITH HYSTERESIS PROGRAMMABLE OSCILLATOR FREQUENCY DEAD TIME 1.25µs dV/dt IMMUNITY UP TO ±50V/ns ESD PROTECTION Minidip SO8 s s s s s s ORDERING NUMBERS: L6569 L6569D L6569A L6569AD be programmed using external resistor and capacitor. The internal circuitry of the device allows it to be driven also by external logic signal. The output drivers are designed to drive external nchannel power MOSFET and IGBT. The internal logic assures a dead time [typ. 1.25µs] to avoid crossconduction of the power devices. Two version are available: L6569 and L6569A. They differ in the low voltage gate driver start up sequence. DESCRIPTION The device is a high voltage half bridge driver with built in oscillator. The frequency of the oscillator can BLOCK DIAGRAM H.V. CVS 1 Source CHARGE PUMP BIAS REGULATOR VS RF RF CF COMP VS RHV BOOT 8 LEVEL SHIFTER 7 HVG CBOOT 2 BUFFER HIGH SIDE DRIVER 6 OUT LOAD CF 3 COMP VS LOGIC LOW SIDE DRIVER 5 LVG GND 4 D94IN058D June 2000 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/13 L6569 L6569A ABSOLUTE MAXIMUM RATINGS Symbol IS (*) VCF V LVG VOUT V HVG VBOOT VBOOT/OUT dV BOOT/dt dVOUT/dt Tstg Tj Tamb Supply Current Oscillator Resistor Voltage Low Side Switch Gate Output High Side Switch Source Output High Side Switch Gate Output Floating Supply Voltage Floating Supply vs OUT Voltage VBOOT Slew Rate (Repetitive) VOUT Slew Rate (Repetitive) Storage Temperature Junction Temperature Ambient Temperature (Operative) Parameter Value 25 18 14.6 -1 to VBOOT - 18 -1 to VBOOT 618 18 ± 50 ± 50 -40 to 150 -40 to 150 -40 to 125 Unit mA V V V V V V V/ns V/ns °C °C °C (*)The device has an internal zener clamp between GND and VS (typical 15.6V).Therefore the circuit should not be driven by a DC low impedance power source. Note: ESD immunity for pins 6, 7 and 8 is guaranteed up to 900 V (Human Body Model) THERMAL DATA Symbol Rth j-amb Parameter Thermal Resistance Junction-Ambient Max Minidip 100 SO8 150 Unit ° C/W RECOMMENDED OPERATING CONDITIONS Symbol VS VBOOT VOUT fout Supply Voltage Floating Supply Voltage High Side Switch Source Output Oscillation Frequency Parameter Min. 10 -1 Max. VCL 500 VBOOT -VCL 200 Unit V V V kHz PIN CONNECTION VS RF CF GND 1 2 3 4 D94IN059 8 7 6 5 BOOT HVG OUT LVG 2/13 L6569 L6569A PIN FUNCTION N° 1 2 Pin VS RF Description Supply input voltage with internal clamp [typ. 15.6V] Oscillator timing resistor pin. A buffer set alternatively to VS and GND can provide current to the external resistor RF connected between pin 2 and 3. Alternatively, the signal on pin 2 can be used also to drive another IC (i.e. another L6569 to drive a full H-bridge) Oscillator timing capacitor pin. A capacitor connected between this pin and GND fixes (together with RF) the oscillating frequency Alternatively an external logic signal can be applied to the pin to drive the IC. Ground Low side driver output. The output stage can deliver 170mA source and 270mA sink [typ.values]. Upper driver floating reference High side driver output. The output stage can deliver 170mA source and 270mA sink [typ.values]. Bootstrap voltage supply. It is the upper driver floating supply. The bootstrap capacitor connected between this pin and pin 6 can be fed by an internal structure named “bootstrap driver” (a patented structure). This structure can replace the external bootstrap diode. 3 CF 4 5 6 7 8 GND LVG OUT HVG BOOT ELECTRICAL CHARACTERISTCS (VS = 12V; VBOOT - VOUT = 12V; Tj = 25°C; unless otherwise specified.) Symbol VSUVP VSUVN VSUVH VCL I SU Iq IBOOTLK IOUTLK IHVG SO IHVG SI ILVG SO ILVG S I 5 8 6 7 Pin 1 Parameter VS Turn On Threshold VS Turn Off Threshold VS Hysteresis VS Clamping Voltage Start Up Current Quiescent Current Leakage Current BOOT pin vs GND Leakage Current OUT pin vs GND High Side Driver Source Current High Side Driver Sink Current Low Side Driver Source Current Low Side Driver Sink Current IS = 5mA VS < VSUVN VS > VSUVP VBOOT = 580V VOUT = 562V VHVG = 6V VHVG = 6V VLVG = 6V VLVG = 6V 110 190 110 190 175 275 175 275 Test Condition Min. 8.3 7.3 0.7 14.6 Typ. 9 8 1 15.6 150 500 Max. 9.7 8.7 1.3 16.6 250 700 5 5 Unit V V V V µA µA µA µA mA mA mA mA 3/13 L6569 L6569A ELECTRICAL CHARACTERISTCS (continued) Symbol VRFON VRF OFF VCFU VCFL td DC 3 Pin 2 Parameter RF High Level Output Voltage RF Low Level Output Voltage CF Upper Threshold CF Lower Threshold Internal Dead Time Duty Cycle, Ratio Between Dead Time + Conduction Time of High Side and Low Side Drivers On resistance of Boostrap LDMOS Boostrap Voltage before UVLO 1 6 Average Current from Vs Oscillation Frequency VS = 8.2 No Load, fs = 60KHz RT = 12K; CT = 1nF 57 2.5 Test Condition IRF = 1mA IRF = -1mA Min. VS -0.05 Typ. Max. VS -0.2 200 Unit V mV V V µs 50 7.7 3.80 0.85 0.45 8 4 1.25 0.5 8.2 4.3 1.65 0.55 R ON VBC IAVE fout 120 3.6 1.2 60 1.5 63 Ω V mA kHz OSCILLATOR FREQUENCY The frequency of the internal oscillator can be programmed using external resistor and capacitor. The nominal oscillator frequency can be calculated using the following equation: 1 1 fOSC = ----------------------------------------- = ----------------------------------------2 ⋅ RF ⋅ CF ⋅ I n2 1.3863 ⋅ RF ⋅ C F Where RF and CF are the external resistor and capacitor. The device can be driven in ”shut down” condition keeping the CF pin close to GND, but some cares have to be taken: 1. When CF is to GND the high side driver is off and the low side is on 2. The forced discharge of the oscillator capacitor CF must not be shorter than 1us: a simple way to do this is to limit the current discharge with a resistive path imposing R · CF >1µs (see fig.1) Figure 1. 1 2 R fault signal CF GNDM RF 3 4 8 7 6 5 4/13 L6569 L6569A Bootstrap Function The L6569 has an internal Bootstrap structure that enables the user to avoid the external diode needed, in similar devices, to perform the charge of the bootstrap capacitor that, in turns, provide an appropriate driving to the Upper External Mosfet. The operation is achieved with an unique structure (patented) that uses a High Voltage Lateral DMOS driven by an internal charge pump (see Block Diagram) and synchronized, with a 50 nsec delay, with the Low Side Gate driver (LVG pin), actually working as a synchronous rectifier . The charging path for the Bootstrap capacitor is closed via the Lower External Mosfet that is driven ON (i.e. LVG High) for a time interval: T C = RF · CF · In2 → 1.1 · RF · CF starting from the time the Supply Voltage VS has reached the Turn On Voltage (VSUVP = 9 V typical value). After time T1 (see waveform Diagram) the LDMOS that charges the Bootstrap Capacitor, is on with a RON=120Ω (typical value). In the L6569A a different start up procedure is followed (see waveform Diagram). The Lower External Mosfet is drive OFF until VS has reached the Turn On Threshold (VSUVPp), then again the TC time interval starts as above. Being the LDMOS used to implement the bootstrap operation a ”bi-directional” switch the current flowing into the BOOT pin (pin 8) can lead an undue stress to the LDMOS itself if a ZERO VOLTAGE SWITCHING operations is not ensured, and then an high voltage is applied to the BOOT pin. This condition can occur, for example, when the load is removed and an high resistive value is placed in series with the gate of the external Power Mos. To help the user to secure his design a SAFE OPERATING AREA for the Bootstrap LDMOS is provided (fig. 7). Let’s consider the steps that should be taken. 1) Calculate the Turn on delay ( td ) of your Lower Power MOS: 1 --------t d = ( R g + Rid ) ⋅ C iss ⋅ ln ---------- VT H – ---------1 VS 2) Calculate the Fall time ( tf ) of your Lower Power MOS: R g + R id t f = ----------------------- ⋅ Q gd VS – VT H where: Rg = External gate resistor Rid = 50Ω, typical equivalent output resistance of the driving buffer (when sourcing current) VTH, C iss and Qgd are Power MOS parameters VS = Low Voltage Supply. 3) Sketch the VBOOT waveform (using log-log scales) starting from the Drain Voltage of the Lower Power MOS (remember to add the Vs, your Low Voltage Supply, value) on the Bootstrap LDMOS SOA . On fig. 8 an example is given where: VS = Low Voltage Supply VHV = High Voltage Supply Rail The VBOOT voltage swing must fall below the curve identified by the actual operating frequency of your application. 5/13 L6569 L6569A DEMO BOARD To allow an easy evaluation of the device, a P.C. board dedicated to lamp ballast application has been designed. Fig.11 shows the electrical schematic of a typical ballast application, while the PC and component layout is given in Fig12. This application has been designed to work with both the 110+/-20%V and the 220 +/- 20%V mains by means of a voltage doubler configuration at the bulk capacitor. The ballast inductance and the operating frequency are especially designed for a 18 W Sylvania De-luxe T/E type bulb. The PTC for preheat at the start up and the two back to back synchronization diodes, makes this application easy to implement and safe in operation. part R1 R2, R3 R4 R5 R6 R7, R9 R8 D1 D2, D3 D4,D5,D6,D7 D8 C1 C2, C5 C3 C4 C6 C7-C8 C9 RV1 Q1, Q2 L1 15ohm 1W 22 ohm 27K 100K 1/2W 47ohm 180K 120K 1/2W 18V zener BYW100-100 1N4007 1N4148 560pF 50V 47µF 250V 4.7 µF 25V 100nF 50V 100nF 250V 8.2nF 630V 470pF 630V PTC 150ohm STD2NB50-1 2.4mH value 6/13 L6569 L6569A Figure 2. Waveforms (L6569) VS VSUVP VBOOT-VOUT VS τ=Ron*CBOOT 4.6V(typ) VCF LVG T1 TC D95IN250B Figure 3. Waveforms (L6569A) VS VSUVP VBOOT-VOUT VS 4.6V(typ) τ=Ron*CBOOT VCF LVG T1 TC D95IN251B 7/13 L6569 L6569A Figure 4. Typical Dead Time vs. Temperature Dependency Dead time [µsec] 1.7 1.6 300 Figure 7. Vboot pin SOA for different Operating Frequency @ Tj = 125°C VBOOT (V) 500 110KHz 70KHz 50KHz 200 20KHz 100 D96IN381 D96IN378A 1.5 1.4 1.3 1.2 1.1 1 0.9 -50 0 50 100 Temperature [C] 150 50 150KHz 30 20 10 20 50 100 200 500 1,000 2,000 Time (ns), from LVG Transition High 5,000 10,000 Figure 5. Typical Frequency vs Temperature Dependency Frequency [KHz] 65 64 63 62 61 60 59 58 57 56 55 D96IN379A Figure 8. Vboo t pin SOA @ Tj = 125°C VBOOT (V) 500 300 200 ACTUAL OPERTATING FREQUENCY 100 VHV+VS D96IN416 50 30 20 td 10 20 50 tf VS 100 200 500 1,000 2,000 Time (ns), from LVG Transition High 5,000 10,000 VBOOT -50 -25 0 25 50 75 Temperature [C] 100 125 Figure 6. Typical and Theoretical Oscillator Frequency vs Resistor Value f (KHz) 150 D96IN380 Figure 9. Typical Rise and Fall Times vs. Load Capacitance time [nsec] 300 250 D96IN417 Theoretical 100 90 80 70 60 50 C=1nF Tr C=330pF C=560pF 200 150 100 Tf 30 50 0 5 6 7 8 9 10 15 20 30 Resistor Value (Kohm) 40 50 20 3 4 5 6 C [nF] For both high and low side buffers @25°C Tamb 0 1 2 8/13 L6569 L6569A Figure 10. Quiescent Current vs. Supply Voltage. Iq (µA) 104 D96IN418 103 102 10 0 2 4 6 8 10 12 14 VS(V) Figure 11. CFL Demoboard 110/220V Inputs. R8 120K 1/2W 4 x 1N4006 D7 220V D6 N R1 15 1W 110V D5 C5 47µF 250V D4 C2 47µF 250V R4 27K 1/4W R5 100K 1/2W C3 4.7µF 25V D8 1N4148 VS RF BOOT HVG C4100nF 50V Q1 STD2NB50-1 R10 10K R9 180K 1/4W L6569 CF C1 560pF 50V R6 47 1/4W OUT LVG GND R2 22 1/4W R3 22 1/4W 1/4W Q2 STD2NB50-1 R7 180K 1/4W BYW100-100 D2 L1=2.4mH C7 8.2nF 630V C6 100nF 250V C8 8.2nF 630V C9 470pF 630V D1 ZPD 18V RV1 PTC 150 350V L1=2.4mH core TH LCC E2006-B4 Ref also VOGH 575 0409200 2.4mH C7-C8=PS8n2J H3 630-2A TH D96IN419B D3 BYW100-100 CFL LAMP SYLVANIA DELUX T/E 18W 9/13 L6569 L6569A Figure 12. PC Board and Components Layout. Component Side Copper Side 10/13 L6569 L6569A DIM. MIN. A a1 a2 a3 b b1 C c1 D (1) E e e3 F (1) L M S 3.8 0.4 4.8 5.8 0.65 0.35 0.19 0.25 0.1 mm TYP. MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 0.026 0.014 0.007 0.010 0.004 MIN. inch TYP. MAX. 0.069 0.010 0.065 0.033 0.019 0.010 0.020 OUTLINE AND MECHANICAL DATA 45° (typ.) 5.0 6.2 1.27 3.81 4.0 1.27 0.6 8 ° (max.) 0.15 0.016 0.189 0.228 0.050 0.150 0.157 0.050 0.024 0.197 0.244 SO8 (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). 11/13 L6569 L6569A DIM. MIN. A a1 B b b1 D E e e3 e4 F I L Z 3.18 7.95 0.51 1.15 0.356 0.204 mm TYP. 3.32 0.020 1.65 0.55 0.304 10.92 9.75 2.54 7.62 7.62 6.6 5.08 3.81 1.52 0.125 0.313 0.045 0.014 0.008 MAX. MIN. inch TYP. 0.131 MAX. OUTLINE AND MECHANICAL DATA 0.065 0.022 0.012 0.430 0.384 0.100 0.300 0.300 0.260 0.200 0.150 0.060 Minidip 12/13 L6569 L6569A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. N o license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics ® 2000 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http:/ /www.st.com 13/13